MC100LVEL59DW ,3.3V ECL Triple 2:1 Multiplexer
MC100LVEL59DW ,3.3V ECL Triple 2:1 MultiplexerAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC100LVEL90 ,Triple ECL to PECL translator
MC100LVEL90DW ,Triple ECL to PECL Translator
MC100LVEL90DW ,Triple ECL to PECL Translator
MC100LVEL90DWR2 ,-3.3V/-5V Triple ECL Input to LVPECL Output TranslatorAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC33199D ,ISO 9141 SERIAL LINK DRIVERELECTRICAL CHARACTERISTICS (continued) (– 40°C ≤ T ≤ 125°C, 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 20 V, un ..
MC33201 ,Amplifiers and Comparators
MC33201 ,Amplifiers and Comparators
MC33201D ,Low Voltage, Rail-to-Rail, Single Operational AmplifierELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)CC EE ACha ..
MC33201DR2 ,Low Voltage, Rail-to-Rail, Single Operational AmplifierELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)CC EE ACh ..
MC33201DR2 ,Low Voltage, Rail-to-Rail, Single Operational AmplifierELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)CC EE ACh ..
MC100LVEL59DW
Triple 2:1 Multiplexer
SEMICONDUCTOR TECHNICAL DATA -
The MC100LVEL59 is a triple 2:1 multiplexer with differential outputs.
The MC100EL59 is pin and functionally equivalent to the MC100LVEL59
but is specified for operation at the standard 100E ECL voltage supply.
The output data of the muxes can be controlled individually via the select
inputs or as a group via the common select input. The flexibile selection
scheme makes the device useful for both data path and random logic
applications. Individual or Common Select Controls 20–Lead SOIC Packaging 500ps Typical Propagation Delays Supports Both Standard and Low Voltage 100K ECL Internal Input Pulldown Resistors >2000V ESD Protection
D1a
Logic Diagram and Pinout: 20–Lead SOIC (Top View)SEL0 SEL1 D2a
VCC Q1 Q1 VCC Q2 Q2 VEE
D0a
VCC Q0
D0b D1bCOM_SEL D2b SEL2
TRUTH TABLE
PIN NAMES
