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MC100LVEL29DW
Dual Differential Data and Clock D Flip-Flop With Set and Reset
SEMICONDUCTOR TECHNICAL DATA " " -"" !"
The MC100LVEL29 is a dual master–slave flip flop. The device
features fully differential Data and Clock inputs as well as outputs. The
MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but
is specified for operation at the standard 100E ECL voltage supply. A VBB
output is provided for AC coupling, refer to the interfacing section of the
ECLinPS Data Book (DL140) for more information on AC coupling ECL
signals. Data enters the master latch when the clock is LOW and
transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are left
open the D input will pull down to VEE and the D input will bias around
VCC/2. The outputs will go to a defined state, however the state will be
random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset inputs.
Note that the Set and Reset inputs cannot both be HIGH simultaneously. 1100MHz Flip–Flop Toggle Frequency 20–lead SOIC Package 580ps Propagation Delays
VBB
Logic Diagram and Pinout: 20-Lead SOIC (Top View)CLK0 D1 CLK1 S0 S1 VCC Q1 Q1 VEE VCC
CLK0 D1D0 CLK1 R1
MC100LVEL29
DC CHARACTERISTICS (VEE = –3.0V to –3.8V; VCC = GND)
TRUTH TABLEZ = LOW to HIGH Transition
PIN NAMES
