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MC100LVE222FAR2
3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver
MC100LVE222
3.3 V�ECL 1:15 Differential
÷1/÷2 Clock Driver
The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be differential or used
single−ended (with VBB output reference bypassed and connected to the
unused input of a pair). Either of two fully differential clock inputs may
be selected. Each of the four output banks of 2, 3, 4, and 6 differential
pairs may be independently configured to fanout 1X or 1/2X of the
input frequency. The LVE222 specifically guarantees low output to
output skew. Optimal design, layout, and processing minimize skew
within a device and from lot to lot.
The fsel pins and CLK_Sel pin are asynchronous control inputs. Any
changes may cause indeterminate output states requiring an MR pulse
to resynchronize any 1/2X outputs.
The device tpd is affected by the quantity of output pairs terminated
with a minimum occurring with only one output pair and increasing
about 10−20 ps for all output pairs. Relative skew distribution is not
affected as more pairs are terminated, but the increased tpd does shift
the entire distribution. Unused output pairs should be left unterminated
(open) to reduce power and switching noise.
The MC100LVE222, as with most ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the LVE222 to
be used for high performance clock distribution in +3.3 V systems.
Designers can take advantage of the LVE222’s performance to
distribute low skew clocks across the backplane or the board. In a PECL
environment series or Thevenin line, terminations are typically used as
they require no additional power supplies. All power supply pins must
be connected. For more information on using PECL, designers should
refer to Application Note AN1406/D. For a SPICE model, refer to
Application Note AN1560/D. 200 ps Part−to−Part Skew 50 ps Output−to−Output Skew Selectable 1x or 1/2x Frequency Outputs ESD Protection: >2 kV HBM, >200 V MM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 2
For Additional Information, refer to Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34 Transistor Count = 684 devices
