MC100EPT25DR2 ,Differential LVECL/ECL to LVTTL Translator2MC100EPT25NECL DC CHARACTERISTICS V = 3.3 V; V = −5.5 V to −3.0 V; GND = 0.0 V (Note 2)CC EE−40°C ..
MC100EPT25DT ,Differential LVECL/ECL to LVTTL Translator
MC100EPT26D ,1:2 Fanout Differential LVPECL to LVTTL Translatorhttp://onsemi.com2ECLSOIC8EVBTable 1. Configuration ListECLinPS PlusECLinPS LiteDevice Comments C ..
MC100EPT26DR2G , 3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator
MC100EPT26DT ,1:2 Fanout Differential LVPECL to LVTTL Translator3Differential ECLAN1406/DThe traditional choice of a negative power supply for ECL for both the 10H ..
MC100EPT26DTR2G , 3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator
MC33121FN ,LOW VOLTAGE SUBSCRIBER LOOP INTERFACE CIRCUIT**Order this documentby MC33121/DSEMICONDUCTOR TECHNICAL DATA * ** * Thin Film Silicon Monolith ..
MC33121FN ,LOW VOLTAGE SUBSCRIBER LOOP INTERFACE CIRCUITELECTRICAL CHARACTERISTICS(V = – 24 V, V = + 5.0 V, unless otherwise noted. V = V = V = 0 V, T = 25 ..
MC33121P ,LOW VOLTAGE SUBSCRIBER LOOP INTERFACE CIRCUITMAXIMUM RATINGSCharacteristic Symbol Value UnitSupply Voltage Vdc(with respect to V ) V – 60, + 0.5 ..
MC33128 ,POWER MANAGEMENT CONTROLLERELECTRICAL CHARACTERISTICS (V = 4.5 V, C = 33 μF with ESR ≤ 1.6 Ω, C = 4.7 μF with ESR ≤ 4.5 Ω, I = ..
MC33128D ,POWER MANAGEMENT CONTROLLERELECTRICAL CHARACTERISTICS (V = 4.5 V, C = 33 μF with ESR ≤ 1.6 Ω, C = 4.7 μF with ESR ≤ 4.5 Ω, I = ..
MC33128D ,POWER MANAGEMENT CONTROLLERELECTRICAL CHARACTERISTICS (V = 4.5 V, C = 33 μF with ESR ≤ 1.6 Ω, C = 4.7 μF with ESR ≤ 4.5 Ω, I = ..
MC100EPT25DR2
Differential LVECL/ECL to LVTTL Translator
MC100EPT25
-3.3V / -5V�Differential ECL
to +3.3V LVTTL T ranslator
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, −3.3 V to −5.2 V , and ground. The small
outline 8−lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single−ended
input mode. In this mode the VBB output is tied to the D input for a
inverting buffer or the D input for a non−inverting buffer. If used, the
VBB pin should be bypassed to ground with at least a 0.01 �F
capacitor. 1.1 ns Typical Propagation Delay Maximum Frequency > 275 MHz Typical Operating Range: VCC = 3.0 V to 3.6 V;
VEE = −5.5 V to −3.0 V; GND = 0 V 24 mA TTL Outputs Q Output Will Default LOW with Inputs Open or at VEE VBB Output Open Input Default State Safety Clamp on Inputs Pb−Free Packages are Available
