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MC100EP131FA
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
MC10EP131, MC100EP131
3.3V / 5V�ECL Quad D
Flip-Flop with Set, Reset,
and Differential Clock
The MC10/100EP131 is a Quad Master−slaved D flip−flop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flip−flop may be clocked separately by holding Common
Clock (CC) LOW and CC HIGH, then using the differential Clock
Enable inputs for clocking (C0−3, C0−3).
Common clocking is achieved by holding the differential inputs
C0−3 LOW and C0−3 HIGH while using the differential Common
Clock (CC) to clock all four flip−flops. When left floating open, any
differential input will disable operation due to input pulldown resistors
forcing an output default state.
Individual asynchronous resets (R0−3) and an asynchronous set
(SET) are provided.
Data enters the master when both CC and C0−3 are LOW, and
transfers to the slave when either CC or C0−3 (or both) go HIGH.
The 100 Series contains temperature compensation. 460 ps Typical Propagation Delay Maximum Frequency > 3 GHz Typical Differential Individual and Common Clocks Individual Asynchronous Resets Asynchronous Set PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at VEE
