MC10EP51DR2 ,3.3V / 5V ECL D Flip Flop with Reset and Differential Clock3AND8009/DTable 4. ECLinPS Plus Input/Output Selection TableDevice Package A Package B Input ESD In ..
MC10EP51DR2 ,3.3V / 5V ECL D Flip Flop with Reset and Differential Clocklogic diagram. It is unnecessary to include an ESD or8−Lead TSSOP 24package model for the V pins of ..
MC10EP51DT ,3.3V / 5V ECL D Flip Flop with Reset and Differential Clock3AN1672/DSection 2: Translation from Different ECL Operating Mode Drivers to Non ECL ReceiversThe f ..
MC10EP52D ,3.3V / 5V ECL Differential Data and Clock D Flip Flop
MC10EP52DR2 ,3.3V / 5V ECL Differential Data and Clock D Flip FlopAND8009/DECLinPS PlusSPICE Modeling KitPrepared by:Senad Lomigora, Paul ShockmanON Semiconductor B ..
MC10EP52DT ,3.3V / 5V ECL Differential Data and Clock D Flip FlopData enters the master portion of the flip−flop when the clock isLOW and is transferred to the slav ..
MC34064 ,UnderVoltage Sensing CircuitThermal CharacteristicsP Suffix, Plastic PackageP 625 mWMaximum Power Dissipation @ T = 25°C DAR 20 ..
MC34064D ,Undervoltage Sensing Circuitfeatures atrimmed–in–package bandgap reference, and a comparator with TO–226AAP SUFFIXprecise thres ..
MC34064D-005 ,UnderVoltage Sensing CircuitMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
MC34064D-5 ,UNDERVOLTAGE SENSING CIRCUITBlock Diagram CASE 846A1(Micro–8)Input 2 (2)Reset1 8Reset N.C.Input 2 7 N.C.1 (1)3 6N.C. N.C.4 5Gro ..
MC34064D-5 ,UNDERVOLTAGE SENSING CIRCUITMAXIMUM RATINGSRating Symbol Value UnitPower Input Supply Voltage V –1.0 to 10 VinReset Output Volt ..
MC34064D-5G , Undervoltage Sensing Circuit
MC100EP08D-MC100EP08DR2-MC100EP105FA-MC100EP11DR2-MC100EP139-MC100EP16FDT-MC100EP31D-MC100EP35DR2-MC100EP35DT-MC100EP56-MC100EPT21D-MC100EPT21DT-MC100EPT24D-MC100EPT25D-MC100LVEP16D-MC100LVEP16DR2-MC10EP016-MC10EP05DR2-MC10EP105FAR2-MC10EP116FAR2-MC10EP11D-MC
2.5V / 3.3V ECL 1:2 Differential Fanout Buffer
AND8009/D
ECLinPS Plus
SPICE Modeling Kit
Prepared by:
Senad Lomigora, Paul ShockmanON Semiconductor Broadband Applications Engineering
ObjectiveThe objective of this kit is to provide customers with
enough circuit schematic and SPICE parameter information
to allow them to perform system level interconnect
modeling for the current devices of the ECLinPS Plus logic
line, ON Semiconductor’s high performance ECL family.
The kit is not intended to provide information necessary
to perform circuit level modeling on ECLinPS Plus
devices. With packaged gate delays of 160 ps and outputedge rates as low as 80 ps, this family defines the
state−of−the−art in ECL logic. The ECLinPS Plus line is one
of ON Semiconductor’s high performance ECL/PECL
family of products.
Schematic InformationThe kit contains representative input and output
schematics, netlists, and waveform used for the ECLinPS
Plus devices. This application note will be modified as new
devices are added. The subcircuit models such as the input
or output buffer, package, input ESD and output ESD may
be interconnected as subcircuits to simulate specific device
characteristics as shown in Figure 1 below.
diagram in Figure 2 illustrates a typical situation which can
be modeled using the information in this kit.
Typical Input Typical Input
Typical Output
50 �
50 �
Subcircuit Interconnects for Input Pins
Subcircuit Interconnects for Output Pins
Figure 1. Input and Output Pins Interconnects
Figure 2. Typical Application for I/O SPICE Modeling Kit
