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MC33186DH1 , H-Bridge Driver
MC33186DH1 , H-Bridge Driver
MC33186DH-1 , H-Bridge Driver
MC100EL39DW-MC100LVEL39DW
?/4,?/6 Clock Generation Chip
SEMICONDUCTOR TECHNICAL DATA ÷ --
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but
is specified for operation at the standard 100K ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPS Data Book DL140/D). If a single-ended input is
to be used, the VBB output should be connected to the CLK input and
bypassed to ground via a 0.01μF capacitor. The VBB output is designed to
act as the switching reference for the input of the LVEL39 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL39s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL39, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of
a single device. 50ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization 75kΩ Internal Input Pulldown Resistors >2000V ESD Protection Low Voltage VEE Range of –3.0 to –3.8V
CLK
Pinout: 20-Lead SOIC (Top View)CLK MR VCC Q1 Q2 Q2 Q3 Q3 VEE
VCC Q0
DIVSELb VBBVCC NC DIVSELa
PIN DESCRIPTION
FUNCTION TABLEZ = Low-to-High Transition
ZZ = High-to-Low Transition
