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MC100EL11DR2-MC100EL16DR2-MC100EL32DR2-MC100EL58DR2-MC100ELT21D-MC100ELT21DT-MC100ELT22DR2-MC100EP01D-MC100EP16D-MC100EP51DT-MC100EPT22D-MC100EPT23D-MC100EPT26D-MC100LVEL01DT-MC100LVEL05D-MC100LVEL11D-MC100LVEL11DR2-MC100LVEL11DT-MC100LVEL32D-MC100LVEL33D-MC100L
2.5V / 3.3V ECL 1:2 Differential Fanout Buffer
ECLSOIC8EVB
Evaluation Board Manual
for High Frequency SOIC 8
INTRODUCTIONON Semiconductor has developed an evaluation board for
the devices in 8−lead SOIC package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 8−lead SOIC device
samples. The board provides a high bandwidth 50 �
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways, depending on
device under test (See Table 1. Configuration List).
This evaluation board manual contains: Information on 8−lead SOIC Evaluation Board Assembly Instructions Appropriate Lab Setup Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−UpThe 8−lead SOIC evaluation board is implemented in four
layers with split (dual) power supplies (Figure 2.
Evaluation Board Lay−up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the
50 � internal impedance in the oscilloscope as a termination
for ECL devices. The first layer or primary trace layer is
0.008″ thick Rogers RO4003 material, which is designed to
have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground plane and a portion of the
plane is the VEE power plane. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is also 1.0 oz copper ground
plane and a portion of this layer is VCC power plane. The
fourth layer is the secondary trace layer.
Figure 1. Top and Bottom View of the 8−lead SOIC Evaluation Board
