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MC100E241FN
5V ECL 8-Bit Scannable Register
MC100E241
5V�ECL 8›Bit Scannable
Register
The MC100E241 is an 8-bit shiftable register. Unlike a standard
universal shift register such as the E141, the E241 features internal
data feedback organized so that the SHIFT control overrides the
HOLD/LOAD control. This enables the normal operations of HOLD
and LOAD to be toggled with a single control line without the need for
external gating. It also enables switching to scan mode with the single
SHIFT control line.
The eight inputs D0 −D7 accept parallel input data, while S-IN
accepts serial input data when in shift mode. Data is accepted a set-up
time before the positive-going edge of CLK; shifting is also
accomplished on the positive clock edge. A HIGH on the Master Reset
pin (MR) asynchronously resets all the registers to zero.
The 100 Series contains temperature compensation. SHIFT overrides HOLD/LOAD Control 1000 ps Max. CLK to Q Asynchronous Master Reset Pin-Compatible with E141 PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V Internal Input 50 K� Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test ESD Protection: > 1 KV HBM, > 75 V MM Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34 Transistor Count = 529 devices
ORDERING INFORMATION
MARKING
DIAGRAM = Assembly Location = Wafer Lot = Year = Work Week
PLCC−28
FN SUFFIX
CASE 77628
http://†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
