MC10E451FNR2 ,5V ECL 6-Bit D Register Differential Data and Clock
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MC100E151FNR2-MC100E163FN-MC100E163FNR2-MC100E211FN-MC100EL07DR2-mc100EL15D-MC100EL16DT-MC100EL51D-MC100EL56DWR2-MC100ELT22-MC100EP139DWR2-MC100EP16VCD-MC100EP31DR2-MC100EP32DR2-MC100EPT20DR2-MC100EPT24DR2-MC100EPT25DT-MC100EPT622FA-MC100H600-MC100H600FN-MC100H60
Hex Buffer with Enable
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Prepared by: Cleon Petty and Paul Shockman
Product Applications
ON SemiconductorThe application inquiries handled by the Product
Applications gives opportunities to solve customer needs
with new ideas and learn of ways the customer has used our
devices in new applications. A couple of these calls lead to
techniques of designing odd number counters with
synchronous clocks and 50% outputs.
The first technique requires a differential clock, that has
a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd
integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs
and a synchronous clock. The frequency of operations is
limited by Tpd of the driving FF, Setup, and Hold of the extra
FF, and the times cannot exceed one half on the incoming
clock cycle time.
The design begins with producing a odd number counter
(Divide By 3 for this discussion) by any means one wishes
and add a flip flop, and a couple of gates to produce the
desired function. Karnaugh maps usually produce counters
that are lockup immune.
Example:Specify,
Using D type Flop flips and karnaugh maps we find;
Ad = A*B* and Bd = A
(Note: * indicates BAR function)
Figure 1 shows schematic and timing of such a design.
Figure 1. Divide By 3
