MC10H101MEL ,Quad OR/NOR Gate2AN1406/Dreduced while maintaining acceptable manufacturing design. After all the inclusion of ECL ..
MC10H101MELG , Quad OR/NOR Gate
MC10H101ML1 ,Quad OR/NOR GateMAXIMUM RATINGSPLCCCASE 775–02Characteristic Symbol Rating UnitPower Supply (V = 0) V –8.0 to 0 Vdc ..
MC10H101ML1 ,Quad OR/NOR Gate**SEMICONDUCTOR TECHNICAL DATA* The MC10H101 is a quad 2–input OR/NOR gate with one input from eac ..
MC10H101ML1 ,Quad OR/NOR GateLOGIC DIAGRAM— Surge 1004 2Operating Temperature Range T 0 to +75 °CA5Storage Temperature Range — P ..
MC10H102 ,Quad 2-Input NOR GateAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC34072ADR2 ,Single Supply 3V to 44V, Low Input Offset Voltage, Dual Op AmpFeatures SOIC−14D SUFFIX14• Wide Bandwidth: 4.5 MHzCASE 751A1• High Slew Rate: 13 V/s• Fast Settli ..
MC34072ADR2G , Single Supply 3.0 V to 44 V Operational Amplifiers
MC34072ADR2G , Single Supply 3.0 V to 44 V Operational Amplifiers
MC34072AP ,HIGH BANDWIDTH SINGLE SUPPLY OPERATIONAL AMPLIFIERSOrder this document by MC34071/D " ** ** **"** ** *!#HIGH BANDWIDTH** ** *SINGLE SUPPLYQuality bip ..
MC34072D ,Single Supply 3V to 44V, Dual Op AmpMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage (from V to V ) V +44 VEE CC SInput Differenti ..
MC34072DG , Single Supply 3.0 V to 44 V Operational Amplifiers
MC100E116FN-MC100E122FN-MC100E136FN-MC100E142FN-MC100E156FN-MC100E158FN-MC100E310FNR2-MC100E404FN-MC100E431FN-MC100E451FNR2-MC100E452FNR2-MC100EL01D-MC100EL01DT-MC100EL04D-MC100EL11DT-mc100EL14DW-MC100EL33-MC100EL34DR2-MC100EL38DWR2-MC100EL52DR2-MC100EL57-MC
Hex Buffer with Enable
-----
The High Speed Solution for the
CMOS/TTL DesignerPrepared by
Cleon Petty
Todd PearsonECL Applications Engineering
This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices.
IntroductionPECL, or Positive Emitter Coupled Logic, is nothing
more than standard ECL devices run off of a positive power
supply. Because ECL, and therefore PECL, has long been
the “black magic” of the logic world many misconceptions
and falsehoods have arisen concerning its use. However,
many system problems which are difficult to address with
TTL or CMOS technologies are ideally suited to the
strengths of ECL. By breaking through the wall of
misinformation concerning the use of ECL, the TTL and
CMOS designers can arm themselves with a powerful
weapon to attack the most difficult of high speed problems.
It has long been accepted that ECL devices provide the
ultimate in logic speed; it is equally well known that the
price for this speed is a greater need for attention to detail in
the design and layout of the system PC boards. Because this
requirement stems only from the speed performance aspect
of ECL devices, as the speed performance of any logic
technology increases these same requirements will hold. As
can be seen in Table 1 the current state–of–the–art TTL and
CMOS logic families have attained performance levels
which require controlled impedance interconnect for even
relatively short distances between source and load. As a
result system designers who are using state–of–the–art TTL
or CMOS logic are already forced to deal with the special
requirements of high speed logic; thus it is a relatively small
step to extend their thinking from a TTL and CMOS bias to
include ECL devices where their special characteristics will
simplify the design task.
Table 1. Relative Logic Speeds
System Advantages of ECLThe most obvious area to incorporate ECL into an
otherwise CMOS/TTL design would be for a subsystem
which requires very fast data or signal processing. Although
this is the most obvious it may also be the least common.
Because of the need for translation between ECL and
CMOS/TTL technologies the performance gain must be
greater than the overhead required to translate back and forth
between technologies. With typical delays of six to seven
nanoseconds for translating between technologies, a
significant portion of the logic would need to be realized
using ECL for the overall system performance to improve.
However, for very high speed subsystem requirements ECL
may very well provide the best system solution.
Transmission Line DrivingMany of the inherent features of an ECL device make it
ideal for driving long, controlled impedance lines. The low
impedance of the open emitter outputs and high input
impedance of any standard ECL device make it ideally
suited for driving controlled impedance lines. Although
designed to drive 50Ω lines an ECL device is equally adept
at driving lines of impedances of up to 130Ω without
significant changes in the AC characteristics of the device.
Although some of the newer CMOS/TTL families have the
ability to drive 50Ω lines many require special driver circuits
to supply the necessary currents to drive low impedance
transmission interconnect. In addition the large output
swings and relatively fast output slew rates of today’s high
performance CMOS/TTL devices exacerbate the problems
of crosstalk and EMI radiation. The problems of crosstalk
and EMI radiation, along with common mode noise and
signal amplitude losses, can be alleviated to a great degree
with the use of differential interconnect. Because of their
architectures, neither CMOS nor TTL devices are capable of
differential communication. The differential amplifier input
structure and complimentary outputs of ECL devices make
them perfectly suited for differential
