MC100LVEL31DTR2 ,3.3V ECL D-Type Flip-Flop with Set and Reset
MC100LVEL32D ,3.3V ECL ÷2 Dividerhttp://onsemi.com3ECLSOIC8EVBEvaluation Board Assembly Instructions On the top side of the evaluati ..
MC100LVEL32DG , 3.3V ECL ÷2 Divider
MC100LVEL32DG , 3.3V ECL ÷2 Divider
MC100LVEL32DR2G , 3.3V ECL ÷2 Divider
MC100LVEL32DR2G , 3.3V ECL ÷2 Divider
MC33179DG , Low Power, Low Noise Operational Amplifiers
MC33179DR2 ,Low Power, Low Noise Quad Operational AmplifierMC33178, MC33179Low Power, Low NoiseOperational AmplifiersThe MC33178/9 series is a family of high ..
MC33179DTBR2G , Low Power, Low Noise Operational Amplifiers
MC33179DTBR2G , Low Power, Low Noise Operational Amplifiers
MC33179DTBR2G , Low Power, Low Noise Operational Amplifiers
MC33179P ,HIGH OUTPUT CURRENT LOW POWER, LOW NOISE OPERATIONAL AMPLIFIERSOrder this document by MC33178/D** * ** * * * ** * * *HIGH OUTPUT CURRENTThe MC33178/9 series i ..
MC100E112FNR2-MC100E136FN-MC100E164FN-MC100E166FN-MC100EL15DR2-MC100EP016A-MC100EP01DR2-MC100EP210S-MC100EP809FA-MC100EPT24D-MC100H600-MC100H641-MC100LVE164-MC100LVE210FNR2-MC100LVEL01DTR2-MC100LVEL30DW-MC100LVEL31DTR2-MC100LVELT22D-MC100LVELT23DT-MC100LVEP11D-
Hex Buffer with Enable
AND8066/D
Interfacing with ECLinPS
Prepared by: Paul ShockmanON Semiconductor Logic Applications Engineering
STANDARD ECL INTERFACE: DIFFERENTIAL
DRIVER AND RECEIVERA typical Emitter Coupled Logic (ECL) circuit interface
may be defined as a differential driver device sending a paired
set of commentary signals – True and Invert – over a pair of
standard, controlled impedance lines to an ECL differential
receiver device. A typical ECL output line driver consists of
a bipolar transistor in an Emitter Follower configuration with
the collector at VCC power supply rail and the emitter pinned
out. A standard, typical differential ECL receiver consists of
a pair of bipolar transistors in a differential configuration with
the True and Invert signals providing base drives to the two
base inputs. Proper differential levels are specified as Vpp and
VIHCMR. When an input is interconnected as a differential
signal, the DC Single Ended parameters of VIL and VIH do not
apply. Terminations are required to preserve optimum signal
integrity, as shown in Figure 1. The standard, controlled
impedance lines assume a sufficient return current capability.
VCC
VTT
VCC
Figure 1. Standard Differential ECL Interconnect
SINGLE–ENDED INTERFACESignals may be imported as full differential lines or as a
Single–Ended (SE) line interconnection. The SE
interconnection may be seen as a special variation of the
typical differential interface using only one driver source
trace line. This single trace line drives a (Base) input pin of
the receiver, as shown in Figure 2. Although a receiver may
present only a single, dedicate SE input pin instead of a
differential input pair of pins, such a receiver still would have
a differential structure with the unavailable input controlled
by internal circuitry.
VCC
Figure 2. Standard Single–Ended ECL InterconnectVTT
VCC
Single–ended receiver input levels are specified in data
sheets DC CHARACTERISTICS block as VIH and VIL
Parameters. Each temperature has a minimum and
maximum limit pair to VIH and VIL parameters, thus
defining the Single–Ended input swing, Vpp(SE). The
Vpp(SE) ranges from 595 mV to 890 mV , depending on the
temperature and family. The Vpp(SE) limits constitute the
receiver device’s input single–ended sensitivity.
Both output lines of the typical differential output may
drive two independent single–ended receivers separately (see
Figure 3).
Figure 3. Differential Driver with Independent
Standard Single–Ended ReceiversVTT
VCC
VEE
VTT
