MC10EP35D ,3.3V / 5V ECL JK Flip Floplogic diagram. It is unnecessary to include an ESD or8−Lead TSSOP 24package model for the V pins of ..
MC10EP35D ,3.3V / 5V ECL JK Flip Flop2AN1504/D28.6300 NS 31.1300 NS 33.6300 NSCH. 3 = 150.0 mV/DIV TIMEBASE = 500 PS/DIVSTOP = 31.5600 N ..
MC10EP35DR2 ,3.3V / 5V ECL JK Flip Flop3MC10EP35, MC100EP35100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 9.)CC EE–40°C 25°C 85°C ..
MC10EP445 ,3.3V / 5VECL 8-Bit Serial/Parallel Converterfeatures of an ECL device make itrequirement stems only from the speed performance aspectideal for ..
MC10EP445FA ,3.3V / 5VECL 8-Bit Serial/Parallel Converter
MC10EP445FAG , 3.3V/5V ECL 8−Bit Serial/Parallel Converter
MC34063ECD-TR ,DC-DC CONVERTER CONTROL CIRCUITSABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Power Supply Voltage 50 VCCVir Comparator Inpu ..
MC34063ECN ,DC-DC CONVERTER CONTROL CIRCUITSELECTRICAL CHARACTERISTICSEmitter Follower Configuration Output Saturation Output Switch ON-OFF Tim ..
MC34063ECN ,DC-DC CONVERTER CONTROL CIRCUITSELECTRICAL CHARACTERISTICSEmitter Follower Configuration Output Saturation Output Switch ON-OFF Tim ..
MC34064 ,UnderVoltage Sensing CircuitThermal CharacteristicsP Suffix, Plastic PackageP 625 mWMaximum Power Dissipation @ T = 25°C DAR 20 ..
MC34064D ,Undervoltage Sensing Circuitfeatures atrimmed–in–package bandgap reference, and a comparator with TO–226AAP SUFFIXprecise thres ..
MC34064D-005 ,UnderVoltage Sensing CircuitMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
MC100E111FN-MC100E137FN-MC100E141FN-MC100E150FNR2-MC100E151FN-MC100E167FN-MC100E175FN-MC100E431FNR2-MC100E446FN-MC100E452FNR2-MC100EL01DR2-MC100EL17-MC100EL29DW-MC100EL91DWR2-MC100ELT23DTR2-MC100ELT25D-MC100ELT28D-MC100ELT28DR2-MC100EP05D-MC100EP11-MC100EP58D-
2.5V / 3.3V / 5V ECL Dual Differential 2:1 Multiplexer
AN1504/D
Metastability and the
ECLinPS Family
Prepared by: Applications EngineeringThis application note examines the concept of
metastability and provides a theoretical discussion of how it
occurs, including examples of the metastable condition. An
equation characterizing metastability and a test circuit
derived from that equation are presented. Metastability
results are then applied to the ECLinPS family.
IntroductionMetastability is a central issue anytime a designer wishes
to synchronize two or more asynchronous signals. A popular
method for accomplishing this task is to employ a D
flip−flop as the synchronizing element (Figure 1).
As shown in Figure 1, synchronization can be
accomplished using a single D flip−flop; more typically,
several D flip−flops are cascaded to provide synchronizationwhile reducing the probability of a metastable or
“anomalous” state occurring at the input of System 2.
Unfortunately the information at the data and clock inputs of
flip−flops used as synchronizing elements is asynchronous by
nature, thus the manufacturer specifications for set−up and
hold times may not be observed. A series of timing diagrams
is shown in Figure 2 demonstrating three possible timing
relationships between the data and clock signals; to the right
of each data trace is the corresponding output waveform. In
the first case the data adheres to the specified set−up and hold
times, hence the output attains the proper state. In case 2 the
set−up time is violated such that the output of the D flip−flop
does not change state. Case 3 represents a violation of the
set−up and
metastable state. The resolving time for a flip−flop in this
metastable state is indeterminate. Further, the final settling
state of the flip−flop having been in this metastable condition
cannot be guaranteed.
Metastability TheoryA bistable device such as a flip−flop has two stable output
states: the “1” or high state and the “0” or low state. When
the manufacturers specified set−up and hold times areobserved the flip−flop will achieve the proper output state
(Figure 3). However if the
violated the device may enter a metastable state, thereby
increasing the propagation delay, as indicated by the output
response shown in Figure 4.
To better understand flip−flop metastability, the operation
of a typical ECLinPS D flip−flop is reviewed. The schematic
of a D flip−flop is shown in Figure 5.
