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MAXQ1850-DNS+
DeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
MAXQ1850
EVALUATION KIT AVAILABLE
DeepCover Secure Microcontroller with Rapid
Zeroization Technology and Cryptography
General Description
DeepCover™ embedded security solutions cloak sensitive
data under multiple layers of advanced physical security
to provide the most secure key storage possible.
The DeepCover Secure Microcontroller (MAXQ1850) is a
low-power, 32-bit RISC device designed for electronic
commerce, banking, and data security systems. It com-
bines high-performance, single-cycle processing, sophis-
ticated tamper-detection technology, and advanced
cryptographic hardware to provide industry-leading data
security and secret key protection.
Physical security mechanisms include environmental
sensors that detect out of range voltage or temperature
conditions, responding with rapid zeroization of critical
data. Four self-destruct inputs are provided for addition-
al tamper response. An internal shield over the silicon
provides protection from microprobe attacks. A high-
speed internal ring oscillator is provided to thwart
attacks that rely on controlling the clock rate of the chip.
To protect data, the MAXQ1850 integrates several high-
speed, analysis-resistant encryption engines. Algorithms
supported in hardware include AES (128-, 192-, and
256-bit), DES, triple DES (2-key and 3-key), ECDSA
(160-, 192-, and 256-bit keys), DSA, RSA (up to 2048
bits), SHA-1, SHA-224, and SHA-256. The advanced
security features of the MAXQ1850 are designed to
meet the stringent requirements of regulations such as
ITSEC E3 High, FIPS140-2 Level 3, and the Common
Criteria certifications.
The MAXQ1850includes 256KB of flash memory and
8KB of secure, battery-backed data SRAM. Several
communication protocols are supported with hardware
engines, including ISO 7816 for smart card applications,
USB (slave interface with four end-point buffers), an RS-
232 universal synchronous/asynchronous receiver-
transmitter (USART), an SPI interface (master or slave
mode support), and up to 16 general-purpose I/O pins.
Other peripherals supported on the MAXQ1850 include
a true hardware random-number generator (RNG), a
real-time clock (RTC), a programmable watchdog timer,
and flexible 16-bit timers that support capture, compare,
and pulse-width modulation (PWM) operations.
FeaturesHigh-Performance, Low-Power, 32-Bit MAXQ30
RISC CoreSingle 3.3V Supply Enables Low Power/Flexible
InterfacingDC to 16MHz Code Execution Across Entire
Operating Range65MHz Cryptography Engine Execution to Reduce
Processing TimeOn-Chip 2x/4x Clock Multiplier33 Instructions16-Bit Instruction Word, 32-Bit Internal Data Bus16 x 32-Bit AccumulatorsUp to 16 General-Purpose I/O Pins5V Tolerant I/OVirtually Unlimited Software StackOptimized for C-Compiler (High-Speed/Density Code)Memory FeaturesSecurity FeaturesAdditional PeripheralsLow-Power Consumption
Applications
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAXQ1850-BNS+ -40°C to +85°C 40 TQFN-EP*
MAXQ1850-LNS+ -40°C to +85°C 49 CSBGA
MAXQ1850-DNS+ -40°C to +85°C Bare die
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Selector Guide appears at end of data sheet.
See the Detailed Featuressection for complete list of features.
Electronic Commerce
EMV®Banking
Secure Access Control
Secure Data Storage
Pay-per-Play
Certificate Authentication
Electronic Signature
Generation
DeepCover is a trademark of Maxim Integrated Products, Inc.
EMV is a registered trademark of EMVCo LLC.
DeepCover Secure Microcontroller with Rapid
Zeroization Technology and Cryptography
MAXQ1850
ABRIDGED DATASHEET
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
CORE
OSC
ECDSARSA
16KB
ROM
8KB
NV SRAM
GPIO
MAXQ30
CORE
ISO 7816
SPI
USB
USART
DSADES
AESRNGTIMERSJTAG/
DEBUG
256KB
FLASH
CRYPTO
OSC
RTCPLL
32kHz12MHzMAXQ1850
NOTE: THE BLOCK DIAGRAM SHOWS A TYPICAL SYSTEM CLOCK USED TO SUPPORT USB OPERATION AT 12MHz. MULTIPLE EXTERNAL CRYSTAL/CLOCK OPTIONS
ARE AVAILABLE.
Block Diagram
Detailed FeaturesHigh-Performance, Low-Power, 32-Bit MAXQ30
RISC CoreSingle 3.3V Supply Enables Low Power/Flexible
InterfacingDC to 16MHz Code Execution Across Entire
Operating Range65MHz Cryptography Engine Execution to Reduce
Processing TimeOn-Chip 2x/4x Clock Multiplier33 InstructionsThree Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement16-Bit Instruction Word, 32-Bit Internal Data Bus16 x 32-Bit AccumulatorsUp to 16 General-Purpose I/O Pins5V Tolerant I/OVirtually Unlimited Software StackOptimized for C-Compiler (High-Speed/Density Code)Memory Features
256KB Flash, Composed of 2048 Byte Sectors
(1K Erase/Write Cycles per Sector)
8KB Battery-Backed Data SRAM
Dedicated Cryptographic Memory SpaceSecurity Features
Unique ID
Tamper Detection with Rapid Key/Data Destruction
Four Self-Destruct Inputs
Hardware AES and DES Engines
Public Key Cryptographic Accelerator for DSA,
ECDSA, and RSA
Supports SHA-1, SHA-224, and SHA-256
Real Hardware RNG and PRNG
Hardware CRC-32/16
Unalterable, Battery-Backed Real-Time ClockAdditional Peripherals
Power-Fail Warning
Power-On Reset/Brownout Reset
JTAG I/F for System Programming and
Accessing On-Chip Debugger
USB I/F with Four End-Point Buffers
ISO 7816 Smart Card UART with FIFO
Four 16-Bit Timer/Counters, Two with PWM
Function
SPI and USART Communication Ports
Programmable Watchdog TimerLow-Power Consumption
150nA Typical Current Draw in Battery-Backed Mode,
Preserving 8KB NV SRAM and with Security
Sensors Active (460nA with RTC Active)
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.

Partno	Mfg	Dc	Qty	Available	Descript
MAXQ1850-DNS+ \|MAXQ1850DNS	MAXIM	N/a	965	avai	DeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography