MAX9761ETI ,Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Muxfeatures include low♦ Low-Power Shutdown Mode: 10µA4mV V (minimizes DC current drain through theOS♦ ..
MAX9766ETJ+T ,750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Muxapplications that do not require♦ Headphone Sense Inputa headphone amp and includes a stereo BTL sp ..
MAX9768ETG+ ,10W Mono Class D Speaker Amplifier with Volume ControlBlock Diagram3.3V 4.5V TO 14VMAX9768 EMI WITH FERRITE BEAD FILTERS(V = 12V, 1m CABLE, 8Ω LOAD)DD40S ..
MAX9768ETG+T ,10W Mono Class D Speaker Amplifier with Volume ControlELECTRICAL CHARACTERISTICS(V = 12V, V = 3.3V, V = V = 0, V = V , V = 0; Max volume setting; speaker ..
MAX976ESA ,Single/Dual/Quad / SOT23 / Single-Supply / High-Speed / Low-Power Comparatorsfeatures a' 1nA Shutdown Supply Currentlow-power shutdown mode that places the output in ahigh-impe ..
MAX976ESA+ ,Single/Dual/Quad, SOT23, Single-Supply, High-Speed, Low-Power ComparatorsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V, V = 0V, T = -40°C to +85°C, unless otherwise noted. ..
MB89475 ,F2MC-8L/Low Power/Low Voltage Microcontrollersapplications forconsumer product.2* : F MC stands for FUJITSU Flexible Microcontroller.n
MB89535A ,F2MC-8L/Low Power/Low Voltage MicrocontrollersFEATURES• Wide range of package options• Two types of QFP packages (1 mm pitch, 0.65 mm pitch) • LQ ..
MB89535A ,F2MC-8L/Low Power/Low Voltage MicrocontrollersFUJITSU SEMICONDUCTORDS07-12547-4EDATA SHEET8-bit Original Microcontroller CMOS2F MC-8L MB89530A Se ..
MB89537A , 8-bit Original Microcontroller CMOS, F-2MC-8L MB89530A Series
MB89537A , 8-bit Original Microcontroller CMOS, F-2MC-8L MB89530A Series
MB89537AC , 8-bit Original Microcontroller CMOS, F-2MC-8L MB89530A Series
MAX9761ETI
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
General DescriptionThe MAX9760–MAX9763 family combines a stereo or
mono 3W bridge-tied load (BTL) audio power amplifier,
stereo single-ended headphone amplifier, headphone
sensing, and a 2:1 input multiplexer all in a tiny 28-pin
thin QFN package. These devices operate from a sin-
gle 4.5V to 5.5V supply and feature an industry-leading
100dB PSRR, allowing these devices to operate from
noisy supplies without the addition of a linear regulator.
An ultra-low 0.002% THD+N ensures clean, low-distor-
tion amplification of the audio signal. Click-and-pop
suppression eliminates audible transients on power and
shutdown cycles. Power-saving features include low
4mV VOS(minimizes DC current drain through the
speakers), low 13mA supply current, and a 10µA shut-
down mode. A MUTE function allows the outputs to be
quickly enabled or disabled.
A headphone sense input detects the presence of a
headphone jack and automatically configures the
amplifiers for either speaker or headphone mode. In
speaker mode, the amplifiers can deliver up to 3W of
continuous average power into a 3Ωload. In head-
phone mode, the amplifier can deliver up to 200mW of
continuous average power into a 16Ωload. The gain of
the amplifiers is externally set, allowing maximum flexi-
bility in optimizing output levels for a given load. The
amplifiers also feature a 2:1 input multiplexer, allowing
multiple audio sources to be selected. The multiplexer
can also be used to compensate for limitations in the
frequency response of the loud speakers by selecting
an external equalizer network. The various functions are
controlled by either an I2C-compatible or simple parallel
control interface.
The MAX9760–MAX9763 are available in either a ther-
mally efficient 28-pin thin QFN package (5mm ✕5mm ✕
0.8mm) or a TSSOP-EP package. All devices have ther-
mal overload protection (OVP) and are specified over
the extended -40°C to +85°C temperature range.
ApplicationsNotebooks
Portable DVD Players
Tablet PCs
PC Audio Peripherals
Camcorders
FeaturesIndustry-Leading, Ultra-High 100dB PSRRPC99/01 Compliant3W BTL Stereo Speaker Amplifier200mW Stereo Headphone AmplifierLow 0.002% THD+NClick-and-Pop SuppressionESD-Protected OutputsLow Quiescent Current: 13mALow-Power Shutdown Mode: 10µAMUTE FunctionHeadphone Sense InputStereo 2:1 Input MultiplexerOptional 2-Wire, I2C-Compatible or Parallel
InterfaceTiny 28-Pin Thin QFN (5mm ✕5mm ✕0.8mm) and
TSSOP-EP Packages
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input MuxSE/
BTL
SINGLE SUPPLY
4.5V TO 5.5V
I2C-
COMPATIBLE
MAX9760
LEFT IN1
LEFT IN2
RIGHT IN1
RIGHT IN2
CONTROL
Simplified Block Diagram
Ordering Information19-2744; Rev 0; 1/03
PARTTEMP RANGEPIN-PACKAGE
MAX9760ETI-40°C to +85°C28 Thin QFN-EP*
MAX9760EUI-40°C to +85°C28 TSSOP-EP*
Pin Configurations and Functional Diagrams appear at end
of data sheet.
Ordering Information continued at end of data sheet.*EP = Exposed paddle.
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................................+6V
SVDDto GND.........................................................................+6V
SVDDto VDD.........................................................................-0.3V
PVDDto VDD.......................................................................±0.3V
PGND to GND.....................................................................±0.3V
All Other Pins to GND.................................-0.3V to (VDD+ 0.3V)
Continuous Input Current (into any pin except power-supply
and output pins)...............................................................±20mA
Continuous Power Dissipation
28-Pin Thin QFN (derate 20.8mW/°C above +70°C)....1667mW
28-Pin TSSOP-EP (derate 23.8mW/°C above +70°C)..1905mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(VDD= PVDD= 5.0V, GND = PGND = 0V, SHDN= 5V, CBIAS= 1µF, RIN= RF= 15kΩ, RL= ∞. TA= TMINto TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply Voltage RangeVDD/PVDDInferred from PSRR test4.55.5V
MAX9760/MAX97611332BTL mode,
HPS = 0VMAX9762/MAX9763718Quiescent Supply Current
(IVDD + IPVDD)IDD
Single-ended mode, HPS = VDD718
Shutdown CurrentI SHDNSHDN = GND1050µA
Switching TimetSWGain or input switching10µs
CBIAS = 1µF300Turn-On TimetONCBIAS = 0.1µF30ms
Thermal Shutdown Threshold160oC
Thermal Shutdown Hysteresis15oC
OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND)Output Offset VoltageVOSOUT_+ - OUT_-, AV = 1V/V±4±32mV
VDD = 4.5V to 5.5V75100
f = 1kHz, VRIPPLE =
200mVP-P82Power-Supply Rejection RatioPSRR(Note 2)
f = 20kHz, VRIPPLE =
200mVP-P70
RL = 8Ω11.4
RL = 4Ω2.6Output PowerPOUT
fIN = 1kHz,
THD+N < 1%,
TA = +25°CRL = 3Ω3
POUT = 1W, RL = 8Ω0.005Total Harmonic Distortion Plus
NoiseTHD+NfIN = 1kHz, BW =
22Hz to 22kHzPOUT = 2W, RL = 4Ω0.01%
Signal-to-Noise RatioSNRRL = 8Ω, POUT = 1W, BW = 22Hz to 22kHz95dB
Slew RateSR1.6V/µs
Maximum Capacitive Load DriveCLNo sustained oscillations1nF
CrosstalkfIN = 10kHz73dB
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)(VDD= PVDD= 5.0V, GND = PGND = 0V, SHDN= 5V, CBIAS= 1µF, RIN= RF= 15kΩ, RL= ∞. TA= TMINto TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = VDD)VDD = 4.5V to 5.5V75106
f = 1kHz, VRIPPLE =
200mVP-P88Power-Supply Rejection RatioPSRR(Note 2)
f = 20kHz, VRIPPLE =
200mVP-P76
RL = 32Ω88Output PowerPOUTfIN = 1kHz, THD+N <
1%, TA = +25°CRL = 16Ω120200mW
POUT = 60mW,
RL = 32Ω0.002
Total Harmonic Distortion Plus
NoiseTHD+NfIN = 1kHz, BW =
22Hz to 22kHzPOUT = 125mW,
RL = 16Ω0.002
Signal-to-Noise RatioSNRRL = 32Ω, BW = 22Hz to 22kHz,
VOUT = 1VRMS92dB
Slew RateSR1.8V/µs
Maximum Capacitive Load DriveCLNo sustained oscillations2nF
CrosstalkfIN = 10kHz78dB
STANDBY SUPPLY (SVDD) (Note 3)VBIAS = 1.25V, VDD = 0V425750SVDD CurrentISVDDVBIAS = 2.5V, VDD = 5V15µA
BIAS VOLTAGE (BIAS)BIAS VoltageVBIAS2.352.52.65V
Output ResistanceRBIAS50kΩ
DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN1111/2)
Input Voltage HighVIH2V
Input Voltage LowVIL0.8V
Input Leakage CurrentIIN±1µA
HEADPHONE SENSE INPUT (HPS)Input Voltage HighVIH0.9 x
VDDV
Input Voltage LowVIL0.7 x
VDDV
Input Leakage CurrentIIN±1µA
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)(VDD= PVDD= 5.0V, GND = PGND = 0V, SHDN= 5V, CBIAS= 1µF, RIN= RF= 15kΩ, RL= ∞. TA= TMINto TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9760/MAX9762)Input Voltage HighVIH2.6V
Input Voltage LowVIL0.8V
Input Hysteresis0.2V
Input High Leakage CurrentIIHVIN = 5V±1µA
Input Low Leakage CurrentIILVIN = 0V±1µA
Input CapacitanceCIN10pF
Output Voltage LowVOLIOL = 3mA0.4V
Output Current HighIOHVOH = 5V1µA
TIMING CHARACTERISTICS (MAX9760/MAX9762)Serial Clock FrequencyfSCL400kHz
Bus Free Time Between STOP
and START ConditionstBUF1.3µs
START Condition Hold TimetHD:STA0.6µs
START Condition Setup TimetSU:STA0.6µs
Clock Period LowtLOW1.3µs
Clock Period HightHIGH0.6µs
Data Setup TimetSU:DAT100ns
Data Hold TimetHD:DAT(Note 4)00.9µs
Receive SCL/SDA Rise Timetr(Note 5)20 +
0.1CB300ns
Receive SCL/SDA Fall Timetf(Note 5)20 +
0.1CB300ns
Transmit SDA Fall Timetf(Note 5)20 +
0.1CB250ns
Pulse Width of Suppressed
SpiketSP(Note 6)50ns
Note 1:All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
Note 2:PSRR is specified with the amplifier inputs connected to GND through RINand CIN.
Note 3:Refer to the SVDDsection.
Note 4:A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 5:CB= total capacitance of one of the bus lines in picofarads. Device tested with CB= 400pF. 1kΩpullup resistors connected
from SDA/SCL to VDD.
Note 6:Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc01
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001100k
RL = 3Ω
AV = 2V/V
POUT = 2.5WPOUT = 2W
POUT = 500mWPOUT = 1W
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc02
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001100k
RL = 3Ω
AV = 4V/V
POUT = 2.5WPOUT = 2W
POUT = 500mWPOUT = 1W
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc03
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001100k
RL = 4Ω
AV = 2V/V
POUT = 2WPOUT = 1W
POUT = 500mWPOUT = 250mW
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc04
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001100k
RL = 4Ω
AV = 4V/V
POUT = 250mW
POUT = 2WPOUT = 1W
POUT = 500mW
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc05
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001100k
RL = 8Ω
AV = 2V/V
POUT = 250mW
POUT = 1.2WPOUT = 1W
POUT = 500mW
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc06
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001100k
POUT = 250mW
POUT = 1.2WPOUT = 1W
POUT = 500mW
RL = 8Ω
AV = 4V/V
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)MAX9760 toc07
OUTPUT POWER (W)
THD+N (%)21
AV = 2V/V
RL = 3Ω
f = 1kHz
f = 20Hz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)MAX9760 toc08
OUTPUT POWER (W)
THD+N (%)21
AV = 4V/V
RL = 3Ω
f = 20Hz
f = 1kHz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)MAX9760 toc09
OUTPUT POWER (W)
THD+N (%)
AV = 2V/V
RL = 4Ω
f = 20Hz
f = 1kHzf = 10kHz
Typical Operating Characteristics(VDD= PVDD= 5V, TA = +25°C, unless otherwise noted.)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)MAX9760 toc10
OUTPUT POWER (W)
THD+N (%)
AV = 4V/V
RL = 4Ω
f = 20Hz
f = 1kHz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)MAX9760 toc11
OUTPUT POWER (W)
THD+N (%)
AV = 2V/V
RL = 8Ω
f = 20Hz
f = 1kHz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)MAX9760 toc12
OUTPUT POWER (W)
THD+N (%)
AV = 4V/V
RL = 8Ω
f = 20Hz
f = 1kHz
f = 10kHz
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)MAX9760 toc13
TEMPERATURE (°C)
OUTPUT POWER (W)3510-15
THD+N = 10%
THD+N = 1%
f = 1kHz
RL = 3Ω
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)MAX9760 toc14
TEMPERATURE (°C)
OUTPUT POWER (W)3510-15
THD+N = 10%
THD+N = 1%
f = 1kHz
RL = 4Ω
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)MAX9760 toc15
TEMPERATURE (°C)
OUTPUT POWER (W)3510-15
THD+N = 10%
THD+N = 1%
f = 1kHz
RL = 8Ω
OUTPUT POWER vs. LOAD RESISTANCE
(SPEAKER MODE)MAX9760 toc16
LOAD RESISTANCE (Ω)
OUTPUT POWER (W)
10k1k10010100k
f = 1kHz
THD+N = 10%
THD+N = 1%
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)MAX9760 toc17
OUTPUT POWER (W)
POWER DISSIPATION (W)
RL = 4Ω
f = 1kHz
ypical Operating Characteristics (continued)(VDD= PVDD= 5V, TA = +25°C, unless otherwise noted.)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
CROSSTALK vs. FREQUENCY
(SPEAKER MODE)MAX9760 toc19
FREQUENCY (Hz)
CROSSTALK (dB)
10k1k100
-120100k
VIN = 200mVP-P
RL = 8Ω
RIGHT TO LEFT
LEFT TO RIGHT
ENTERING SHUTDOWN (SPEAKER MODE)MAX9760 toc20
100ms/div
OUT_+
AND OUT_-
2V/div
1V/div
200mV/divOUT_+
- OUT_-
SHDN
RL = 8Ω
INPUT AC-COUPLED TO GND
EXITING SHUTDOWN (SPEAKER MODE)MAX9760 toc21
100ms/div
OUT_+
AND OUT_-
2V/div
1V/div
200mV/divOUT_+
- OUT_-
SHDN
RL = 8Ω
INPUT AC-COUPLED TO GND
ENTERING POWER-DOWN
(SPEAKER MODE)MAX9760 toc22
100ms/div
OUT_+
AND OUT_-
2V/div
1V/div
200mV/divOUT_+
- OUT_-
VDD
RL = 8Ω
INPUT AC-COUPLED TO GND
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)MAX9760 toc23
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.0001100k
RL = 16Ω
AV = 1V/V
POUT = 50mWPOUT = 25mW
POUT = 100mWPOUT = 150mW
ypical Operating Characteristics (continued)(VDD= PVDD= 5V, TA = +25°C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPEAKER MODE)MAX9760 toc18
FREQUENCY (Hz)
PSRR (dB)
10k1k100
100100k
VRIPPLE = 200mVP-P
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)MAX9760 toc28
OUTPUT POWER (mW)
THD+N (%)
AV = 2V/V
RL = 16Ω
f = 20Hz
f = 1kHz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)MAX9760 toc29
OUTPUT POWER (mW)
THD+N (%)
AV = 1V/V
RL = 32Ω
f = 20Hz
f = 1kHz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)MAX9760 toc30
OUTPUT POWER (mW)
THD+N (%)
AV = 2V/V
RL = 32Ω
f = 20Hz
f = 1kHz
f = 10kHz
OUTPUT POWER vs. TEMPERATURE
(HEADPHONE MODE)MAX9760 toc31
TEMPERATURE (°C)
OUTPUT POWER (mW)3510-15
THD+N = 10%
THD+N = 1%
f = 1kHz
RL = 16Ω
OUTPUT POWER vs. TEMPERATURE
(HEADPHONE MODE)MAX9760 toc332
TEMPERATURE (°C)
OUTPUT POWER (mW)3510-15
THD+N = 10%
THD+N = 1%
f = 1kHz
RL = 32Ω
Typical Operating Characteristics (continued)(VDD= PVDD= 5V, TA = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)MAX9760 toc25
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.0001100k
RL = 32Ω
AV = 1V/V
POUT = 50mWPOUT = 25mW
POUT = 100mWPOUT = 150mW
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)MAX9760 toc26
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.0001100k
RL = 32Ω
AV = 2V/V
POUT = 50mWPOUT = 25mW
POUT = 100mWPOUT = 150mW
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)MAX9760 toc27
OUTPUT POWER (mW)
THD+N (%)
AV = 1V/V
RL = 16Ω
f = 20Hz
f = 1kHz
f = 10kHz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)MAX9760 toc24
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.0001100k
RL = 16Ω
AV = 2V/V
POUT = 50mWPOUT = 25mW
POUT = 100mWPOUT = 150mW
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
CROSSTALK vs. FREQUENCY
(HEADPHONE MODE)MAX9760 toc37
FREQUENCY (Hz)
CROSSTALK (dB)
10k1k100
-120100k
VIN = 200mVP-P
RL = 16Ω
RIGHT TO LEFT
LEFT TO RIGHT
EXITING SHUTDOWN (HEADPHONE MODE)MAX9760 toc38
100ms/div
OUT_+
2V/div
1V/div
200mV/divHP JACK
SHDN
RL = 16Ω
INPUT AC-COUPLED TO GND
ENTERING SHUTDOWN (HEADPHONE MODE)MAX9760 toc39
100ms/div
OUT_+
2V/div
1V/div
200mV/divHP JACK
SHDN
RL = 16Ω
INPUT AC-COUPLED TO GND
EXITING POWER-DOWN
(HEADPHONE MODE)MAX9760 toc40
100ms/div
OUT_+
2V/div
1V/div
200mV/divHP JACK
VDD
RL = 16Ω
INPUT AC-COUPLED TO GND
Typical Operating Characteristics (continued)(VDD= PVDD= 5V, TA = +25°C, unless otherwise noted.)
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)MAX9760 toc35
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
RL = 32Ω
f = 1kHz
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)MAX9760 toc36
FREQUENCY (Hz)
PSRR (dB)
10k1k100
100100k
VRIPPLE = 200mVP-P
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)MAX9760 toc33
LOAD RESISTANCE (Ω)
OUTPUT POWER (mW)10010
60010k
f = 1kHz
THD+N = 10%
THD+N = 1%
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)MAX9760 toc34
OUTPUT POWER (mW)
POWER DISSIPATION (mW)100150200
RL = 16Ω
f = 1kHz
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
EXITING POWER-DOWN
(SPEAKER MODE)MAX9760 toc46
100ms/div
OUT_+
AND OUT_-
2V/div
1V/div
200mV/divOUT_+
- OUT_-
VDD
RL = 8Ω
INPUT AC-COUPLED TO GND
Typical Operating Characteristics (continued)(VDD= PVDD= 5V, TA = +25°C, unless otherwise noted.)
ENTERING POWER-DOWN
(HEADPHONE MODE)MAX9760 toc41
100ms/div
OUT_+
2V/div
1V/div
200mV/divHP JACK
VDD
RL = 16Ω
INPUT AC-COUPLED TO GND
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SPEAKER MODE)MAX9760 toc42
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TA = +85°C
TA = +25°C
TA = -40°C
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)MAX9760 toc43
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TA = +85°C
TA = +25°C
TA = -40°C
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX97960 toc44
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
TA = +85°C
TA = +25°C
TA = -40°C
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)MAX9760 toc45
OUTPUT POWER (W)
POWER DISSIPATION (W)
RL = 8Ω
f = 1kHz
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Pin Description
PIN
MAX9760MAX9761MAX9762MAX9763
QFNTSSOPQFNTSSOPQFNTSSOPQFNTSSOP
NAMEFUNCTION126——126——SDABidirectional Serial Data I/O
227——227——INTµC Interrupt Output28328328328VDDPower Supply414141SVDD
Standby Power Supply. Connect
to a standby power supply that is
always on, or connect to VDD
through a Schottky diode and
bypass with 220µF capacitor to
GND. Short to VDD if clickless
operation is not essential.2525252INL1Left-Channel Input 13636363INL2Left-Channel Input 24747474GAINLALeft-Channel Gain Set A5858585GAINLBLeft-Channel Gain Set B
9, 13,
23, 27
6, 10,
20, 24
9, 13,
23, 27
6, 10, 20,
9, 23,6, 20, 249, 23, 276, 20, 24PGNDPower Ground7107107107OUTL+
Left-Channel Bridged Amplifier
Positive Output. OUTL+ also
serves as the left-channel
headphone amplifier output.
11, 258, 2211, 258, 2211, 258, 2211, 258, 22PVDDOutput Amplifier Power Supply9129————OUTL-Left-Channel Bridged Amplifier
Negative Output11141114111411SHDNActive-Low Shutdown. Connect
SHDN to VDD for normal operation.12——1512——ADD
Address Select. A logic high sets
the address LSB to 1, a logic low
sets the address LSB to zero.13161316131613HPS
Headphone Sense Input. A logic
high configures the device as a
single-ended headphone amp. A
logic low configures the device as
a BTL speaker amp.14171417141714BIAS
DC Bias Bypass. See BIAS
Capacitor Selection section for
capacitor selection. Connect
CBIAS from BIAS to GND.15181513101310GNDGround
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Detailed DescriptionThe MAX9760–MAX9763 feature 3W BTL speaker
amplifiers, 200mW headphone amplifiers, input multi-
plexers, headphone sensing, and comprehensive click-
and-pop suppression. The MAX9760/ MAX9761 are
stereo BTL/headphone amplifiers. The MAX9762/
MAX9763 are mono BTL/stereo headphone amplifiers.
The MAX9760/MAX9762 are controlled through an I2C-
compatible, 2-wire serial interface. The MAX9761/
MAX9763 are controlled through five logic inputs:
MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2 (see
Selector Guide). The MAX9760–MAX9763 feature
exceptional PSRR (100dB at 1kHz), allowing these
devices to operate from noisy digital supplies without
the need for a linear regulator.
The speaker amplifiers use a BTL configuration. The
signal path is composed of an input amplifier and an
output amplifier. Resistor RINsets the input amplifier’s
gain, and resistor RFsets the output amplifier’s gain.
The output of these two amplifiers serves as the input to
a slave amplifier configured as an inverting unity-gain
follower. This results in two outputs, identical in magni-
tude, but 180°out of phase. The overall gain of the
speaker amplifiers is twice the product of the two
amplifier gains (see Gain-Setting Resistor section). A
feature of this architecture is that there is no phase
inversion from input to output.
Pin Description (continued)
PIN
MAX9760MAX9761MAX9762MAX9763
QFNTSSOPQFNTSSOPQFNTSSOPQFNTSSOP
NAMEFUNCTION16191619161916INR1Right-Channel Input 117201720172017INR2Right-Channel Input 218211821182118GAINRARight-Channel Gain Set A19221922192219GAINRBRight-Channel Gain Set B21242124212421OUTR+
Right-Channel Bridged Amplifier
Positive Output. OUTR+ also
serves as the right-channel
headphone amplifier output.23262326232623OUTR-Right-Channel Bridged Amplifier
Negative Output25——2825——SCLSerial Clock Line——129129N.C.No Connection. Not internally
connected.——18151815GAINMMono Gain Set126——126MUTEActive-High Mute Input227——227HPS_EN
Headphone Enable. A logic high
enables HPS. A logic low disables
HPS and the device is always
configured as a BTL speaker amp.1512——1512GAINA/B
Gain Select. A logic low selects
the gain set by GAIN_A. A logic
high selects the gain set by
GAIN_B.2825——2825IN1/2
Input Select. A logic low selects
amplifier input 1. A logic high
selects amplifier input 2.
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input MuxWhen configured as a headphone (single-ended) ampli-
fier, the slave amplifier is disabled, muting the speaker
and the main amplifier drives the headphone. The
MAX9760–MAX9763 can deliver 3W of continuous aver-
age power into a 3Ωload with less than 1% THD+N in
speaker mode, and 200mW of continuous average
power into a 16Ωload with less than 1% THD+N in
headphone mode. These devices also feature thermal
overload protection.
Mono ModeThe MAX9762/MAX9763 are 3W mono speaker ampli-
fiers, 200mW stereo headphone amplifiers, and a
mixer/attenuator (see the MAX9762/MAX9763 Functional
Diagram). In speaker (mono) mode, the mixer/attenuator
combines the two stereo inputs (INL_ and INR_) and
attenuates the resultant signal by a factor of 2. This
allows for full reproduction of a stereo signal through a
single speaker, while maintaining optimum headroom.
The resistor connected between GAINM and OUTR+,
sets the gain of the devices in speaker mode (see the
MAX9762 Functional Diagram). This allows the speaker
amplifier to have a different gain and feedback network
from the headphone amplifier.
BIASThese devices operate from a single 5V supply, and
feature an internally generated, power-supply indepen-
dent, common-mode bias voltage of 2.5V referenced to
GND. BIAS provides both click-and-pop suppression
and sets the DC bias level for the audio outputs. BIAS
is internally connected to the noninverting input of each
speaker amplifier (see Typical Application Circuit/
Functional Diagram). Choose the value of the bypass
capacitor as described in the BIAS Capacitorsection.
No external load should be applied to BIAS. Any load
lowers the BIAS voltage, affecting the overall perfor-
mance of the device.
Input MultiplexerEach amplifier features a 2:1 input multiplexer, allowing
input selection between two stereo sources. Both multi-
plexers are controlled by bit 1 in the control register
(MAX9760/MAX9762) or by the IN1/2 pin (MAX9761/
MAX9763). A logic low selects input IN_1 and a logic
high selects input IN_2.
The input multiplexer can also be used to further
expand the number of gain options available from the
MAX9760–MAX9763 family. Connecting the audio
source to the device through two different input resis-
tors (Figure 1) increases the number of gain options
from two to four (MAX9760/MAX9761) and from three to
six (MAX9762/MAX9763). Additionally, the input multi-
plexer allows a speaker equalization network to be
switched into the speaker signal path. This is typically
useful in optimizing acoustic response from speakers
with small physical dimensions.
Headphone Sense Enable The HPS pin is enabled by HPS_EN (MAX9762/
MAX9763) or the HPSD bit (MAX9760/MAX9761).
HPSD or HPS_EN determines whether the device is in
automatic detection mode or fixed mode operation (see
Tables 1a and 1b).
Headphone Sense Input (HPS)A voltage on HPS less than 0.7 ✕VDDsets the device
to speaker mode. A voltage greater than 0.9 ✕VDDdis-
ables the inverting bridge amplifier (OUT_-), which
mutes the speaker amplifier and sets the device into
headphone mode.
For automatic headphone detection, connect HPS to the
control pin of a 3-wire headphone jack as shown in
Figure 2. With no headphone present, the resistive volt-
age-divider created by R1 and R2 sets the voltage on
HPS to be less than 0.7 ✕VDD, setting the device to
speaker mode and the gain setting defaults to GAINA
(MAX9760/MAX9762). When a headphone plug is insert-
ed into the jack, the control pin is disconnected from the
tip contact, and HPS is pulled to VDDthrough R1, setting
the device into headphone mode and the gain-setting
defaults to GAINB (MAX9760/MAX9762) (see Gain
Select section). Place a resistor in series with the control
pin and HPS (R3) to prevent any audio signal from cou-
pling into HPS when the device is in speaker mode.
ShutdownThe MAX9760–MAX9763 feature a 10µA, low-power
shutdown mode that reduces quiescent current con-
sumption and extends battery life. The drive amplifiers
and bias circuitry are disabled, the amplifier outputs
(OUT_) go high impedance, and BIAS is driven to
MAX9760
AUDIO
INPUT
15kΩ
30kΩ
IN_1
IN_2
Figure 1. Using the Input Multiplexer for Gain Setting
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input MuxGND. Driving SHDNlow places the devices into shut-
down mode, disables the interface, and resets the I2C
registers to a default state. A logic high on SHDN
enables the devices.
MAX9760/MAX9762 Software ShutdownA logic high on bit 0 of the SHDN register places the
MAX9760/MAX9762 in shutdown mode. A logic low
enables the device. The digital section of the
MAX9760/MAX9762 remains active when the device is
shut down through the interface. All devices feature a
logic low on the SHDNinput.
MUTEAll devices feature a mute mode. When the device is
muted, the input is disconnected from the amplifiers.
MUTE does not shut down the device.
MAX9760/MAX9762 MUTEThe MAX9760/MAX9762 MUTE mode is selected by
writing to the MUTE register (see the Command Byte
Definitions section). The left and right channels can be
independently muted.
MAX9761/MAX9763 MUTEThe MAX9761/MAX9763 feature an active-high MUTE
input that mutes both channels.
Click-and-Pop SuppressionThe MAX9760–MAX9763 feature Maxim’s comprehen-
sive click-and-pop suppression. During startup and
shutdown, the common-mode bias voltage of the ampli-
fiers is slowly ramped to and from the DC bias point
using an S-shaped waveform. In headphone mode, this
waveform shapes the frequency spectrum, minimizing
the amount of audible components present at the head-
phone. In speaker mode, the BTL amplifiers start up in
the same fashion as in headphone mode. When enter-
ing shutdown, both amplifier outputs ramp to GND
quickly and simultaneously. The MAX9760–
MAX9763 can also be connected to a standby power
source that ensures that the device undergoes its full
shutdown cycle even after power has been removed.
Standby Power Supply (SVDD)The MAX9760–MAX9763 feature a system that provides
clickless power-down when power is inadvertently
removed from the device. SVDDis an optionalsec-
ondary supply that powers the device through its shut-
down cycle when VDDis removed. During this cycle,
the amplifier output DC level slowly ramps to GND,
ensuring clickless power-down. If clickless power-down
is required, connect SVDDto either a secondary power
supply that is always on, or connect a reservoir capaci-
tor from SVDDto GND. SVDDdoes not need to be con-
nected to either a secondary power supply or reservoir
capacitor for normal device operation. If click-and-pop
suppression during power-down is not required, con-
nect SVDDto VDDdirectly.
MAX9760–
MAX9763
47kΩ
680kΩ
10kΩ
HPS
VDD
OUTL+
OUTR+
Figure 2. HPS Configuration Circuit
INPUTS
HPSDHPSSPKR/HPMODE
MAX9760
GAIN
PATH*
MAX9762
GAIN
PATH*0XBTLAMXSEBBX0BTLA or BMX1SEA or BA or B
Table 1a. HPS Setting (MAX9760/MAX9761)
INPUTS
HPSENHPS
MODEMAX9761
GAIN PATH*
MAX9763
GAIN PATH*XBTLA or BM0BTLA or BM1SEA or BA or B
Table 1b. HPS Setting (MAX9762/MAX9763)
*Note:A – GAINA path selected
B – GAINB path selected
M – GAINM path selected
A or B – Gain path selected by GAINAB control bit in register
02h
*Note:A or B – Gain path selected by external GAINAB
M – GAINM path selected
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input MuxThe clickless power-down cycle only occurs when the
device is in headphone mode. The speaker mode is
inherently clickless, the differential architecture cancels
the DC shift across the speaker. The MAX9760–
MAX9763 BTL outputs are pulled to GND quickly and
simultaneously, resulting in no audible components. If
the MAX9760–MAX9763 are only used as speaker
amplifiers, then reservoir capacitors or secondary sup-
plies are not necessary.
When using a reservoir capacitor, a 220µF capacitor
provides optimum charge storage for the shutdown
cycle for all conditions. If a smaller reservoir capacitor
is desired, decrease the size of CBIAS. A smaller CBIAS
causes the output DC level to decay at a faster rate,
increasing the audible content at the speaker, but
reducing the duration of the shutdown cycle.
Digital InterfaceThe MAX9760/MAX9762 feature an I2C/SMBus-compat-
ible 2-wire serial interface consisting of a serial data
line (SDA) and a serial clock line (SCL). SDA and SCL
facilitate bidirectional communication between the
MAX9760/MAX9762 and the master at clock rates up to
400kHz. Figure 3 shows the 2-wire interface timing dia-
gram. The MAX9760/MAX9762 are transmit/receive
slave-only devices, relying upon a master to generate a
clock signal. The master (typically a microcontroller) ini-
tiates data transfer on the bus and generates SCL to
permit that transfer.
A master device communicates to the MAX9760/
MAX9762 by transmitting the proper address followed
by a command and/or data words. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.
The MAX9760/MAX9762 SDA and SCL amplifiers are
open-drain outputs requiring a pullup resistor (500Ωor
greater) to generate a logic high voltage. Series resis-
tors in line with SDA and SCL are optional. These series
resistors protect the input stages of the devices from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
Bit TransferOne data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions section). SDA and SCL idle high
when the I2C bus is not busy.
START and STOP ConditionsWhen the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition from the master signals
the beginning of a transmission to the MAX9760/
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tHD, STAtHD, STAtSP
tBUF
tSU, STOtLOW
tSU, DAT
tHD, DAT
tHIGHtF
Figure 3. 2-Wire Serial Interface Timing Diagram
SCL
SDA
SSrP
Figure 4. START/STOP Conditions
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input MuxMAX9762. The master terminates transmission by issu-
ing the STOP condition, this frees the bus. If a REPEAT-
ED START condition is generated instead of a STOP
condition, the bus remains active.
Early STOP ConditionsThe MAX9760/MAX9762 recognize a STOP condition at
any point during the transmission except if a STOP con-
dition occurs in the same high pulse as a START condi-
tion (Figure 5). This condition is not a legal I2C format,
at least one clock pulse must separate any START and
STOP conditions.
REPEATED START ConditionsA REPEATED START (Sr) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Srmay also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX9760/
MAX9762 serial interface supports continuous write
operations with or without an Srcondition separating
them. Continuous read operations require Srconditions
because of the change in direction of data flow.
Acknowledge Bit (ACK)The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9760/MAX9762 generate an ACK
when receiving an address or data by pulling SDA low
during the night clock period. When transmitting data,
the MAX9760/MAX9762 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
Slave AddressThe bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9760/
MAX9762 wait for a START condition followed by its
slave address. The LSB of the address word is the
Read/Write(R/W) bit. R/Windicates whether the master
is writing to or reading from the MAX9760/MAX9762
(R/W= 0 selects the write condition, R/W= 1 selects
the read condition). After receiving the proper address,
the MAX9760/MAX9762 issue an ACK by pulling SDA
low for one clock cycle.
The MAX9760/MAX9762 have a factory-/user-pro-
grammed address. Address bits A6–A2 are preset,
while A0 and A1 is set by ADD. Connect ADD to either
VDD, GND, SCL, or SDA to change the last 2 bits of the
slave address (Table2).
Write Data FormatThere are three registers that configure the
MAX9760/MAX9762: the MUTE register, SHDN register,
and control register. In write data mode (R/W= 0), the
register address and data byte follow the device
address (Figure 7).
MUTE RegisterThe MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel, bit 4
(MUTER) controls the right channel. A logic high mutes
the respective channel, a logic low brings the channel
out of mute.
SHDN RegisterThe SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic high
in bit 0 of the SHDN register shuts down the device; a
logic low turns on the device. A logic high is required in
bits 2 to 7 to reset all registers to their default settings.
SCL
SDA
STOPSTART
SCL
SDA
ILLEGAL
STOP
START
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP ConditionA6A5A4A3A2A1A0R/W
Figure 6. Slave Address Byte Definition
