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MAX9691ESA+
Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable
General DescriptionThe MAX9691/MAX9692/MAX9693 are ultra-fast ECL
comparators capable of very short propagation delays.
Their design maintains the excellent DC matching char-
acteristics normally found only in slower comparators.
The MAX9691/MAX9692/MAX9693 have differential
inputs and complementary outputs that are fully com-
patible with ECL-logic levels. Output current levels are
capable of driving 50Ωterminated transmission lines.
The ultra-fast operation makes signal processing possi-
ble at frequencies in excess of 600MHz.
The MAX9692/MAX9693 feature a latch-enable (LE)
function that allows the comparator to be used in a
sample-hold mode. When LE is ECL high, the compara-
tor functions normally. When LE is driven ECL low, the
outputs are forced to an unambiguous ECL-logic state,
dependent on the input conditions at the time of the
latch input transition. If the latch-enable function is not
used on either of the two comparators, the appropriate
LE input must be connected to ground; the companioninput must be connected to a high ECL logic level.
These devices are available in SO, QSOP, and tiny
µMAX packages for added space savings.
________________________ApplicationsHigh-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
Features1.2ns Propagation Delay100ps Propagation Delay Skew 150ps Dispersion 0.5ns Latch Setup Time0.5ns Latch-Enable Pulse WidthAvailable in µMAX and QSOP Packages+5V, -5.2V Power Supplies
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable_________________________________________________________Functional Diagrams
19-1789; Rev 1; 10/02
Ordering Information
Ordering Information continued at the end of data sheet.
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage (VCC)...............................................-0.3V to +6V
Supply Voltage (VEE)................................................-6V to +0.3V
Input Voltage....................................(VCC+ 0.3V) to (VEE- 0.3V)
Output Short-Circuit Duration ....................................Continuous
Differential Input Voltage ......................................................±5V
Latch Enable...............................................(VEE- 0.3V) to +0.3V
Output Current....................................................................50mA
Input Current ....................................................................±25mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.1mW/°C above 70°C)...............330mW
8-Pin SO (derate 5.88mW/°C above +70°C)...............471mW
8-Pin PDIP (derate 10.53mW/°C above +70°C)...........842mW
10-Pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)..........667mW
16-Pin SO (derate 8.7mW/°C above +70°C)...............696mW
16-Pin PDIP (derate 9.09mW/°C above +70°C)..........727mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
ELECTRICAL CHARACTERISTICS (continued)
Note 2:VIN= 100mV, VOD= 10mV.
ELECTRICAL CHARACTERISTICS
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
WORST-CASE PROPAGATION DELAY
vs. INPUT OVERDRIVEMAX9691/3-01
INPUT OVERDRIVE (mV)
PROPAGATION DELAY (ps)
WORST-CASE PROPAGATION DELAY
vs. SOURCE IMPEDANCE
MAX9691/3-02
SOURCE IMPEDANCE (Ω)
PROPAGATION DELAY (ps)
WORST-CASE PROPAGATION DELAY
vs. CLOAD
MAX9691/3-03
CLOAD (pF)
PROPAGATION DELAY (ps)
WORST-CASE PROPAGATION DELAY
vs. TEMPERATURE
MAX9691/3-04
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
MAX9691/3-05
TEMPERATURE (°C)
(V)
OUTPUT LOW VOLTAGE
vs. TEMPERATURE
MAX9691/3-06
TEMPERATURE (°C)
(V)
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
MAX9691/3-08
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
INPUT BIAS CURRENT
vs. TEMPERATURE
MAX9691/3-09
TEMPERATURE (°C)
INPUT BIAS CURRENT (
Typical Operating Characteristics(VCC= +5V, VEE= -5.2V, RL= 50Ωto VT, VT= -2V, VOD = 10mV, TA= +25°C, unless otherwise noted.)
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Typical Operating Characteristics (continued)(VCC= +5V, VEE= -5.2V, RL= 50Ωto VT, VT= -2V, VOD = 10mV, TA= +25°C, unless otherwise noted.)
__________ Applications Information
LayoutBecause of the MAX9691/MAX9692/MAX9693s’ large
gain-bandwidth characteristic, special precautions
must be taken to use them. A PC board with a ground
plane is mandatory. Mount 0.01µF ceramic decoupling
capacitors as close to the power-supply pins as possi-
ble, and process the ECL outputs in microstrip fashion,
consistent with the load termination of 50Ωto 200Ω(for
VT = -2V). For low-impedance applications, microstrip
layout and terminations at the input may also be help-
ful. Pay close attention to the bandwidth of the decou-
pling and terminating components. Chip components
can be used to minimize lead inductance. Connect
GND1 and GND2 together to a solid copper ground
plane for the MAX9691/MAX9692. GND1 biases the
input gain stages, while GND2 biases the ECL output
stage. If the LE function is not used, connect the LE pin
to GND (MAX9692/MAX9693) and the complementaryto ECL logic high level (MAX9693 only). Do not
leave the inputs of an unused comparator floating for
the MAX9693.
Input Slew-Rate RequirementsAs with all high-speed comparators, the high gain-
bandwidth product of these devices creates oscillation
problems when the input goes through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Poor layout and
larger source impedance will increase the minimum
slew-rate requirement.
Figure 1 shows a high-speed receiver application with
50Ωinput and output termination. With this configura-
tion, in which a ground plane and microstrip PC board
are used, the minimum slew rate for clean output
switching is 1V/µs.
In many applications, adding regenerative feedback
will assist the input signal through the linear region,
which will lower the minimum slew-rate requirement
considerably. For example, with the addition of positive
feedback components, Rf = 1kΩand Cf = 10pF, the
minimum slew-rate requirement can be reduced by a
factor of four.
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch EnableAs high-speed receivers, the MAX9691/MAX9692/
MAX9693 are capable of processing signals in excess
of 600MHz. Figure 2 is a 100MHz example with an
input signal level of 14mVRMS.
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval tpd. Output Q and Qtran-
sistors are similar in timing. The input signal must occur
at time tsbefore the latch falling edge, and must be
maintained for time thafter the edge to be acquired.
After th, the output is no longer affected by the input sta-
tus until the latch is again strobed. A minimum latch
pulse width of tpw(LE)is needed for the strobe opera-
tion, and the output transitions occur after a time tLE(±).
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
