MAX9686BCSA-MAX9698BCSE Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX9686BCSA-MAX9698BCSE
Single/Dual, Very Fast TTL Latched Output Comparators
Not Recommended for New Designs
This product was manufactured for Maxim by an outside wafer foundry
using a process that is no longer available. It is not recommended for
new designs. The data sheet remains available for existing users.
A Maxim replacement or an industry second-source may be available.
Please see the QuickView data sheet for this part or contact technical
support for assistance.
For further information, contact Maxim’s Applications Tech Support.
MAX9686/MAX9698
Single/Dual, Very Fast TTL Output Comparators
19-2399; Rev 2; 6/90
Pin Configurations
General Description
The MAX9686 (single)/MAX9698 (dual) are very fast
TTL comparators manufactured with a high-frequency
bipolar process (fT= 6GHz) that are capable of very
short propagation delays, yet maintain the excellent DC
matching characteristics that are normally found only in
slower comparators. The MAX9698 is a dual version of
the MAX9686.
The MAX9686/MAX9698 have differential inputs and
complementary outputs that are fully compatible with
TTL logic levels. The extremely short propagation
delays allow signal processing at frequencies in excess
of 200MHz.
When the latch enable input goes high, the outputs go
to the states defined by the input condition at the time
of the latch transition. The outputs remain latched as
long as the LE pin remains high. If the latch enable
function is not used, the LE pin must be tied to ground.
Applications
High-Speed Analog-to-Digital Converters
High-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
Features6ns Propagation Delay2ns Latch Setup Time+5V, -5.2V Power SuppliesPin Compatible to LT1016, Am686Available in Commercial and Military VersionsAvailable in SO
Ordering Information
PARTTEMP RANGEPIN-PACKAGE*
MAX9686CPA0°C to +70°C8 Plastic Dip
MAX9686CJA0°C to +70°C8 CERDIP
MAX9686CSA0°C to +70°C8 SO
MAX9686C/D0°C to +70°CDice
MAX9686CTV0°C to +70°C8 TO-99 Metal Can
MAX9686MJA-55°C to +125°C8 CERDIP
MAX9686MTV-55°C to +125°C8 TO-99 Metal Can
MAX9698CPE0°C to +70°C16 Plastic Dip
MAX9698CJE0°C to +70°C16 CERDIP
MAX9698CSE0°C to +70°C16 SO
MAX9698C/D0°C to +70°CDice
MAX9698MJE-55°C to +125°C16 CERDIP
*Contact factory for availability of 20-lead LCC.
GND
LE2LE1Q1
GND
PLASTIC DIP, CERDIP,
TO-99 METAL CAN
PLASTIC DIP, CERDIP,
-IN2
+IN2+IN1
N.C.+V-
-IN1
N.C.
GNDV-
OUT
OUT+IN
-IN+
GND+IN
OUT
-IN+
OUT-27MAX9686
MAX9686
MAX9698
TOP VIEW
MAX9686/MAX9698
Single/Dual, Very Fast TTL Output Comparators
Supply Voltages.....................................................................±6V
Power Dissipation (Notes 1, 2).........................................336mW
Input Voltages........................................................................±5V
Differential Input Voltages........................................................5V
Output Current....................................................................20mA
Operating Temperature Ranges:
Commercial (MAX9686C/MAX9698M)................0°C to +70°C
Military (MAX9686M/MAX9698M)...................-55°C to +125°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s)....................................300°C
Note 1:Power derating above TA= +70°C is based on a maxi-
mum junction temperature of +150°C and the follow-
ing thermal resistance factors.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VS= ±5V, TA= +25°C, unless otherwise noted.)
Note 2:Continuous short-circuit protection is allowed to the
following case and ambient temperatures: for
MAX9698, continuous short circuit is allowed on one
comparator at a time up to case temperature of +85°C
and ambient temperatures of +30°C.
PACKAGEθJC (°C/W)θJA (°C/W)
DIP75180115180
TO-99115150
PACKAGETC (°C)TA (°C)
DIP110709570
TO-999530
MAX9686C/9698CMAX9686M/9698MPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXUNITS
Input Offset VoltageVOSRS = 100Ω-3+3-3+3mV
Temperature CoefficientΔVOS/ΔT44µV/°C
Input Offset CurrentIOS5.05.0µA
Input Bias CurrentIB2525µA
Common-Mode Rejection RatioCMRR80968096dB
Power-Supply Rejection RatioPSRR70857085dB
Input Voltage Range-3.0+3.0-3.0+3.0V
Latch High Input Voltage2.02.0V
Latch Low Input Voltage0.80.8V
Latch Low Input Current-750-750µA
I/O Logic Levels (Output High
Voltage)VOHIOUT = -3mA2.43.02.43.0V
I/O Logic Levels (Output Low
Voltage)VOLIOUT = 8mA0.50.5V
MAX968616251625Positive Supply CurrentICCMAX969832503250mA
MAX968613201320N eg ati ve S up p l y C ur r entIEEMAX969826402640mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
LATCH
VIN
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
COMPARE
50%
VOS
VOD
50%
50%
tpw(E)
tpd(E)tpd
MAX9686/MAX9698
Single/Dual, Very Fast TTL Output Comparators
MAX9686 and MAX9698 Timing Diagram (worst case)
Applications Information
Layout
Because of the large gain-bandwidth characteristic of
the MAX9686 and MAX9698, special precautions need
to be taken if the high-speed capabilities of the devices
are to be realized. A PC board with ground plane
should be considered mandatory. All decoupling
capacitors should be mounted as close as possible to
the power-supply pins. For low-impedance applica-
tions, microstrip layout at the input may be helpful.
Close attention should be paid to the bandwidth of the
decoupling and terminating components. Chip compo-
nents to minimize lead inductance can be used as an
advantage. An unused latch enable pin must be con-
nected to ground.
Input Slew-Rate Requirements
As with all high-speed comparators, the high gain-
bandwidth product of these devices creates oscillation
problems when the input traverses through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and the
source impedance of the circuit employed. Both poor
layout and larger source impedance will increase the
minimum slew-rate requirement.
ELECTRICAL CHARACTERISTICS (continued)
(VS= ±5V, TA= +25°C, unless otherwise noted.)
MAX9686C/9698CMAX9686M/9698MPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXUNITS
SWITCHING CHARACTERISTICS (EACH COMPARATOR FOR MAX9698)r op ag ati on D el ays ( Guar anteed ver Ful l Tem p er atur e Rang e)
Inp ut to O utp ut H i g h
tp d + 100mV pulse; 10mV
overdrive6.09.06.09.0ns
Inp ut to O utp ut Low tp d - 100mV pulse; 10mV
overdrive5.78.55.78.5nsr op ag ati on D el ay S kew tp d + - tp d - 0.30.3ns
Latch S etup tS22ns
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Single/Dual, Very Fast TTL Output Comparators
MAX9686/9698
Definition of Terms
VOSInput Offset Voltage—The voltage required
between the input terminals to obtain 0V dif
ferential at the output.
VINInput Voltage Pulse Amplitude
VODInput Voltage Overdrive
tpd+Input to Output High Delay—The propagation
delay measured from the time the input sig
nal crosses the input offset voltage to the
50% point of an output LOW to HIGH transition.
tpd-Input to Output Low Delay—The propagation
delay measured from the time the input sig
nal crosses the input offset voltage to the
50% point of an output HIGH to LOW transition.
tpd+(E)Latch Enable to Output High Delay—The
propagation delay measured from the 50%
point of the Latch-Enable signal HIGH
LOtransition to the 50% point of an output
LOW to HIGH transition.
tpd-(E)Latch Enable to Output Low Delay—The prop
agation delay measured from the 50%
point of the Latch-Enable signal HIGH to
LOW transition to the 50% point of an output
HIGH to LOW transition.
tpw(E)Minimum Latch Enable Pulse Width—The
minimum time the Latch-Enable signal must
be LOW to acquire and hold an input signal.Minimum Setup Time—The minimum time,
before the positive transition of the Latch-
Enable pulse, that an input signal must be
present to be acquired and
held at the outputs.Minimum Hold Time—The minimum time,
after the positive transition of the Latch-
Enable signal, than an input signal must
remain unchanged to be acquired and held
at the output.
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Partno	Mfg	Dc	Qty	Available	Descript
MAX9686BCSA	MAXIM	N/a	100	avai	Single/Dual, Very Fast TTL Latched Output Comparators
MAX9698BCSE	MAXIM	N/a	4	avai	Single/Dual, Very Fast TTL Latched Output Comparators