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MAX9672ETI+-MAX9672ETI+TG0E-MAX9673ETI+-MAX9674ETI+-MAX9674ETI+T
10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs
General DescriptionThe MAX9672/MAX9673/MAX9674 output 12/14/16 volt-
age references for gamma correction in TFT LCDs and
one voltage reference for VCOM. Each gamma refer-
ence voltage has its own 10-bit DAC and buffer to
ensure a stable voltage. The VCOM reference voltage
has its own 10-bit DAC and an amplifier to ensure a sta-
ble voltage when critical levels and patterns are dis-
played. The MAX9672/MAX9673/MAX9674 feature
integrated multiple-time programmable (MTP) memory to
store gamma and VCOM values on the chip, eliminating
the need for external EEPROM. The MAX9672/
MAX9673/MAX9674 support up to 300 write operations
to the on-chip nonvolatile memory.
The gamma outputs can drive 200mA peak transient
current and settle within 1µs. The VCOM output can
provide 600mA peak transient current and also settles
within 1µs. The analog supply voltage range extends
from 9V to 20V, and the digital supply voltage range
extends from 2.7V to 3.6V.
Gamma values and the VCOM value are programmed
into registers through the I2C interface.
ApplicationsTFT LCDs
FeaturesDAC Reference Input12/14/16-Channel Gamma Correction, 10-Bit
ResolutionVCOM DriverIntegrated MTP MemoryProgrammable VCOM Limits200mA Peak Current on Gamma Channels600mA Peak Current on VCOM Channel
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs 19-4718; Rev 4; 2/11
EVALUATION KIT
AVAILABLE
Ordering Information
PARTGAMMA
CHANNELSPIN-PACKAGE
MAX9672ETI+1228 TQFN-EP*
MAX9673ETI+1428 TQFN-EP*
MAX9674ETI+1628 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Note:All devices are specified over the -40°C to +85°C temper-
ature range.
DAC
REGISTERS
I2C
REGISTERS
I2C
INTERFACE
MTP
MEMORY
10-BIT
DACGMA1
REF
10-BIT
DACGMA210
10-BIT
DACGMA310
10-BIT
DACGMA410
10-BIT
DACGMA510
10-BIT
DACGMA610
10-BIT
DACGMA710
10-BIT
DACGMA810
10-BIT
DACGMA910
10-BIT
DACGMA1010
10-BIT
DACGMA1110
10-BIT
DACGMA1210
10-BIT
DACGMA13*10
10-BIT
DACGMA14*10
10-BIT
DACGMA15**10
10-BIT
DACGMA16**
DVDD
SDA
SCL
GND
10-BIT
DACAVDD_AMP
AGND_AMP
VCOM_FB
VCOM
MAX9672
MAX9673
MAX9674
AVDD
Functional Diagram
THIN QFN
(5mm × 5mm)TOP VIEW
SCL
DVDD
AGND_AMP
VCOM
GMA16**
REFGMA7GMA6AVDDGMA5GMA4
GMA12672119171615
GMA13*
GMA14*
GMA1
GND
AVDD
AVDD_AMP
SDA
GMA88GMA15**VCOM_FB
GMA1113GMA2GMA1014GMA3GMA9
EP†
†EP = EXPOSED PAD, CONNECT EP TO GROUND PLANE.
*N.C. FOR THE MAX9672
**N.C. FOR THE MAX9672 AND THE MAX9673
MAX9672
MAX9673
MAX9674
Pin Configuration
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD= 18V, VAVDD_AMP= VREF= 18V, VDVDD= 3.3V, VGND= VAGND_AMP= 0, VCOM = VCOM_FB, no load, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltages
AVDD, REF to GND............................................-0.3V to +22V
AVDD_AMP to AGND_AMP................................-0.3V to +22V
AVDD to AVDD_AMP.........................................-0.3V to +0.3V
DVDD to GND.......................................................-0.3V to +4V
AGND_AMP to GND..........................................-0.1V to +0.1V
Outputs
GMA1–GMA16...................................-0.3V to (VAVDD+ 0.3V)
VCOM.........................................-0.3V to (VAVDD_AMP+ 0.3V)
Inputs
SDA, SCL..............................................................-0.3V to +6V
VCOM_FB...................................-0.3V to (VAVDD_AMP+ 0.3V)
SDA, SCL..........................................................................±20mA
GMA1–GMA16................................................................±200mA
VCOM.............................................................................±600mA
Continuous Power Dissipation (TA= +70°C)
28-Pin TQFN-EP (derate 28.6mW/°C
above +70°C) ........................................................2285.7mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLIESAnalog Supply Voltage RangeVAVDD,
VAVDD_AMPGuaranteed by total output error920V
Analog Supply Voltage Range for
Programming MTPVAVDD_MTP1520V
Digital Supply Voltage RangeVDVDD2.73.6V
Analog Quiescent CurrentIAVDD2035mA
VCOM Quiescent CurrentIAVDD_AMP2.75.6mA
During a register mode load event400Digital Quiescent CurrentIDVDDNo SCL or SDA transitions260600µA
Thermal Shutdown+160°C
Thermal-Shutdown Hysteresis15°C
Undervoltage Lockout ThresholdUVLODVDD undervoltage lockout voltage
threshold2.32.6V
REF Input Resistance384kΩ
VCOM OUTPUT (VCOM)ResolutionRES10Bits
Integral Nonlinearity ErrorINL0.1251LSB
Differential Nonlinearity ErrorDNL0.1251LSB
Total Output ErrorVERRCode = 512, VAVDD_AMP = 9V and 20V, TA
= +25°C-40+40mV
Total Output-Error Drift∆VERRCode = 51215µV/°C
Output-Voltage LowVOUTTA = +25°C, sinking 100mA0.40.85V
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput-Voltage HighVOUTTA = +25°C, sourcing 100mAVAVDD_AMP
- 1.1
VAVDD_AMP
- 0.6V
To AVDD_AMP, f = 60kHz, REF shorted to
VAVDD_AMP40Power-Supply Rejection RatioPSRR
9V ≤ VAVDD_AMP ≤ 20V6090
Output Load RegulationLRTransient -80mA to +80mA, code = 512±0.1mV/mA
Continuous Output CurrentIOCode = 512 (Note 2)80mA
Short-Circuit Current9V ≤ VAVDD_AMP ≤ 20V600mA
Slew RateSRSwing 4VP-P at VCOM, 10% to 90%,
RL = 10kΩ, CL = 50pF (Note 3)100V/µs
Program to Output DelaytD
From SCL rising edge for ACK bit after
programming VCOM to 50% voltage
change at output
0.8µs
BandwidthBWRS = 10kΩ, CL = 50pF (Note 3)60MHz
NoiseeNRMS noise voltage (10MHz BW)375µV
DAC OUTPUTS (GMA1–GMA16)ResolutionRESGuaranteed monotonic10Bits
Integral Nonlinearity ErrorINL0.1251LSB
Differential Nonlinearity ErrorDNL0.1251LSB
Total Output ErrorVERRCode = 512, VAVDD = 9V and 20V,
TA = +25°C-40+40mV
Output-Voltage LowVOUTTA = +25°C, sinking 10mA0.150.28V
Output-Voltage HighVOUTTA = +25°C, sourcing 10mAVAVDD
- 0.38
VAVDD
- 0.25V
To AVDD, f = 60kHz, REF shorted to
AVDD40Power-Supply Rejection RatioPSRR
9V ≤ VAVDD ≤ 20V6090
Load RegulationLR-12mA to +12mA0.5mV/mA
Short-Circuit CurrentISCOutputs to AVDD or GND200mA
Output ImpedanceZOOutput resistance when output is disabled84kΩ
Slew RateSRSwing 5VP-P at input, 10% to 90%
measurement on output22V/µs
Program to Output DelaytD
From SCL rising edge for ACK bit after
programming gamma to 50% voltage
change at output
0.8µs
NoiseeNRMS noise voltage at any output (10MHz
BW)375µV
Channel-to-Channel IsolationCXTLKf = 5MHz, all channels to all channels80dB
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= 18V, VAVDD_AMP= VREF= 18V, VDVDD= 3.3V, VGND= VAGND_AMP= 0, VCOM = VCOM_FB, no load, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= 18V, VAVDD_AMP= VREF= 18V, VDVDD= 3.3V, VGND= VAGND_AMP= 0, VCOM = VCOM_FB, no load, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS (SDA, SCL)Input High VoltageVIH0.7 x
VDVDDV
Input Low VoltageVIL0.3 x
VDVDDV
Input Leakage CurrentIIH, IILVIN = 0V or VDVDD-1+0.01+1µA
Input Capacitance5pF
Power-Down Input CurrentIINVDVDD = 0V, VIN = 2V-10+10µA
SDA Output Low VoltageVOLISINK = 6mA0.4V
I2C TIMING CHARACTERISTICS (Figure 1)Serial-Clock FrequencyfSCL0400kHz
Bus Free Time Between STOP
and START ConditionstBUF1.3µs
Hold Time (REPEATED) START
ConditiontHD,STA0.6µs
SCL Pulse-Width LowtLOW1.3µs
SCL Pulse-Width HightHIGH0.6µs
Setup Time for a REPEATED
START ConditiontSU,STA0.6µs
Data Hold TimetHD,DAT0900ns
Data Setup TimetSU,DAT100ns
SDA and SCL Receiving Rise
TimetR(Note 4)20 +
0.1CB300ns
SDA and SCL Receiving Fall
TimetF(Note 4)20 +
0.1CB300ns
SDA Transmitting Fall
TimetF,TX(Note 4)20 +
0.1CB250ns
Setup Time for STOP ConditiontSU,STO0.6µs
Bus CapacitanceCB400pF
Pulse Width of Suppressed SpiketSP050ns
Note 1:All devices are 100% production tested at TA= +25°C. All temperature limits are guaranteed by design.
Note 2:Thermal pad attached to multilayered board. Exceeding this limit may cause the thermal shutdown to trip.
Note 3:Measured with the VCOM amplifier configured as an inverting unity-gain amplifier (RS= RF= 1kΩ).
Note 4:CBis in pF.
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
OUTPUT OFFSET-VOLTAGE
DISTRIBUTIONMAX9672/73/74 toc01
OUTPUT OFFSET (mV)
N (%)
GAMMA LOAD REGULATION
MAX9672/73/74 toc02
LOAD CURRENT (mA)
LOAD REGULATION (mV)
VCOM LOAD REGULATION
MAX9672/73/74 toc03
LOAD CURRENT (mA)
LOAD REGULATION (mV)
DNL
GAMMA
MAX9672/73/74 toc04
CODE (UNITS)
DNL (LSB)
DNL
VCOM
MAX9672/73/74 toc05
DNL (LSB)
Typical Operating Characteristics(VAVDD= VAVDD_AMP= VREF= 18V, VDVDD= 3.3V, VGND= VAGND_AMP= 0, no load, unless otherwise noted. Typical values are at= +25°C.)
GAMMA
INL
MAX9672 toc06
INL (LSB)
VREF = 10V
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Typical Operating Characteristics (continued)(VAVDD= VAVDD_AMP= VREF= 18V, VDVDD= 3.3V, VGND= VAGND_AMP= 0, no load, unless otherwise noted. Typical values are at= +25°C.)
VCOM
INL
MAX9672/73/74 toc09
CODE (UNITS)
INL (LSB)
GAMMA
INL
MAX9672/73/74 toc08
CODE (UNITS)
INL (LSB)
GAMMA
DNL
CODE (UNITS)
DNL (LSB)
MAX9672
toc
VCOM
DNL
MAX9672 toc11
DNL (LSB)
VREF = 10V
VCOM
INL
MAX9672 toc07
CODE (UNITS)
INL (LSB)
VREF = 10V
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs VOUT
250mV/div
IOUT
250mA/div
VCOM PULSE RESPONSEMAX9672/73/74 toc16
TIME (2μs/div)
RISO = 10Ω
CLOAD = 68nF
-2.5V TO +2.5V
CLOAD
RISOVCOM
DAC
VOUT
1V/div
IOUT
50mA/div
GAMMA PULSE RESPONSEMAX9672/73/74 toc17
TIME (2μs/div)
RISO = 10Ω
CLOAD = 10nF
-2.5V TO +2.5V
CLOAD
RISOGAMMA
DAC
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY, GAMMA OUTPUTS
MAX9672 toc12
FREQUENCY (Hz)
PSRR (dB)100k
10k10M
VRIPPLE = 200mVP-P
CODE = 512
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY, VCOM OUTPUT
MAX9672 toc13
FREQUENCY (Hz)
PSRR (dB)100k
10k10M
VRIPPLE = 200mVP-P
CODE = 512
REFERENCE REJECTION RATIO
vs. FREQUENCY, GAMMA OUTPUTS
MAX9672 toc14
FREQUENCY (Hz)
REFERENCE REJECTION RATIO (dB)100k
10k10M
VRIPPLE = 200mVP-P
CODE = 512
REFERENCE REJECTION RATIO
vs. FREQUENCY, VCOM OUTPUT
MAX9672 toc15
FREQUENCY (Hz)
REFERENCE REJECTION RATIO (dB)100k
10k10M
VRIPPLE = 200mVP-P
CODE = 512
Typical Operating Characteristics (continued)(VAVDD= VAVDD_AMP= VREF= 18V, VDVDD= 3.3V, VGND= VAGND_AMP= 0, no load, unless otherwise noted. Typical values are at= +25°C.)
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Detailed DescriptionThe MAX9672/MAX9673/MAX9674 feature 13/15/17
total programmable reference voltage channels. Each
channel has a 10-bit DAC to create the reference volt-
age. One channel has an amplifier that follows the DAC
while all other channels have a buffer after the DAC.
The MAX9672/MAX9673/MAX9674 feature integrated
MTP memory to store gamma and VCOM values on the
chip, eliminating the need for external EEPROM. The
MAX9672/MAX9673/MAX9674 support up to 300 write
operations to the on-chip nonvolatile memory.
The MAX9672/MAX9673/MAX9674 can provide the
gamma, VCOM, and possibly level-shifter reference
voltages for an LCD panel that can potentially replace a
discrete digital variable resistor (DVR), VCOM amplifier,
Pin Description
PIN
MAX9672MAX9673MAX9674NAMEFUNCTION1, 26, 27, 281, 28—N.C.No Connection. Not internally connected.—1GMA16Gamma DAC Analog Output 1622SCLI2C-Compatible Serial-Clock Input33SDAI2C-Compatible Serial-Data Input/Output4A0I2C-Compatible Device Address Bit 055DVDDDigital Power Supply. Bypass DVDD with a 0.1µF capacitor to GND.66AGND_AMPGround for VCOM Amplifier77VCOMVCOM Output88VCOM_FBFeedback for VCOM Amplifier99AVDD_AMPPower Supply for VCOM Amplifier. Bypass AVDD_AMP with a 0.1µF
capacitor to AGND_AMP.
10, 2110, 2110, 21AVDDAnal og P ow er S up p l y. Byp ass AV D D w i th a 0.1µF cap aci tor to G N D .1111GNDAnalog Ground1212GMA1Gamma DAC Analog Output 11313GMA2Gamma DAC Analog Output 21414GMA3Gamma DAC Analog Output 31515GMA4Gamma DAC Analog Output 41616GMA5Gamma DAC Analog Output 51717GMA6Gamma DAC Analog Output 61818GMA7Gamma DAC Analog Output 71919GMA8Gamma DAC Analog Output 82020REFDAC Reference Input2222GMA9Gamma DAC Analog Output 92323GMA10Gamma DAC Analog Output 102424GMA11Gamma DAC Analog Output 112525GMA12Gamma DAC Analog Output 122626GMA13Gamma DAC Analog Output 132727GMA14Gamma DAC Analog Output 14—28GMA15Gamma DAC Analog Output 15—EPExposed Pad. EP is internally connected to the analog ground and
digital ground. EP must be connected to the system’s ground.
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDsgamma buffers, high-voltage linear regulator, and resis-
tor strings. The high-voltage linear regulator can be
eliminated because the DAC contains a lowpass filter
that reduces horizontal line frequency noise by 50dB.
Power sequencing is well controlled since a single chip
generates all the various reference voltages needed for
the LCD panel.
Each part has an I2C interface for programming both
the MTP memory and the I2C registers.
With the MTP memory and the I2C interface, the
MAX9672/MAX9673/MAX9674 enable automatic
gamma and automatic flicker calibration on a panel-by-
panel basis on the production line. Contact your Maxim
representative for more details.
10-Bit DACsThe voltage at REF sets the full-scale output of the
DACs. Determine the output voltage using the following
equation:
VOUT= (VREFx CODE)/2N
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX9672/MAX9673/MAX9674, N = 10 and CODE
ranges from 0 to 1023.
The DAC can never output REF because the maximum
value of CODE is always 1 least significant bit (LSB)
less than the reference. For example, if VREF= 16V and
CODE = 1023, then the output voltage is:
VOUT= (16V x 1023)/210
= 15.98438V
Gamma BuffersThe gamma buffers are guaranteed to source or sink
10mA of DC current within 200mV of the supplies.
The source drivers can kick back a great deal of cur-
rent to the buffer outputs during a horizontal line
change or a polarity switch. The DAC output buffers
can source/sink 200mA of peak current to reduce the
recovery time of the output voltages when critical levels
and patterns are displayed.
VCOM AmplifierThe operational amplifier attached to the VCOM DAC
holds the VCOM voltage stable while providing the abil-
ity to source and sink 600mA into the backplane of a
TFT LCD panel. The operational amplifier can directly
drive the capacitive load of the TFT LCD backplane
without the need for a series resistor in most cases. The
VCOM amplifier has current limiting on its output to pro-
tect its bond wires.
If the application requires more than 600mA, buffer the
output of the VCOM amplifier with a MAX9650, a VCOM
power amplifier. The MAX9650 can source or sink 1A of
current.
Thermal ShutdownThe MAX9672/MAX9673/MAX9674 feature thermal-
shutdown protection with temperature hysteresis. When
the die temperature reaches +165°C, all of the gamma
outputs are disabled. When the die cools down by
15°C, the outputs are enabled again.
I2C Serial InterfaceThe MAX9672/MAX9673/MAX9674 feature an I2C/
SMBus™-compatible, 2-wire serial interface consisting of
a serial-data line (SDA) and a serial-clock line (SCL).
SDA and SCL facilitate communication between the
MAX9672/MAX9673/MAX9674 and the master at clock
rates up to 400kHz. Figure 1 shows the 2-wire interface
timing diagram. The master generates SCL and initiates
data transfer on the bus. A master device writes data to
the MAX9672/MAX9673/MAX9674 by transmitting the
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD,STA
tSU,STA
tHD,STAtSP
tBUF
tSU,STOtLOW
tSU,DAT
tHD,DAT
tHIGHtF
Figure 1. I2C Serial-Interface Timing Diagram
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDsproper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each byte is serially trans-
mitted to the MAX9672/MAX9673/MAX9674 as 8 bits and
is followed by an acknowledge clock pulse. A master
reading data from the MAX9672/MAX9673/MAX9674
transmit the proper slave address followed by a series of
nine SCL pulses. The MAX9672/MAX9673/MAX9674
transmit data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω, is required on the SDA bus. SCL operates as
only an input. A pullup resistor, typically greater than
500Ω, is required on SCL if there are multiple masters on
the bus, or if the master in a single-master system has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX9672/MAX9673/MAX9674 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
Bit TransferOne data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
START and STOP ConditionsSDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 2). A START
condition from the master signals the beginning of a
transmission to the MAX9672/MAX9673/MAX9674. The
master terminates transmission, and frees the bus, by
issuing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
Early STOP ConditionsThe MAX9672/MAX9673/MAX9674 use a STOP condi-
tion at any point during data transmission except if the
STOP condition occurs in the same high pulse as a
START condition. For proper operation, do not send a
STOP condition during the same SCL high pulse as the
START condition.
Slave AddressThe slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/Wbit to 1 to configure the MAX9672/MAX9673/
MAX9674 to read mode. Set the R/Wbit to 0 to config-
ure the MAX9672/MAX9673/MAX9674 to write mode.
The address is the first byte of information sent to the
MAX9672/MAX9673/MAX9674 after the START condi-
tion. The MAX9672/MAX9673/MAX9674 slave address
is configured with A0. Table 1 shows the possible
addresses for the MAX9672/MAX9673/MAX9674.
AcknowledgeThe acknowledge bit (ACK) is a clocked 9th bit that the
MAX9672/MAX9673/MAX9674 use to handshake
receipt of each byte of data when in write mode (see
Figure 3). The MAX9672/MAX9673/MAX9674 pull down
SDA during the entire master-generated ninth clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
SCL
SDA
SSrP
Figure 2. START, STOP, and REPEATED START Conditions
READ ADDRESSWRITE ADDRESSGNDE9hE8h
DVDDEBhEAh
Table 1. Slave AddressSCL
START
CONDITION
SDA9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 3. Acknowledge
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDsa receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master may retry communication. The master
pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9672/
MAX9673/MAX9674 are in read mode. An acknowledge
is sent by the master after each read byte to allow data
transfer to continue. A not acknowledge is sent when
the master reads the final byte of data from the
MAX9672/MAX9673/MAX9674, followed by a STOP
condition.
Write Data FormatA write to the MAX9672/MAX9673/MAX9674 consists of
transmitting a START condition, the slave address with
the R/Wbit set to 0, one data byte of data to configure
the internal register address pointer, one word (two
bytes) of data or more, and a STOP condition. Figure 4
illustrates the proper frame format for writing one word
of data to the MAX9672/MAX9673/MAX9674. Figure 5
illustrates the frame format for writing n-bytes of data to
the MAX9672/MAX9673/MAX9674.
The slave address with the R/Wbit set to 0 indicates that
the master intends to write data to the MAX9672/
MAX9673/MAX9674. The MAX9672/MAX9673/MAX9674
acknowledge receipt of the address byte during the
master-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9672/MAX9673/MAX9674’s internal regis-
ter address pointer. The MAX9672/MAX9673/
MAX9674’s internal address pointer consists of the 6
LSBs of the second byte. The 2 MSBs of the second
byte (M1 and M0) are set to 00b when writing to the
internal registers. See the Memorysection for more
details. The pointer tells the MAX9672/MAX9673/
MAX9674 where to write the next byte of data. An
acknowledge pulse is sent by the MAX9672/
MAX9673/MAX9674 upon receipt of the address point-
er data.
The third and fourth bytes sent to the MAX9672/
MAX9673/MAX9674 contain the data that is written to the
chosen register and which type of register it writes to,
volatile (DAC) or nonvolatile memory (MTP). See the
1 WORD
ACKNOWLEDGE FROM
MAX9672/MAX9673/MAX9674APA0
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
R/WSLAVE ADDRESSREGISTER ADDRESSDATA BYTE 2
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER00DATA BYTE 1W0D9D8XXXXD7D6D1D0D2D4D3D5M1
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM
MAX9672/MAX9673/MAX9674
Figure 4. Writing a Word of Data to the MAX9672/MAX9673/MAX9674
1 WORDAA0
ACKNOWLEDGE FROM
MAX9672/MAX9673/MAX9674
ACKNOWLEDGE FROM
MAX9672/MAX9673/MAX9674
R/WSLAVE ADDRESSREGISTER ADDRESSDATA BYTE 2
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER00DATA BYTE 1
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674W0D9D8XXXXD7D6D1D0D2D4D3D5
1 WORDPDATA BYTE nDATA BYTE n-1W0D9D8XXXXD7D6D1D0D2D4D3D5M1
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
Figure 5. Writing n Bytes of Data to the MAX9672/MAX9673/MAX9674
MAX9672/MAX9673/MAX9674
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDsfrom the MAX9672/MAX9673/MAX9674 signals receipt of
each data byte. The address pointer autoincrements to
the next register address after receiving every other data
byte. This autoincrement feature allows a master to write
to sequential register address locations within one contin-
uous frame. The master signals the end of transmission
by issuing a STOP condition.
If data is written into register address 0x1E, the address
pointer autoincrements to 0xFF and stays at 0xFF until
the master writes a new value into the register address
pointer.
Read Data FormatThe master presets the address pointer by first sending
the MAX9672/MAX9673/MAX9674’s slave address with
the R/Wbit set to 0 followed by the register address
MTP FACTORY
INTIALIZATION VALUEREGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
MAX9672MAX9673MAX9674
READ/
WRITE0x00GMA1Gamma 10x3B00x3BA0x3C2Read and write
0x01GMA2Gamma 20x3610x3760x386Read and write
0x02GMA3Gamma 30x3120x3320x34ARead and write
0x03GMA4Gamma 40x2C40x2EE0x30ERead and write
0x04GMA5Gamma 50x2750x2AA0x2D2Read and write
0x05GMA6Gamma 60x2260x2650x295Read and write
0x06GMA7Gamma 70x1D80x2210x259Read and write
0x07GMA8Gamma 80x1890x1DD0x21DRead and write
0x08GMA9Gamma 90x13A0x1990x1E1Read and write
0x09GMA10Gamma 100x0EC0x1550x1A5Read and write
0x0AGMA11Gamma 110x09D0x1100x169Read and write
0x0BGMA12Gamma 120x04E0x0CC0x12CRead and write
0x0CGMA13Gamma 13—0x0880X0F0Read and write
0x0DGMA14Gamma 14—0x0440x0B4Read and write
0x0EGMA15Gamma 15——0x078Read and write
0x0FGMA16Gamma 16——0x03CRead and write
0x10Reserved—————
0x11Reserved—————
0x12VCOMCommon voltage0x1930x1930x193Read and write
0x13Reserved—————
0x14Reserved—————
0x15Reserved—————
0x16Reserved—————
0x17Reserved—————
0x18VCOMMINMinimum VCOM value0x10D0x10D0x10DRead and write
0x19VCOMMAXMaximum VCOM value0x21A0x21A0x21ARead and write
0x1DReserved,
DO NOT WRITE—————
0x1EReserved,
DO NOT WRITE—————
Table 2. Register Map
