MAX9671CTH+ ,Low-Power Audio/Video Switches with Audio Volume Control for Dual SCART ConnectorsApplicationsRGB, Y/C, CVBS2I CCVBS2Set-Top Boxes I C INTERFACEL/R AUDIOINTERRUPT REGISTERS AND µC(M ..
MAX9672ETI+ ,10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDsApplicationsREF AVDDTFT LCDs10 1010-BITGMA1DAC10 1010-BITPin ConfigurationGMA2DAC10 10 10-BITGMA3DA ..
MAX9672ETI+TG0E ,10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDsApplicationsREF AVDDTFT LCDs10 1010-BITGMA1DAC10 1010-BITPin ConfigurationGMA2DAC10 10 10-BITGMA3DA ..
MAX9673ETI+ ,10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDsELECTRICAL CHARACTERISTICS(V = 18V, V = V = 18V, V = 3.3V, V = V = 0, VCOM = VCOM_FB, no load, T = ..
MAX9674ETI+ ,10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDsFeaturesThe MAX9672/MAX9673/MAX9674 output 12/14/16 volt-♦ DAC Reference Inputage references for ga ..
MAX9674ETI+T ,10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDsMAX9672/MAX9673/MAX967419-4718; Rev 4; 2/1110-Bit, Programmable Gamma ReferenceSystems with MTP for ..
MB89121 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12509-6EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89120/1 ..
MB89123A ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12509-6EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89120/1 ..
MB89133A ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12510-9EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89130/1 ..
MB89153 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12506-4EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89150/1 ..
MB89163 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12405-2EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89160/1 ..
MB89163 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12405-2EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89160/1 ..
MAX9671CTH+
Low-Power Audio/Video Switches with Audio Volume Control for Dual SCART Connectors
General DescriptionThe MAX9670/MAX9671 dual SCART matrices route
audio and video signals between a set-top box
decoder chip and two external SCART connectors
under I2C control. Operating from a 3.3V supply and a
12V supply, the MAX9670/MAX9671 consume 66mW
during quiescent operation and 300mW during average
operation when driving typical signals into typical
loads. Video input detection, video load detection, and
a 2.8mW standby mode facilitate the design of intelli-
gent, low-power set-top boxes.
The MAX9670/MAX9671 audio section contains a
buffered crosspoint to route audio inputs to audio out-
puts and programmable volume control from -62dB to
0dB in 2dB steps. The DirectDrive®output amplifiers
create a 2VRMSfull-scale audio signal biased around
ground, eliminating the need for bulky output capaci-
tors and reducing click-and-pop noise. The zero-cross
detection circuitry also further reduces clicks and pops
by enabling audio sources to switch only during a zero-
crossing. The MAX9671 offers TV left and right audio
inputs.
The MAX9670/MAX9671 video section contains a
buffered crosspoint to route video inputs to video out-
puts. The standard-definition video signals from the set-
top box decoder chip are lowpass filtered to remove
out-of-band artifacts.
The MAX9670/MAX9671 also support slow-switching
and fast-switching signals. An interrupt signal from the
MAX9670/MAX9671 informs the microcontroller when
the system status has changed.
ApplicationsSet-Top Boxes
TVs
DVD Players
Features66mW Quiescent Power Consumption2.8mW Standby Mode ConsumptionProgrammable Audio Gain Control of -62dB to
0dB (TV Audio Outputs)Clickless, Popless, DirectDrive AudioVideo Input and Video Load Detection Video Reconstruction Filter with 10MHz Passband
and 52dB Attenuation at 27MHz3.3V and 12V Supply Voltages
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors19-4653; Rev 2; 12/10
EVALUATION KITAVAILABLE
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
TV R+L
AUDIO
INPUTS
MAX9670CTL+0°C to +70°C40 TQFN-EP*No
MAX9671CTH+0°C to +70°C44 TQFN-EP*Yes
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
DirectDrive is a registered trademark of Maxim Integrated
Typical Application Circuit appears at end of data sheet.I2C INTERFACE
REGISTERS AND
ACTIVITY
MONITOR
VIDEO FILTERS AND
CROSSPOINT
AUDIO CROSSPOINT
WITH DIRECTDRIVE
OUTPUTS, VOLUME
CONTROL
SLOW SWITCHING
FAST SWITCHING
CHARGE PUMP
V12VAUDVVID
12V3.3V3.3VGNDVID
µC
VIDEO
ENCODER
STEREO
AUDIO
DAC
I2C
INTERRUPT
OUTPUT
RGB, Y/C, CVBS
SINGLE-ENDED R/L
STEREO AUDIO
RGB, Y/C, CVBS
CVBS
L/R AUDIO
(MAX9671 ONLY)
SLOW SWITCHING
Y/C, CVBS
RGB, Y/C, CVBS
L/R AUDIO
SLOW SWITCHING
STB CHIP
SCART
VCR
SCART
FAST SWITCHING
FAST SWITCHING
L/R AUDIO
(MAX9670 ONLY)
MAX9670/MAX9671
System Block Diagram
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(V12= 12V, VVID= VAUD= 3.3V, VGNDVID= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VVIDto GNDVID........................................................-0.3V to +4V
V12to EP.................................................................-0.3V to +14V
VAUDto EP...............................................................-0.3V to +4V
EP to GNDVID.......................................................-0.1V to +0.1V
All Video Inputs, VCRIN_FS to GNDVID...................-0.3V to +4V
All Audio Inputs to EP.......................................-1V to (VEP+ 1V)
SDA, SCL, DEV_ADDR, INTto GNDVID..................-0.3V to +4V
TV_SS, VCR_SS to EP.................................-0.3V to (V12+ 0.3V)
Current
All Video/Audio Inputs...................................................±20mA
C1P, C1N, CPVSS.........................................................±50mA
Output Short-Circuit Current Duration
Video and Fast-Switching Outputs to VVID,
GNDVID.................................................................Continuous
Audio Outputs to VAUD, EP.....................................Continuous
TV_SS, VCR_SS to V12, EP......................................Continuous
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN-EP (derate 26.3mW/°C above +70°C)...2105.3mW
44-Pin TQFN-EP (derate 26.3mW/°C above +70°C)...2222.2mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
40/44-pin TQFN-EP.........................................................1°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
40/44-pin TQFN-EP.......................................................27°C/W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVideo Supply Voltage RangeVVIDInferred from video PSRR test at 3V and
3.6V33.33.6V
Audio Supply Voltage RangeVAUDInferred from audio PSRR test at 3V and
3.6V33.33.6V
V12 Supply Voltage RangeV12Inferred from slow-switching levels11.41212.6V
Normal operation; all video output
amplifiers are enabled and muted (Note 3)1630mA
Standby mode, slow switch inputs low1500VVID Quiescent Supply CurrentIVID_Q
Shutdown35µA
Normal operation (Note 3)3.26mAVAUD Quiescent Supply CurrentIAUD_QShutdown35µA
Slow-switching output
set to low-level0.3100
Normal operation
(Note 3)Slow-switching output
set to medium-level475V12 Quiescent Supply CurrentI12_Q
Shutdown, TA = +25°C10µA
VIDEO CHARACTERISTICS
DC-COUPLED INPUTVVID = 3V1.15
VVID = 3.135V1.15Input Voltage RangeVIN
RL = 75Ω to
GNDVID or 150Ω
to VVID/2; inferred
from gain testVVID = 3.3V1.3
VP-P
Input CurrentIINVIN = 0.3V, TA = +25°C12µA
Note 1:Package thermal resistance were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
AC-COUPLED INPUTSync-Tip Clamp LevelVCLPSync-tip clamp-13-4+6mV
Sync Crushync- ti p cl am p ; p er centag e r ed ucti on i n
sync p ul se ( 0.3V P - P ) ; g uar anteed b y i np ut
cl am p i ng cur r ent m easur em ent, TA = + 25° C
Input Clamping CurrentSync-tip clamp, VIN = 0.3V, TA = +25°C12µA
Maximum Input Source
Resistance
Input sync-tip circuit must be stable even if
the source resistance is as high as 300Ω300Ω
Bias circuit0.570.60.63
Input VoltageHigh-impedance input circuit0.3 x
VVID
0.36 x
VVID
Bias circuit10Input ResistanceHigh-impedance input circuit222kΩ
DC CHARACTERISTICSDC Voltage GainAVGuaranteed by output voltage swing1.9522.05V/V
DC Gain Mismatch Among R, G,
and B Outputs
Guaranteed by output voltage swing of
TV_R/C_OUT, TV_G_OUT, and TV_B_OUT;
first input signal set is VCR_R/C_IN,
VCR_G_IN, and VCR_B_IN; second signal
set is ENC_R/C_IN, ENC_G_IN, and
ENC_B_IN+2%
Sync-tip clamp (VIN = VCLP)0.10.300.51Output LevelBias circuit1.31.51.78V
Sync-tip clamp, measured at output,
VVID = 3V, VIN = VCLP to (VCLP +1.15V),
RL = 150Ω to VVID/2, RL = 75Ω to GNDVID
Measured at output, VVID = 3.135V, VIN =
VCLP to (VCLP + 1.15V), RL = 150Ω to
VVID/2, RL = 75Ω to GNDVID
Bias circuit, measured at output, VVID = 3V,
VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V),
RL = 150Ω to VVID/2, RL = 75Ω to GNDVID
Output Voltage Swing
Measured at output, VVID = 3.135V,
VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V),
RL = 150Ω to VVID/2, RL = 75Ω to GNDVID
VP-P
Output Short-Circuit Current100mA
Output ResistanceROUT0.5Ω
Output Leakage CurrentOutput disabled (load detection not active)170µA
Power-Supply Rejection Ratio3V ≤ VVID ≤ 3.6V35dB
ELECTRICAL CHARACTERISTICS (continued)(V12= 12V, VVID= VAUD= 3.3V, VGNDVID= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at= +25°C.) (Note 2)
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)(V12= 12V, VVID= VAUD= 3.3V, VGNDVID= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
AC CHARACTERISTICSFilter Passband FlatnessVOUT = 2VP-P, f = 100kHz to 5.5MHz-1dB
f = 9.5MHz3
f = 27MHz40Filter Attenuation
VOUT = 2VP-P,
attenuation is
referred to 100kHzf = 54MHz55
Slew RateVOUT = 2VP-P, no filter in video path60V/µs
Settling TimeVOUT = 2VP-P, settle to 0.1% (Note 4)400ns
Differential GainDG5-step modulated staircase, f = 4.43MHz0.15%
Differential PhaseDP5-step modulated staircase, f = 4.43MHz0.5Degrees
2T Pulse-to-Bar K Rating
2T = 200ns, bar time is 18µs, the beginning
2.5% and the ending 2.5% of the bar time is
ignored
0.3K%
2T Pulse Response2T = 200ns0.2K%
2T Bar Response
2T = 200ns, bar time is 18µs, the beginning
2.5% and the ending 2.5% of the bar time is
ignored
0.2K%
Nonlinearity5-step staircase0.1%
Group Delay Distortion100kHz ≤ f ≤ 5MHz, outputs are 2VP-P11ns
Glitch Impulse Caused by
Charge-Pump SwitchingMeasured at outputs100pV-s
Peak Signal to RMS Noise100kHz ≤ f ≤ 5MHz70dB
Power-Supply Rejection Ratiof = 100kHz, 100mVP-P47dB
Output Impedancef = 5MHz2Ω
Video Crosstalkf = 4.43MHz-80dB
Reverse Isolation
VCR SCART inputs to encoder inputs,
full-power mode with VCR being looped
through to TV, f = 4.43MHzdB
Pulldown ResistanceEnable VCR_R/C_OUT pulldown through
I2C interface4.47.5Ω
AUDIO CHARACTERISTICSVoltage GainVIN = -0.707V to +0.707V3.9544.05V/V
Gain MismatchVIN = -0.707V to +0.707V-1.5+1.5%
Flatnessf = 20Hz to 20kHz, 0.25VRMS input0.006dB
Frequency Bandwidth0.25VRMS input, frequency where output is
-3dB referenced to 1kHz230kHz
Capacitive DriveNo sustained oscillations; 75Ω series
resistor on output300pF
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)(V12= 12V, VVID= VAUD= 3.3V, VGNDVID= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput ResistanceVIN = -0.707V to +0.707V10MΩ
Input Bias CurrentVIN = 0, TA = +25°C500nA
Input Signal Amplitudef = 1kHz, THD < 1%0.5VRMS
Output DC LevelNo input signal, VIN grounded-4+4mV75100Power-Supply Rejection Ratiof = 1kHz90dB
Signal-to-Noise Ratiof = 1kHz, 0.25VRMS input, 20Hz to 20kHz96dB
RL = 3.33kΩ, f = 1kHz, 0.25VRMS input0.002Total Harmonic Distortion Plus
NoiseRL = 3.33kΩ, f = 1kHz, 0.5VRMS input0.001%
Output Impedancef = 1kHz0.4Ω
Volume Control Attenuation StepProgrammable gain to TV SCART volume
control from -62dB to 02dB
Volume Control Minimum
Attenuation0dB
Volume Control Maximum
Attenuation62dB
Mute Suppressionf = 1kHz, 0.25VRMS input110dB
Audio Crosstalkf = 1kHz, 0.25VRMS input100dB
VIDEO-TO-AUDIO INTERACTIONCrosstalkVideo input: f = 15kHz, 1VP-P signal
Audio input: f = 15kHz, 0.5VRMS signal92dB
CHARGE PUMPSwitching Frequency570kHz
FAST SWITCHINGInput Low0.4V
Input High Level1V
Input CurrentTA = +25°C10µA
Output Low VoltageIOL = 0.5mA0.1V
Output High VoltageIOH = 0.5mAVVID -
0.1V
Output Resistance7Ω
Rise Time143Ω to GNDVID12ns
Fall Time143Ω to GNDVID10ns
SLOW SWITCHINGInput Low Voltage2V
Input Medium Voltage4.57V
Input High Voltage9.5V
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)(V12= 12V, VVID= VAUD= 3.3V, VGNDVID= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput Current70100µA
Output Low Voltage10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V1.5V
Output Medium Voltage10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V56.5V
Output High Voltage10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V10V
DIGITAL INTERFACEInput High VoltageVIH0.7 x
VVIDV
Input Low VoltageVIL0.3 x
VVIDV
Input HysteresisVHYS0.06 x
VVIDV
Input Leakage CurrentIIH, IILTA = +25°C-1+1µA
Input Capacitance6pF
Input Current
0.1VVID < SDA < 3.3V,
0.1VVID < SCL < 3.3V
I/O pins of fast-mode devices must not
obstruct the SDA and SCL lines if V+ is
switched off, TA = +25°C
-10+10µA
Output Low Voltage SDAVOLISINK = 6mA0.4V
Serial-Clock FrequencyfSCL0400kHz
Bus Free Time Between a STOP
and a START ConditiontBUF1.3µs
Hold Time, (Repeated) START
ConditiontHD, STA0.6µs
Low Period of the SCL ClocktLOW1.3µs
High Period of the SCL ClocktHIGH0.6µs
Setup Time for a Repeated
START ConditiontSU, STA0.6µs
Data Hold TimetHD, DAT(Note 5)00.9µs
Data Setup TimetHD, DAT100ns
Fall Time of SDA TransmittingtF
ISINK ≤ 6mA, CB = total capacitance of one
bus line in pF, tR and tF measured between
0.3VVID and 0.7VVID
100ns
Setup Time for STOP ConditiontSU, STO0.6µs
Pulse Width of Spike SuppressedtSPInput filters on the SDA and SCL inputs
suppress noise spikes less than 50ns050ns
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)(V12= 12V, VVID= VAUD= 3.3V, VGNDVID= VEP= 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OTHER DIGITAL I/ODEV_ADDR Low Level0.3 x
VVIDV
DEV_ADDR High Level0.7 x
VVIDV
DEV_ADDR Input CurrentTA = +25°C-1+1µA
Interrupt Output Low VoltageIOL = 0.5mA0.1V
Interrupt Output Leakage CurrentINT high impedance, TA = +25°C10µA
Note 2:All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
Note 3:Normal operation mode is full power with input video and load detection active.
Note 4:The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output.
Note 5:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Typical Operating Characteristics(VVID= VAUD= 3.3V, V12= 12V, VGNDVID= VEP= 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
SMALL-SIGNAL GAIN
vs. FREQUENCYMAX9670 toc01
FREQUENCY (Hz)
GAIN (dB)
100M10M1M
100k1G
NO FILTER
VOUT = 100mVP-P
FILTER
SMALL-SIGNAL GAIN FLATNESS
vs. FREQUENCYMAX9670 toc02
FREQUENCY (Hz)
GAIN (dB)
10M100M
NO FILTER
VOUT = 100mVP-P
FILTER
LARGE-SIGNAL GAIN
vs. FREQUENCYMAX9670 toc03
FREQUENCY (Hz)
GAIN (dB)
100M10M1M
100k1G
NO FILTER
VOUT = 2VP-P
FILTER
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Typical Operating Characteristics (continued)(VVID= VAUD= 3.3V, V12= 12V, VGNDVID= VEP= 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCYMAX9670 toc04
FREQUENCY (Hz)
GAIN (dB)
10M100M
NO FILTER
FILTER
VIDEO CROSSTALK
vs. FREQUENCYMAX9670 toc05
FREQUENCY (Hz)
DELAY (ns)
10M1M
100k100M
VOUT = 100mVP-P
ALL HOSTILE
GROUP DELAY
vs. FREQUENCYMAX9670 toc06
FREQUENCY (Hz)
DELAY (ns)
10M1M
100k100M
VOUT = 2VP-P
FILTER
NO FILTER
VIDEO POWER-SUPPLY REJECTION RATIO
vs. FREQUENCYMAX9670 toc07
FREQUENCY (Hz)
PSRR (dB)
10M1M
100k100M
FILTER
NO FILTER
VIDEO VOLTAGE GAIN
vs. TEMPERATUREMAX9670 toc08
TEMPERATURE (°C)
VOLTAGE GAIN (V/V)25
VIDEO OUTPUT VOLTAGE
vs. INPUT VOLTAGE
MAX9670 toc09
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
DIFFERENTIAL GAIN AND PHASE
MAX9670 toc10
DIFFERENTIAL PHASE (deg)02345
DIFFERENTIAL GAIN (%)
DIFFERENTIAL GAIN AND PHASE
MAX9670 toc11
DIFFERENTIAL PHASE (deg)02345
DIFFERENTIAL GAIN (%)
-0.30234580ns/div
2T WITH FILTERVIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc12
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Typical Operating Characteristics (continued)(VVID= VAUD= 3.3V, V12= 12V, VGNDVID= VEP= 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
80ns/div
2T NO FILTERVIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc13
1μs/div
12.5T WITH FILTERVIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc14
1μs/div
12.5T NO FILTERVIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc15
10μs/div
NTC7 WITH FILTERVIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
MAX9670 toc16
10μs/div
NTC7 NO FILTERVIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
MAX9670 toc17
2ms/div
FIELD SQUARE WAVEVIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
MAX9670 toc18
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Typical Operating Characteristics (continued)(VVID= VAUD= 3.3V, V12= 12V, VGNDVID= VEP= 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
VIDEO INPUT SYNC-TIP CLAMP VOLTAGE
vs. TEMPERATUREMAX9670 toc19
TEMPERATURE (°C)
INPUT CLAMP VOLTAGE (mV)2575
VIDEO INPUT BIAS VOLTAGE
vs. TEMPERATUREMAX9670 toc20
TEMPERATURE (°C)
INPUT BIAS VOLTAGE (mV)25
VIDEO INPUT SYNC-TIP CLAMP CURRENT
vs. TEMPERATURE
MAX9670 toc21
TEMPERATURE (°C)
INPUT CLAMP CURRENT (mA)25
VIDEO INPUT SYNC-TIP CLAMP CURRENT
vs. INPUT VOLTAGE
MAX9670 toc22
INPUT VOLTAGE (V)
INPUT CLAMP CURRENT (
VIDEO OUTPUT BIAS VOLTAGE
vs. TEMPERATUREMAX9670 toc23
OUTPUT BIAS VOLTAGE (V)25
AUDIO LARGE-SIGNAL GAIN
vs. FREQUENCY
MAX9670 toc24
GAIN (dB)
100k10k1k100
-201M
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART ConnectorsVVID QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
MAX9670 toc28
TEMPERATURE (°C)
CURRENT (mA)
VAUD QUIESCENT SUPPLY CURRENT
vs. TEMPERATUREMAX9670 toc29
CURRENT (mA)
V12 QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
MAX9670 toc30
CURRENT (nA)25
Typical Operating Characteristics (continued)
(VVID= VAUD= 3.3V, V12= 12V, VGNDVID= VEP= 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
AUDIO CROSSTALK
vs. FREQUENCYMAX9670 toc25
FREQUENCY (Hz)
CROSSTALK (dB)
10k1k100
-120100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCYMAX9670 toc26
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.0001100k
TVIN TO
VCROUT
VIN = 0.25VRMS
TVIN TO
TVOUT
VAUD POWER-SUPPLY REJECTION RATIO
(INPUT REFERRED) vs. FREQUENCYMAX9670 toc27
FREQUENCY (Hz)
PSRR (dB)
10k1k100
-120100k
VAUD = 3.3V + 100mVP-P
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Pin Description
PIN
MAX9670MAX9671NAMEFUNCTION1SDABidirectional I2C Data I/O. Output is open drain and tolerates up to 3.6V.2SCLI2C Clock Input3DEV_ADDRDevice Address Set Input. Connect to GNDVID, VVID, SDA or SCL. See Table 3.INT
Interrupt Output. This is an open-drain output that pulls down to GNDVID to
indicate a change in the VCR slow switching or fast switching input, the activity
status of the composite video inputs, or the load status of the composite video
outputs.VAUDAudio Supply. Connect to a 3.3V supply. Bypass with a 10µF aluminum
electrolytic capacitor and a 0.47µF ceramic capacitor to EP.6C1PCharge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF capacitor
from C1P to C1N.7C1NCharge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF capacitor
from C1P to C1N.8CPVSSC har g e- P um p N eg ati ve P ow er S up p l y. Byp ass w i th a 1µF cer am i c cap aci tor to E P .9ENC_INLEncoder Left-Channel Audio Input10ENC_INREncoder Right-Channel Audio Input11TV_INLTV SCART Left-Channel Audio Input12TV_INRTV SCART Right-Channel Audio Input13VCR_INLVCR SCART Left-Channel Audio Input14VCR_INRVCR SCART Right-Channel Audio Input15TV_OUTLTV SCART Left-Channel Audio Output16VCR_OUTLVCR SCART Left-Channel Audio Output17VCR_OUTRVCR SCART Right-Channel Audio Output18TV_OUTRTV SCART Right-Channel Audio Output19TV_SSTV SCART Bidirectional Slow-Switch Signal20V12+12V Supply for the Slow Switching Circuit. Bypass with a 10µF + 0.47µF ceramic
capacitor to EP.21VCR_SSVCR SCART Bidirectional Slow-Switch Signal22TVOUT_FSTV SCART Fast-Switching Logic Output23, 44N.C.No Connection. Leave unconnected.24VCRIN_FSVCR SCART Fast-Switching Logic Input25ENC_B_INEncoder Blue Video Input26ENC_G_INEncoder Green Video Input27VCR_B_INVCR SCART Blue Video Input28VCR_G_INVCR SCART Green Video Input29TV_B_OUTTV SCART Blue Video Output30TV_G_OUTTV SCART Green Video Output
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Detailed DescriptionThe MAX9670/MAX9671 represents Maxim’s third gen-
eration of SCART audio/video (A/V) switches. Under I2C
control, these devices route audio, video, and control
information between the set-top box decoder chip and
two SCART connectors. The audio signals are left audio
and right audio. The video signals are composite video
with blanking and sync (CVBS) and component video
(red, green, blue). S-video (Y/C) can be transported
across the SCART interface if CVBS is reassigned to
luma (Y) and red is reassigned to chroma (C). Support
for S-video is optional. The slow-switch signal and the
fast-switch signal carry control information. The slow-
switch signal is a 12V, three-level signal that indicates
whether the picture aspect ratio is 4:3 or 16:9 or causes
the television to use an internal A/V source such as an
antenna. The fast-switch signal indicates whether the
television should display CVBS or RGB signals.
CVBS, left audio, and right audio are full duplex. All the
other signals are half duplex. Therefore, one device on
the link must be designated as the transmitter, and the
other device must be designated as the receiver.
The low power consumption and the advanced monitor-
ing functions of the MAX9670/MAX9671 enable the cre-
ation of lower power set-top boxes, televisions, and
DVD players. Unlike competing SCART ICs, the audio
and video circuits of the MAX9670/MAX9671 operate
entirely from 3.3V rather than from 5V and 12V. Only the
slow-switch circuit of the MAX9670/MAX9671 requires a
12V supply. The MAX9670/MAX9671 also have circuits
that detect activity on the CVBS inputs, loads on the
CVBS outputs, and the level of the slow-switch signals.
The INTsignal informs the microcontroller if there are
any changes so that the microcontroller can intelli-
gently decide whether to power up or power down
the equipment.
In addition, the MAX9670/MAX9671 have DirectDrive
audio circuitry to eliminate click-and-pop noise. With
DirectDrive, the DC bias of the audio line outputs is
always at ground, no matter whether the MAX9670/
MAX9671 are being powered up or powered down.
Conventional audio line output drivers that operate from a
single supply require series AC-coupling capacitors.
During power-up, the DC bias on the AC-coupling capac-
itor moves from ground to a positive voltage, and during
power-down, the opposite occurs. The changing DC bias
usually causes an audible transient.
Pin Description (continued)
PIN
MAX9670MAX9671NAMEFUNCTION31GNDVIDVideo Ground32VCR_R/C_INVCR SCART Red/Chroma Video Input33VVID
Video and Digital Supply. Connect to a 3.3V supply. Bypass with parallel 1µF and
0.1µF ceramic capacitors to GNDVID. VVID also serves as a digital supply for the
I2C interface.34ENC_C_INEncoder Chroma Video Input35ENC_R/C_INEncoder Red/Chroma Video Input36TV_R/C_OUTTV SCART Red/Chroma Video Output37VCR_R/C_OUTVCR SCART Red/Chroma Video Output38VCR_Y/CVBS_OUTVCR SCART Luma/Composite Video Output39TV_Y/CVBS_OUTTV SCART Luma/Composite Video Output40VCR_Y/CVBS_INVCR SCART Luma/Composite Video Input41TV_Y/CVBS_INTV SCART Luma/Composite Video Input42ENC_Y_INEncoder Luma Video Input43ENC_Y/CVBS_INEncoder Luma/Composite Video InputEP
Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and
charge pump. A low-impedance connection between ground and EP is required
for proper isolation.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Audio SectionThe MAX9670 audio circuit is essentially a stereo,
2-by-2, nonblocking, audio crosspoint with output dri-
vers. The encoder (stereo audio DAC) and the VCR are
the two input sources, and the two outputs go to the TV
SCART connector and the VCR SCART connector. See
Figure 1. The MAX9671 audio circuit is similar to that of
the MAX9670 except that it is a stereo, 3-by-2,
nonblocking audio crosspoint with TV as the third input
source.
The integrated charge pump inverts the +3.3V supply
to create a -3.3V supply. The audio circuit operates
from bipolar supplies so the audio signal is always
biased to ground.
ENC_INL
VCR_INL
ZCD
(0.5VRMS FULL-SCALE INPUT)(2VRMS FULL-SCALE OUTPUT)
(2VRMS FULL-SCALE OUTPUT)
TV_OUTL
TV_OUTR
MUTE
VAUD
C1P
C1N
CPVSS
CHARGE
PUMP
SCL
SDAREGISTER
CONTROL
DEV_ADDR
MUTE
MUTE
MUTE
MUTE
VCR_OUTL
VCR_OUTR
*TV_INL
ENC_INR
VCR_INR
*TV_INR
VOLUME
CONTROL
0dB TO -62dB
VOLUME
CONTROL
0dB TO -62dB
*MAX9671 ONLY.
MUTE
MAX9670/MAX9671
Figure 1. MAX9670/MAX9671 Audio Section Functional Diagram
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Clickless SwitchingThe TV audio channel incorporates a zero-crossing
detect (ZCD) circuit that minimizes click noise due to
abrupt signal level changes that occur when switching
between audio signals at an arbitrary moment.
To implement the zero-crossing function when switch-
ing audio signals, set the ZCD bit high (Audio Control
register00h, bit 6). Then set the mute bit high (Audio
Control register 00h, bit 0). Next, wait for a sufficient
period of time for the audio signal to cross zero. This
period is a function of the audio signal path’s low-fre-
quency 3dB corner (fL3dB). Thus, if fL3dB= 20Hz, the
time period to wait for a zero-crossing detect is 1/20Hz
or 50ms.
After the wait period, select a new audio source for the
TV audio channel by writing to bits 1 and 0 of TV Audio
Control register (01h). Finally, clear mute (Audio Control
register, 00h, bit 0), but leave ZCD (Audio Control reg-
ister 00h, bit 6) high. The MAX9670/MAX9671 switches
the signal out of mute at the next zero crossing. See
Tables 12 and 13.
Audio OutputsThe MAX9670/MAX9671 audio output amplifiers feature
Maxim’s DirectDrive architecture, thereby eliminating
the need for output-coupling capacitors required by
conventional single-supply audio line drivers. An inter-
nal charge pump inverts the positive supply (VAUD),
creating a negative supply (CPVSS). The audio output
amplifiers operate from these bipolar supplies with their
outputs biased about audio ground (Figure 2). The ben-
efit of this audio ground bias is that the amplifier out-
puts do not have a DC component. The DC-blocking
capacitors required with conventional audio line drivers
are unnecessary, conserving board space, reducing
system cost, and improving frequency response.
Conventional single-supply audio line drivers have their
outputs biased about a nominal DC voltage (typically
half the supply) for maximum dynamic range. Large
coupling capacitors are needed to block this DC bias.
Clicks and pops are created when the coupling capaci-
tors are charged during power-up and discharged dur-
ing power-down.
The MAX9670/MAX9671 features a low-noise charge
pump that requires only two small ceramic capacitors.
The 580kHz switching frequency is well beyond the
audio range and does not interfere with audio signals.
The switch drivers feature a controlled switching speed
that minimizes noise generated by turn-on and turn-off
transients.
The SCART standard specifies 2VRMSas the full-scale
for audio signals. As the audio circuits process
0.5VRMSfull-scale audio signals internal to the
MAX9670/MAX9671, the gain-of-4 output amplifiers
restore the audio signals to a full-scale of 2VRMS.
To select which audio input source is routed to the TV
SCART connector, write to bits 1 and 0 of the TV Audio
Controlregister(01h). To select which audio input
source is routed to the VCR SCART connector, write to
bits 3 and 2 of the TV Audio Control register (01h). The
power-on default is for the TV and VCR audio outputs to
be muted (the inputs of the output amplifiers are con-
nected to audio ground). See Tables 10 and 13.
Volume ControlVolume control is programmable from -62dB to 0dB in
2dB steps through I2C interface. The block consists of
a resistive ladder network to generate 31 2dB volume
control steps, a unity gain buffer to isolate the input
from the resistive ladder, switches (MPLx and MNLx)
that select 1 of 32 nodes on the resistive ladder, and
logic to decode the the I2C volume control value. See
Table 12.
+VDD
-VDD
GNDVOUT
CONVENTIONAL DRIVER-BIASING SCHEME
DirectDrive BIASING SCHEME
VDD/2
VDD
VDD
GND
2VDD
Figure 2. Conventional Driver Output Waveform vs. MAX9670/
MAX9671 Output Waveform.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Video SectionThe video circuit routes different video formats between
the VCR SCART connector. It also routes slow-switch
and fast-switch control information. See Figure 3.
MAX9670/MAX9671
AV = 2V/V
TV_Y/CVBS_IN
MUTE
TV_Y/CVBS_OUT
LOAD SENSE
AV = 2V/VVCR_Y/CVBS_OUT
LOAD SENSE
CLAMP
VCR_Y/CVBS_INCLAMP
ENC_Y/CVBS_INCLAMP
ENC_Y_INCLAMP
ACTIVITY DETECT
ACTIVITY DETECT
ACTIVITY DETECT
ACTIVITY DETECT
LPF
LPF
AV = 2V/V
MUTE
TV_R/C_OUT
AV = 2V/VVCR_R/C_OUT
VCR_R/C_INCLAMP/BIAS
ENC_R/C_INCLAMP/BIAS
ENC_C_INCLAMP/BIAS
LPF
LPF
AV = 2V/V
MUTE
TV_G_OUT
VCR_G_INCLAMP
ENC_G_INCLAMPLPF
AV = 2V/V
MUTE
TV_B_OUT
VCR_B_INCLAMP
ENC_B_INCLAMPLPF
AV = 1V/V
VCRIN_FS
0.7V
VVID
GNDVID
TVOUT_FS
TO I2C
AV = 1V/V
V12
+6V
TV_SS
TO I2C
AV = 1V/V
V12
+6V
VCR_SS
Figure 3. MAX9670/MAX9671 Video Section Function Diagram
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Video InputsWhether the incoming video signal is AC-coupled or
DC-coupled into the MAX9670/MAX9671 depends
upon the origin, format, and voltage range of the video
signal. Table 1 below shows the recommended con-
nections. Always AC-couple an external video signal
through a 0.1µF capacitor because its voltage is not
well defined (see the Typical Application Circuit). For
example, the video transmitter circuit might have a dif-
ferent ground than the video receiver, thereby level
shifting the DC bias. 60Hz power line hum might cause
the video signal to change DC bias slowly.
Internal video signals that are between 0 and 1V can be
DC-coupled. Most video DACs generate video signals
between 0 and 1V because the video DAC sources cur-
rent into a ground-referenced resistor. For the minority
of video DACs that generate video signals between
2.3V and 3.3V because the video DAC sinks current
from a VVID-referenced resistor, AC-couple the video
signal to the MAX9670/MAX9671.
The MAX9670/MAX9671 restore the DC level of incom-
ing, AC-coupled video signals with either transparent
sync-tip clamps or bias circuits. When using an AC-
coupled input, the transparent sync-tip clamp automati-
cally clamps the input signal minimum to ground,
preventing it from going lower. A small current of 1µA
pulls down on the input to prevent an AC-coupled sig-
nal from drifting outside the input range of the part. Use
sync-tip clamps with CVBS, RGB, and luma signals.
The transparent sync-tip clamp is transparent when the
incoming video signal is DC-coupled and at or above
ground. Under such conditions, the clamp never acti-
vates. Therefore, the outputs of video DACs that gener-
ate signals between 0 and 1V can be directly
connected to the MAX9670/MAX9671 inputs.
The bias circuit accepts AC-coupled chroma, which is
a subcarrier with the color information modulated onto
it. The bias voltage of the bias circuits is around
600mV.
ENC_R/C_IN and VCR_R/C_IN can receive either a red
video signal or a chroma video signal. Set the input con-
figuration by writing to bits 7 and 3 of the VCR Video
Input Control register (08h). See Tables 10 and 16.
The MAX9670/MAX9671 also have video input detec-
tion. When activated, activity detect circuits check if
sync is present on incoming CVBS and luma (Y) sig-
nals. If so, then there is a valid video signal. Read bits
0, 2, 4, and 5 of the Video Activity Status register (0Fh)
to determine the status of the CVBS and luma (Y)
inputs. See Table 21.
In high-impedance mode, the inputs to the MAX9670/
MAX9671 do not distort the video signal in case the out-
puts of the video DAC are also connected to another
video circuit such as a high-definition video filter amplifi-
er. See the SCART Set-Top Box with Analog HD Outputs
section. The inputs in high-impedance mode are biased
at VVID/3, which is sufficiently above ground so that the
ESD diodes never forward biases as the video signal
changes. The input resistance is 222kΩ, which presents
negligible loading on the video current DAC.
Video Reconstruction FilterThe video DAC outputs of the set-top box decoder chip
need to be lowpass-filtered to reject the out-of-band
noise. The MAX9670/MAX9671 integrate sixth-order,
Butterworth filters. The filter passband (±1dB) is typical-
ly 5.5MHz, and the attenuation at 27MHz is 52dB. The
filters are suited for standard-definition video.
Video OutputsThe video output amplifiers can both source and sink
load current, allowing output loads to be DC- or AC-
coupled. The amplifier output stage needs around
300mV of headroom from either supply rail. For video
signals with a sync pulse, the sync tip is typically at
300mV, as shown in Figure 4. For a chroma signal, the
blank level is typically at 1.5V, as shown in Figure 5.
If the supply voltage is greater than 3.135V (5% below
a 3.3V supply), each amplifier can drive two DC-cou-
pled video loads to ground. If the supply is less than
3.135V, each amplifier can drive only one DC-coupled
or AC-coupled video load.
The SCART standard allows for video signals to have a
superimposed DC component within 0 and 2V.
Therefore, most video signals are DC-coupled at the
output. In the unlikely event that the video signal needs
to be AC-coupled, the coupling capacitors should be
220µF or greater to keep the highpass filter formed by
the 37.5Ωequivalent resistance of the video transmis-
sion line to a corner frequency of 4.8Hz or below to keep
it well below the 25Hz frame rate of the PAL standard.
The CVBS outputs have load sense circuits. If enabled,
each load sense circuit checks for a load eight times
per second by connecting an internal 15kΩpullup
resistor to the output for 1ms. If the output is pulled up,
no load is present. If the output stays low, a load is con-
nected. Read bits 1 and 3 of the Video Activity Status
register (0Fh) to determine load status. See Table 21.
The selection of video sources that are sent to the TV
SCART connector are controlled by bits 0 to 4 of the TV
Video Input Control register (06h) while the selection of
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectorsvideo sources that are sent to the VCR SCART connec-
tor are controlled by bits 0 to 2 of the VCR Video Input
Control register (08h). See Tables 10, 14, and 16. The
video outputs can be enabled or disabled by bits 2
through 7 of the Output Enable register (0Dh). See
Table 18.
Slow SwitchingThe MAX9670/MAX9671 support the IEC 933-1,
Amendment 1, three-level slow switching that selects
the aspect ratio for the display (TV). Under I2C control,
the MAX9670/MAX9671 set the slow-switching output
voltage level. Table 2 shows the valid input levels of the
slow-switching signal and the corresponding operating
modes of the display device.
Two bidirectional ports are available for slow-switching
signals for the TV and VCR. The slow-switching input
status is continuously read and stored in the Status reg-
ister (0Eh). The slow-switching outputs can be set to a
logic level or high impedance by writing to the TV Video
Output Control register(07h) and the VCR Video Output
Control register(09h). When enabled, INTbecomes
active low if the voltage level changes on TV_SS or
VCR_SS. See Tables 10, 15, 17, and 20.
Fast SwitchingThe fast-switching signal was originally used to switch
between CVBS and RGB signals on a pixel-by-pixel
basis so that on-screen display (OSD) information
could be inserted. Since modern set-top box decoder
chips have integrated OSD circuitry, there is no need to
create OSD information using the older technique. Now,
the fast-switching signal is just used to switch between
CVBS and RGB signal sources.
Set the source of the fast-switching signal by writing to
bits 4 and 3 of the TV Video Output Control register
(07h). The fast-switching signal to the TV SCART con-
nector can be enabled or disabled by bit 1 of the Output
Enable register (0Dh). See Tables 10, 15, and 18.
I2C Serial InterfaceThe MAX9670/MAX9671 feature an I2C/SMBus™-com-
patible, 2-wire serial interface consisting of a serial-data
line (SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9670/
MAX9671 and the master at clock rates up to 400kHz.
Figure 6 shows the 2-wire interface timing diagram. The
master generates SCL and initiates data transfer on the
bus. A master device writes data to the MAX9670/
MAX9671 by transmitting a START (S) condition, the
proper slave address with the R/Wbit set to 0, followed
by the register address and then the data word. Each
transmit sequence is framed by a START and a STOP
(P) condition. Each word transmitted to the
MAX9670/MAX9671 is 8 bits long and is followed by an
acknowledge clock pulse. A master reads from the
MAX9670/MAX9671 by transmitting the slave address
with the R/Wbit set to 0, the register address of the reg-
ister to be read, a REPEATED START (Sr) condition, the
slave address with the R/Wbit set to 1, followed by a
series of SCL pulses. The MAX9670/MAX9671 transmit
data on SDA in sync with the master-generated SCL
pulses. The master acknowledges receipt of each byte
of data. Each read sequence is framed by a START or
MAX9670 fig04
20μs/div
INPUT
500mV/div
OUTPUT
500mV/div
Figure 4. MAX9670/MAX9671 Video Output with CVBS Signal,
Multiburst Video Test Signal Shown
MAX9670 fig05
10μs/div
INPUT
200mV/div
OUTPUT
200mV/div
Figure 5. MAX9670/MAX9671 Video Output with Chroma (C)
Signal, Multiburst Video Test Signal Shown
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART ConnectorsREPEATED START condition, an acknowledge or a not
acknowledge, and a STOP condition. SDA operates as
both an input and an open-drain output. A pullup resis-
tor, typically greater than 500Ω, is required on the SDA
bus. SCL operates as only an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there
are multiple masters on the bus, or if the master in a
single-master system has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the
MAX9670/MAX9671 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit TransferOne data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
START and STOP ConditionsSDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 7). A
START condition from the master signals the beginning
of a transmission to the MAX9670/MAX9671. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
Early STOP ConditionsThe MAX9670/MAX9671 recognize a STOP condition at
any point during data transmission except if the STOP
condition occurs in the same high pulse as a START
condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave AddressThe slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/Wbit to 1 to configure the MAX9670/MAX9671 to
read mode. Set the R/Wbit to 0 to configure the
MAX9670/MAX9671 to write mode. The slave address
is always the first byte of information sent to the
MAX9670/MAX9671 after a START or a REPEATED
START condition. The MAX9670/MAX9671 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the
MAX9670/MAX9671.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD, STA
tSU, STA
tHD, STAtSP
tBUF
tSU, STOtLOW
tSU, DAT
tHD, DAT
tHIGHtF
Figure 6. I2C Serial-Interface Timing Diagram
SCL
SDA
SSrP
Figure 7. START, STOP, and REPEATED START Conditions
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
AcknowledgeThe acknowledge bit (ACK) is a clocked 9th bit that the
MAX9670/MAX9671 use to handshake receipt of each
byte of data when in write mode (see Figure 8). The
MAX9670/MAX9671 pull down SDA during the entire
master-generated ninth clock pulse if the previous byte
is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may retry
communication. The master pulls down SDA during the
ninth clock cycle to acknowledge receipt of data when
the MAX9670/MAX9671 are in read mode. An acknowl-
edge is sent by the master after each read byte to allow
data transfer to continue. A not acknowledge is sent
when the master reads the final byte of data from the
MAX9670/MAX9671, followed by a STOP condition.
Write Data FormatA write to the MAX9670/MAX9671 consists of transmit-
ting a START condition, the slave address with the R/W
bit set to 0, one data byte to configure the internal reg-
ister address pointer, one or more data bytes, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the
MAX9670/MAX9671. Figure 10 illustrates the frame for-
mat for writing n bytes of data to the MAX9670/
MAX9671.
The slave address with the R/Wbit set to 0 indicates
that the master intends to write data to the MAX9670/
MAX9671. The MAX9670/MAX9671 acknowledge
receipt of the address byte during the master-generat-
ed ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9670/MAX9671’s internal register address
pointer. The pointer tells the MAX9670/MAX9671 where
to write the next byte of data. An acknowledge pulse is
sent by the MAX9670/MAX9671 upon receipt of the
address pointer data.SCL
START
CONDITION
SDA9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 8. Acknowledge0SLAVE ADDRESSREGISTER ADDRESSDATA BYTE
ACKNOWLEDGE FROM MAX9670/MAX9671
R/W1 BYTE
ACKNOWLEDGE FROM MAX9670/MAX9671
ACKNOWLEDGE FROM MAX9670/MAX9671B0B3B2B5B4B7B6AAP
Figure 9. Writing a Byte of Data to the MAX9670/MAX9671
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671B0B3B2B5B4B7B6A0
ACKNOWLEDGE FROM MAX9670/MAX9671
R/WA
1 BYTE
ACKNOWLEDGE FROM
MAX9670/MAX9671B0B3B2B5B4B7B6ASLAVE ADDRESSREGISTER ADDRESSDATA BYTE 1 DATA BYTE n
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART ConnectorsThe third byte sent to the MAX9670/MAX9671 contains
the data that is written to the chosen register. An
acknowledge pulse from the MAX9670/MAX9671 sig-
nals receipt of the data byte. The address pointer
autoincrements to the next register address after each
received data byte. This autoincrement feature allows a
master to write to sequential register address locations
within one continuous frame. The master signals the
end of transmission by issuing a STOP condition.
Read Data FormatThe master presets the address pointer by first sending
the MAX9670/MAX9671’s slave address with the R/W
bit set to 0 followed by the register address after a
START condition. The MAX9670/MAX9671 acknowl-
edges receipt of its slave address and the register
address by pulling SDA low during the ninth SCL clock
pulse. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/Wbit set to 1.
The MAX9670/MAX9671 transmits the contents of the
specified register. Transmitted data is valid on the ris-
ing edge of the master-generated serial clock (SCL).
The address pointer autoincrements after each read
data byte. This autoincrement feature allows all regis-
ters to be read sequentially within one continuous
frame. A STOP condition can be issued after any num-
ber of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte
to be read is from the register address location set by
the previous transaction and not 00h and subsequent
reads autoincrement the address pointer until the next
addresses higher than 10h results in repeated reads
from a dummy register containing FFh data. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figures 11
and 12 illustrate the frame format for reading data from
the MAX9670/MAX9671.
Interrupt OutputWhen interrupt is enabled in modes 1 and 2, INT, which
is an open-drain output, pulls low under the following
conditions: slow-switch signals change value, CVBS
input signals are detected or disappear, and CVBS out-
put loads are added or removed.
When interrupt is enabled in mode 3, INTpulls low only
when the slow-switch signal changes value.
Enable INTby writing a 1 into bit 4 of register 01h. See
Table 13.
The interrupt can be cleared by reading register 0Eh
and 0Fh.
Applications Information
Audio InputsThe maximum full-scale audio signal that can be
applied to the audio inputs is 0.5VRMSbiased at
ground. The recommended application circuit to atten-
uate and bias an incoming audio signal is shown in
ACKNOWLEDGE FROM
MAX9670/MAX9671
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM
MAX9670/MAX9671
NOT ACKNOWLEDGE FROM MASTERAPA0
ACKNOWLEDGE FROM
MAX9670/MAX9671
R/W
R/WREPEATED START1SLAVE ADDRESSREGISTER ADDRESSSLAVE ADDRESS DATA BYTE
Figure 11. Reading One Indexed Byte of Data from the MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM
MAX9670/MAX9671AAP0
ACKNOWLEDGE FROM
MAX9670/MAX9671
R/W
R/WREPEATED START1SLAVE ADDRESSREGISTER ADDRESSSLAVE ADDRESS DATA BYTE
NOT ACKNOWLEDGE FROM MASTER
Figure 12. Reading n Bytes of Indexed Data from the MAX9670/MAX9671
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART ConnectorsThe audio path has a gain of 4V/V so that the full scale
of the audio output signal is 2VRMS. If less than 2VRMS,
full scale is desired at the audio outputs, and the full
scale of the audio input signal should be proportionate-
ly decreased below 0.5VRMS.
Operating ModesThe MAX9670/MAX9671 has four operating modes,
which can be set by writing to bits 6 and 7 of register
10h. See Table 19.
ShutdownAll circuitry is shutdown in the MAX9670/MAX9671
except for the I2C interface, which is designed with sta-
tic CMOS logic. Except for register 10h, which sets the
operating mode, the values in all of the other I2C regis-
ters are preserved while entering, during, and leaving
shutdown mode.
Standby ModeIn standby mode, the MAX9670/MAX9671 monitor the
slow-switch signals and decide whether to loop through
the audio/video signals. If the VCR slow switch input
has activity (6V or 12V at the input), the audio/video sig-
nals are looped through from the VCR SCART to the TV
SCART. If the TV slow-switch input has activity, the
audio/video signals are looped through from the TV
SCART to the VCR SCART. If neither the VCR slow-
switch input nor the TV slow switch input show activity,
i.e., both inputs are at ground, no signals are looped
through. If both the VCR slow-switch input and the TV
considers this condition to be illegal and does not loop
through any signals.
A finite state machine (Figure 14) controls the operation
of the MAX9670/MAX9671. State 0 is always the initial
state when the MAX9670/MAX9671 enter standby
mode. Table 4 shows the values of the I2C registers in
state 0. The state machine sets the other I2C registers
to the correct values to loop through the audio/video
signals in states 1 and 2 (see Tables 5 and 6). When
the MAX9670/MAX9671 leaves standby mode, the val-
ues in all of the I2C registers except register 10h are
preserved so that the operation is not disturbed. For
example, if in standby mode, the MAX9670 is looping
through the audio/video signals from VCR SCART to TV
SCART, and if the microcontroller changes the operat-
ing mode from standby mode to full-power mode, the
audio/video signals continue to be looped through dur-
ing and after the mode change. The user does not
experience any disruption in audio or video service.
The microcontroller can be turned off in standby mode
because the MAX9670/MAX9671 operate autonomous-
ly. Upon power-up, the default operating mode is
standby mode.
Full-Power Mode with Video Input Detection
and Video Load DetectionIn this mode, the MAX9670/MAX9671 are fully on. If
interrupt is enabled, INTgoes active low whenever the
slow-switch signal changes; a CVBS signal appears or
disappears; or a CVBS load appears or disappears.
The microcontroller can decide whether to change the
routing configuration or operating mode of the
MAX9670/MAX9671.
Full-Power Mode Without Video Input Detection
and Video Load DetectionThis mode is similar to the above mode except that
video input detection and video load detection are not
active. If interrupt is enabled, INTgoes active low only
when the slow-switch signal changes.
Power ConsumptionThe quiescent power consumption and average power
consumption of the MAX9670/MAX9671 are very low
because of 3.3V operation and low-power circuit design.
Quiescent power consumption is defined when the
MAX9670/MAX9671 are operating without loads and
without any audio or video signals. Table 7 shows the
quiescent power consumption in all 4 operating modes.
Average power consumption is defined when the MAX9670/
MAX9671 drives typical signals into typical loads. Table 8
shows the average power consumption in full-power
MAX96701μF6.65kΩ
*R1 VALUES
DAC = CS4334/5/8/9: R1 = 4.53kΩ, 1%
DAC = PCM1742: R1 = 5.57kΩ, 1%
R1*
ENC_INL
1μF6.65kΩ
R1*
ENC_INR
STEREO
AUDIO
DACS
Figure 13. Application circuit to connect audio source to audio
inputs. The 1µF capacitor connected to the ground-referenced
resistors biases the audio signal at ground. The resistors atten-
uate the audio signal.
