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MAX9669ETI+-MAX9669ETI+T
10-Bit Programmable Gamma Reference System with MTP for TFT LCDs
General DescriptionThe MAX9669 outputs 16 voltage references for gamma
correction in TFT LCDs and one voltage reference for
VCOM. Each gamma reference voltage has its own 10-
bit digital-to-analog converter (DAC) and buffer to
ensure a stable voltage. The VCOM reference voltage
has its own 10-bit DAC and an amplifier to ensure a sta-
ble voltage when critical levels and patterns are dis-
played. The MAX9669 features integrated multiple-time
programmable (MTP) memory to store gamma and
VCOM values on the chip, eliminating the need for exter-
nal EEPROM. The MAX9669 supports up to 100 write
operations to the on-chip nonvolatile memory.
The gamma outputs can drive 200mA peak transient
current and settle within 1µs. The VCOM output can
provide 600mA peak transient current and also settles
within 1µs. The analog supply voltage range extends
from 9V to 20V, and the digital supply voltage range
extends from 2.7V to 3.6V.
Gamma values and the VCOM value are programmed
into registers through the I2C interface.
ApplicationsTFT LCDs
Features16-Channel Gamma Correction, 10-Bit ResolutionVCOM DriverIntegrated MTP MemoryProgrammable VCOM Limits200mA Peak Current on Gamma Channels600mA Peak Current on VCOM Channel1µs Settling Time
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs 19-4326; Rev 4; 8/11
Ordering Information
PARTTEMP RANGEPIN-PACKAGEMAX9669ETI+-40°C to +85°C28 TQFN-EP*
MAX9669ETI/V+-40°C to +85°C28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.
DAC
REGISTERS
I2C
REGISTERS
I2C
INTERFACE
MTP
MEMORY
10-BIT
DACGMA1
AVDD
10-BIT
DACGMA210
10-BIT
DACGMA310
10-BIT
DACGMA410
10-BIT
DACGMA510
10-BIT
DACGMA610
10-BIT
DACGMA710
10-BIT
DACGMA810
10-BIT
DACGMA910
10-BIT
DACGMA1010
10-BIT
DACGMA1110
10-BIT
DACGMA1210
10-BIT
DACGMA1310
10-BIT
DACGMA1410
10-BIT
DACGMA1510
10-BIT
DACGMA16
DVDD
SDA
SCL
DGND
10-BIT
DACAVDD_AMP
AGND_AMP
VCOM_FB
VCOM
MAX9669
Functional Diagram
THIN QFN
(5mm ×× 5mm)
TOP VIEW
SCL
DVDD
AGND_AMP
VCOM
GMA16
AVDDGMA7GMA6AGNDGMA5GMA4
GMA12672119171615
GMA13
GMA14
GMA1
AGND
AVDD
AVDD_AMP
SDA
GMA88GMA15VCOM_FB
GMA1113GMA2GMA1014GMA3GMA9
EP*
MAX9669
Pin Configuration
MAX9669
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD= 18V, VAVDD_AMP= 18V, VDVDD= 3.3V, VAGND= VAGND_AMP= VDGND= 0, VCOM = VCOM_FB, no load, TA= TMINto
TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltages
AVDD to AGND..................................................-0.3V to +22V
AVDD_AMP to AGND_AMP................................-0.3V to +22V
AVDD to AVDD_AMP.........................................-0.3V to +0.3V
DVDD to DGND....................................................-0.3V to +4V
AGND_AMP, DGND to AGND...........................-0.1V to +0.1V
Outputs
GMA1–GMA16....................................-0.3V to (AVDD + 0.3V)
VCOM........................................-0.3V to (AVDD_AMP + 0.3V)
Inputs
SDA, SCL..............................................................-0.3V to +6V
VCOM_FB..................................-0.3V to (AVDD_AMP + 0.3V)
SDA, SCL..........................................................................±20mA
GMA1–GMA16................................................................±200mA
VCOM.............................................................................±600mA
Continuous Power Dissipation (TA= +70°C)
28-Pin TQFN-EP (derate 28.6mW/°C
above +70°C) .........................................................2285.7mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLIESAnalog Supply Voltage RangeVAVDD,
VAVDD_AMPGuaranteed by total output error920V
Analog Supply Voltage Range for
Programming MTPVAVDD_MTP1520V
Digital Supply Voltage RangeVDVDD2.73.6V
Analog Quiescent CurrentIAVDD2035mA
VCOM Quiescent CurrentIAVDD_AMP2.75.6mA
During a register mode load event400Digital Quiescent CurrentIDVDDNo SCL or SDA transitions260600µA
Thermal Shutdown+160°C
Thermal-Shutdown Hysteresis15°C
Undervoltage Lockout ThresholdUVLODVDD undervoltage lockout voltage
threshold2.32.6V
VCOM OUTPUT (VCOM)ResolutionRES10Bits
Integral Nonlinearity ErrorINL0.1251LSB
Differential Nonlinearity ErrorDNL0.1251LSB
Total Output ErrorVERRCode = 512, AVDD_AMP = 9V and 20V,
TA = +25°C-40+40mV
Total Output-Error DriftΔVERRCode = 51215µV/°C
Output Voltage LowVOUTTA = +25°C, sinking 100mA0.40.85V
Output Voltage HighVOUTTA = +25°C, sourcing 100mAVAVDD_AMP
- 1.1
VAVDD_AMP
- 0.6V
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSContinuous Output CurrentIOCode = 512 (Note 2)80mA
Short-Circuit Current9V ≤ VAVDD_AMP ≤ 20V600mA
Slew RateSRSwing 4VP-P at VCOM, 10% to 90%,
RL = 10kΩ, CL = 50pF (Note 3)100V/µs
Program to Output DelaytD
From SCL rising edge for ACK bit after
programming VCOM to 50% voltage
change at output
0.8µs
BandwidthBWRS = 10kΩ, CL = 50pF (Note 3)60MHz
NoiseeNRMS noise voltage (10MHz BW)375µV
DAC OUTPUTS (GMA1–GMA16)ResolutionRESGuaranteed monotonic10Bits
Integral Nonlinearity ErrorINL0.1251LSB
Differential Nonlinearity ErrorDNL0.1251LSB
Total Output ErrorVERRCode = 512, AVDD = 9V and 20V,
TA = +25°C-40+40mV
Output Voltage LowVOUTTA = +25°C, sinking 10mA0.150.28V
Output Voltage HighVOUTTA = +25°C, sourcing 10mAVAVDD
- 0.38
VAVDD
- 0.25V
Load RegulationLR-12mA to +12mA0.50mV/mA
Short-Circuit CurrentISCOutputs to AVDD or AGND200mA
Output ImpedanceZOOutput resistance when output is disabled84kΩ
Slew RateSRSwing 5VP-P at input, 10% to 90%
measurement on output22V/µs
Program to Output DelaytD
From SCL rising edge for ACK bit after
programming gamma to 50% voltage
change at output
0.8µs
NoiseenRMS noise voltage at any output (10MHz
BW)375µV
Channel-to-Channel IsolationCXTLKf = 5MHz, all channels to all channels80dB
LOGIC INPUTS (SDA, SCL)Input High VoltageVIH0.7 x
VDVDDV
Input Low VoltageVIL0.3 x
VDVDDV
Input Leakage CurrentIIH, IILVIN = 0 or DVDD-1+0.01+1µA
Input Capacitance5pF
Power-Down Input CurrentIINVDVDD = 0, VIN = 2V-10+10µA
SDA Output Low VoltageVOLISINK = 6mA0.4V
I2C TIMING CHARACTERISTICS (Figure 1)
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= 18V, VAVDD_AMP= 18V, VDVDD= 3.3V, VAGND= VAGND_AMP= VDGND= 0, VCOM = VCOM_FB, no load, TA= TMINto
TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
MAX9669
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= 18V, VAVDD_AMP= 18V, VDVDD= 3.3V, VAGND= VAGND_AMP= VDGND= 0, VCOM = VCOM_FB, no load, TA= TMINto
TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBus Free Time Between STOP
and START ConditionstBUF1.3µs
Hold Time (Repeated) START
ConditiontHD,STA0.6µs
SCL Pulse-Width LowtLOW1.3µs
SCL Pulse-Width HightHIGH0.6µs
Setup Time for a Repeated
START ConditiontSU,STA0.6µs
Data Hold TimetHD,DAT0900ns
Data Setup TimetSU,DAT100ns
SDA and SCL Receiving Rise
TimetR(Note 4)20 +
0.1CB300ns
SDA and SCL Receiving Fall
TimetF(Note 4)20 +
0.1CB300ns
SDA Transmitting Fall
TimetF,TX(Note 4)20 +
0.1CB250ns
Setup Time for STOP ConditiontSU,STO0.6µs
Bus CapacitanceCB400pF
Pulse Width of Suppressed SpiketSP050ns
Note 1:All devices are 100% production tested at TA= +25°C. All temperature limits are guaranteed by design.
Note 2:Thermal pad attached to multilayered board. Exceeding this limit may cause the thermal shutdown to trip.
Note 3:Measured with the VCOM amplifier configured as an inverting unity-gain amplifier (RS= RF= 1kΩ).
Note 4:CBis in pF.
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
OUTPUT OFFSET-VOLTAGE
DISTRIBUTIONMAX9669 toc01
OUTPUT OFFSET (mV)
N (%)
GAMMA LOAD REGULATION
MAX9669 toc02
LOAD CURRENT (mA)
LOAD REGULATION (mV)
VCOM LOAD REGULATION
MAX9669 toc03
LOAD CURRENT (mA)
LOAD REGULATION (mV)
DNL
GAMMA
MAX9669 toc04
CODE (UNITS)
DNL (LSB)
DNL
VCOM
MAX9669 toc05
DNL (LSB)
Typical Operating Characteristics(VAVDD= VAVDD_AMP= 18V, VDVDD= 3.3V, VAGND= VAGND_AMP= VDGND= 0, no load, unless otherwise noted. Typical values are
at TA= +25°C.)
MAX9669
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
Typical Operating Characteristics (continued)(VAVDD= VAVDD_AMP= 18V, VDVDD= 3.3V, VAGND= VAGND_AMP= VDGND= 0, no load, unless otherwise noted. Typical values are
at TA= +25°C.)
VOUT
250mV/div
IOUT
250mA/div
VCOM PULSE RESPONSEMAX9669 toc08
TIME (2μs/div)
RISO = 10Ω
CLOAD = 68nF
-2.5V TO +2.5V
CLOAD
RISOVCOM
DAC
VOUT
1V/div
IOUT
50mA/div
GAMMA PULSE RESPONSEMAX9669 toc09
TIME (2μs/div)
RISO = 10Ω
CLOAD = 10nF
-2.5V TO +2.5V
CLOAD
RISOGAMMA
DAC
INL
VCOM
MAX9669 toc07
CODE (UNITS)
INL (LSB)
INL
GAMMA
MAX9669 toc06
CODE (UNITS)
INL (LSB)
Detailed DescriptionThe MAX9669 features 17 total programmable refer-
ence voltage channels. Each channel has a 10-bit DAC
to create the reference voltage. One channel has an
amplifier that follows the DAC while all other channels
have a buffer after the DAC. The MAX9669 features
integrated MTP memory to store gamma and VCOM
values on the chip, eliminating the need for external
EEPROM. The MAX9669 supports up to 100 write oper-
ations to the on-chip nonvolatile memory.
The MAX9669 can provide the gamma, VCOM, and
possibly level-shifter reference voltages for an LCD
panel, which can potentially replace a discrete digital
variable resistor (DVR), VCOM amplifier, gamma
buffers, high-voltage linear regulator, and resistor
strings. The high-voltage linear regulator can be elimi-
nated because the DAC contains a lowpass filter that
reduces horizontal line frequency noise by 50dB. Power
sequencing is well controlled since a single chip gener-
ates all the various reference voltages needed for the
LCD panel.
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
Pin Description
PINNAMEFUNCTIONGMA16Gamma DAC Analog Output 16SCLI2C-Compatible Serial-Clock InputSDAI2C-Compatible Serial-Data Input/Output
4A0I2C-Compatible Device Address Bit 0DVDDDigital Power Supply. Bypass DVDD with a 0.1µF capacitor to EP.AGND_AMPGround for VCOM AmplifierVCOMVCOM OutputVCOM_FBFeedback for VCOM AmplifierAVDD_AMPPower Supply for VCOM Amplifier. Bypass AVDD_AMP with a 0.1µF capacitor to AGND_AMP.
10, 20AVDDAnalog Power Supply. Bypass AVDD with a 0.1µF capacitor to AGND.
11, 21AGNDAnalog GroundGMA1Gamma DAC Analog Output 1GMA2Gamma DAC Analog Output 2GMA3Gamma DAC Analog Output 3GMA4Gamma DAC Analog Output 4GMA5Gamma DAC Analog Output 5GMA6Gamma DAC Analog Output 6GMA7Gamma DAC Analog Output 7GMA8Gamma DAC Analog Output 8GMA9Gamma DAC Analog Output 9GMA10Gamma DAC Analog Output 10GMA11Gamma DAC Analog Output 11GMA12Gamma DAC Analog Output 12GMA13Gamma DAC Analog Output 13GMA14Gamma DAC Analog Output 14GMA15Gamma DAC Analog Output 15DGNDDigital Ground
—EPExposed Pad. EP is internally connected to DGND. EP must be connected to the system’s digital
ground.
MAX9669Each part has an I2C interface for programming both
the MTP memory and the I2C registers.
With the MTP memory and the I2C interface, the
MAX9669 enables automatic gamma and automatic
flicker calibration on a panel-by-panel basis on the pro-
duction line. Contact your Maxim representative for
more details.
10-Bit DACsThe voltage at AVDD sets the full-scale output of the
DACs. Determine the output voltage using the following
equations:
VOUT= (VAVDDx CODE)/2N
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX9669, N = 10 and CODE ranges from 0 to 1023.
The DAC can never output AVDD because the maxi-
mum value of CODE is always 1 least significant bit
(LSB) less than the reference. For example, if AVDD =
16V and CODE = 1023, then the output voltage is:
VOUT= (16V x 1023)/210
= 15.98438V
Gamma BuffersThe gamma buffers are guaranteed to source or sink
10mA of DC current within 200mV of the supplies.
The source drivers can kick back a great deal of cur-
rent to the buffer outputs during a horizontal line
change or a polarity switch. The DAC output buffers
can source/sink 200mA of peak current to reduce the
recovery time of the output voltages when critical levels
and patterns are displayed.
VCOM AmplifierThe operational amplifier attached to the VCOM DAC
holds the VCOM voltage stable while providing the abil-
ity to source and sink 600mA into the backplane of a
TFT LCD panel. The operational amplifier can directly
drive the capacitive load of the TFT LCD backplane
without the need for a series resistor in most cases. The
VCOM amplifier has current limiting on its output to pro-
tect its bond wires.
If the application requires more than 600mA, buffer the
output of the VCOM amplifier with a MAX9650, a VCOM
power amplifier. The MAX9650 can source or sink 1A of
current.
Thermal ShutdownThe MAX9669 features thermal-shutdown protection
with temperature hysteresis. When the die temperature
reaches +165°C, all of the gamma outputs are dis-
abled. When the die cools down by 15°C, the outputs
are enabled again.
I2C Serial InterfaceThe MAX9669 features an I2C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facili-
tate communication between the MAX9669 and the mas-
ter at clock rates up to 400kHz. Figure 1 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. A master
device writes data to the MAX9669 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each byte is serially trans-
mitted to the MAX9669 as 8 bits and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9669 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX9669
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDsSCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD,STA
tSU,STAtHD,STAtSP
tBUF
tSU,STOtLOW
tSU,DAT
tHD,DAT
tHIGHtF
Figure 1. I2C Serial-Interface Timing Diagram
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω, is required on the SDA bus. SCL operates as
only an input. A pullup resistor, typically greater than
500Ω, is required on SCL if there are multiple masters on
the bus, or if the master in a single-master system has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX9669 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit TransferOne data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the2C bus is not busy.
START and STOP ConditionsSDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 2). A START
condition from the master signals the beginning of a
transmission to the MAX9669. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP ConditionsThe MAX9669 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave AddressThe slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/Wbit to 1 to configure the MAX9669 to read mode.
Set the R/Wbit to 0 to configure the MAX9669 to write
mode. The address is the first byte of information sent
to the MAX9669 after the START condition. The
MAX9669 slave address is configured with A0. Table 1
shows the possible addresses for the MAX9669.
AcknowledgeThe acknowledge bit (ACK) is a clocked 9th bit that the
MAX9669 uses to handshake receipt of each byte of
data when in write mode (see Figure 3). The MAX9669
pulls down SDA during the entire master-generated
ninth clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication. The
master pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9669 is in
read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not
acknowledge is sent when the master reads the final
byte of data from the MAX9669, followed by a STOP
condition.
Write Data FormatA write to the MAX9669 consists of transmitting a
START condition, the slave address with the R/Wbit set
to 0, one data byte of data to configure the internal reg-
ister address pointer, one word (two bytes) data or
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDsSCL
SDA
SSrP
Figure 2. START, STOP, and REPEATED START Conditions
READ ADDRESSWRITE ADDRESSDGNDE9hE8h
DVDDEBhEAh
Table 1. Slave AddressSCL
START
CONDITION
SDA9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 3. Acknowledge
MAX9669more, and a STOP condition. Figure 4 illustrates the
proper frame format for writing one word of data to the
MAX9669. Figure 5 illustrates the frame format for writ-
ing n-bytes of data to the MAX9669.
The slave address with the R/Wbit set to 0 indicates
that the master intends to write data to the MAX9669.
The MAX9669 acknowledges receipt of the address
byte during the master-generated ninth SCL pulse.
The second byte transmitted from the master configures
the MAX9669’s internal register address pointer. The
MAX9669’s internal address pointer consists of the 6
LSBs of the second byte. The 2 MSBs of the second
byte (M1 and M0) are set to 00b when writing to the
internal registers. See the Memorysection for more
details. The pointer tells the MAX9669 where to write the
next byte of data. An acknowledge pulse is sent by the
MAX9669 upon receipt of each data byte when writing
to the DAC. When writing to the MTP, a not acknowl-
edge is sent from the MAX9669 after the master writes
the final byte of data, followed by a STOP condition.
The third and fourth bytes sent to the MAX9669 contain
type of register it writes to, volatile (DAC) or nonvolatile
memory (MTP). See the Registers section for more
details. An acknowledge pulse from the MAX9669 sig-
nals receipt of each data byte. The address pointer
autoincrements to the next register address after
receiving every other data byte. This autoincrement fea-
ture allows a master to write to sequential register
address locations within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition.
If data is written into register address 0x1E, the address
pointer autoincrements to 0xFF and stays at 0xFF until
the master writes a new value into the register address
pointer.
Read Data FormatThe master presets the address pointer by first sending
the MAX9669’s slave address with the R/Wbit set to 0
followed by the register address with M1 and M0 set to
00 after a START condition. The MAX9669 acknowl-
edges receipt of its slave address and the register
address by pulling SDA low during the ninth SCL clock
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs1 WORD
ACKNOWLEDGE FROM MAX9669APA/A0
ACKNOWLEDGE FROM MAX9669
R/WSLAVE ADDRESSREGISTER ADDRESSDATA BYTE 2
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER00DATA BYTE 1
ACKNOWLEDGE FROM MAX9669
ACKNOWLEDGE FROM MAX9669W0D9D8XXXXD7D6D1D0D2D4D3D5M1
Figure 4. Writing a Word of Data to the MAX9669
1 WORD
ACKNOWLEDGE FROM MAX9669AA0
ACKNOWLEDGE FROM MAX9669
R/WSLAVE ADDRESSREGISTER ADDRESSDATA BYTE 2
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER00DATA BYTE 1
ACKNOWLEDGE FROM MAX9669
ACKNOWLEDGE FROM MAX9669W0D9D8XXXXD7D6D1D0D2D4D3D5
1 WORD
ACKNOWLEDGE FROM MAX9669PDATA BYTE nDATA BYTE n-1
ACKNOWLEDGE FROM MAX9669W0D9D8XXXXD7D6D1D0D2D4D3D5M1
A/A
Figure 5. Writing n Bytes of Data to the MAX9669
lowed by the slave address with the R/Wbit set to 1.
The MAX9669 transmits the contents of the specified
register. Transmitted data is valid on the rising edge of
the master-generated serial clock (SCL). The address
pointer autoincrements after every other read data byte.
This autoincrement feature allows all registers to be
read sequentially within one continuous frame. A STOP
condition can be issued after any number of read data
bytes. If a STOP condition is issued followed by another
read operation, the first data byte to be read is from the
tion and not 0x00. Subsequent reads autoincrement the
address pointer until the next STOP condition.
Attempting to read from register addresses higher than
0x1E results in repeated reads from a dummy register
containing all one data. The master acknowledges
receipt of each read byte during the acknowledge
clock pulse. The master must acknowledge all correctly
received bytes except the last byte. The final byte must
be followed by a not acknowledge from the master and
then a STOP condition. Figures 6 and 7 illustrate the
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
MTP FACTORY
INITIALIZATION VALUEREAD/WRITE0x00GMA1Gamma 10x200Read and write
0x01GMA2Gamma 20x200Read and write
0x02GMA3Gamma 30x200Read and write
0x03GMA4Gamma 40x200Read and write
0x04GMA5Gamma 50x200Read and write
0x05GMA6Gamma 60x200Read and write
0x06GMA7Gamma 70x200Read and write
0x07GMA8Gamma 80x200Read and write
0x08GMA9Gamma 90x200Read and write
0x09GMA10Gamma 100x200Read and write
0x0AGMA11Gamma 110x200Read and write
0x0BGMA12Gamma 120x200Read and write
0x0CGMA13Gamma 130x200Read and write
0x0DGMA14Gamma 140x200Read and write
0x0EGMA15Gamma 150x200Read and write
0x0FGMA16Gamma 160x200Read and write
0x10Reserved———
0x11Reserved———
0x12VCOMCommon voltage0x200Read and write
0x13Reserved———
0x14Reserved———
0x15Reserved———
0x16Reserved———
0x17Reserved———
0x18VCOMMINMinimum VCOM value0x000Read and write
0x19VCOMMAXMaximum VCOM value0x3FFRead and write
0x1DReserved,
DO NOT WRITE———
0x1EReserved,
DO NOT WRITE———
Table 2. Register Map
MAX9669
Registers
Register MapThe MAX9669 has a bank of nonvolatile MTP memory
and two banks of volatile memory comprised of I2C reg-
isters and DAC registers. Each memory location
whether in nonvolatile or volatile memory holds a 10-bit
word. Two bytes must be read or written through the
I2C interface for every 10-bit word.
Table 2 shows the register map. The same register
address and register name exists in the MTP memory
bank, I2C register bank, and the DAC register bank.
The write control bits determine which memory location
the data is stored into.
Register DescriptionOnly the 10 LSBs are written to the registers (see Table
3). During a write operation, the write control bits (the 2
MSBs) are stripped from the incoming data stream and
are used to determine whether the MTP or DAC regis-
ters are updated (see Table 4).
10-Bit Programmable Gamma Reference
System with MTP for TFT LCDs
REGREG
ADDRB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0GMA10x00W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA20x01W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA30x02W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA40x03W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA50x04W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA60x05W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA70x06W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA80x07W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA90x08W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA100x09W1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA110x0AW1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA120x0BW1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA130x0CW1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA140x0DW1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA150x0EW1W0XXXXb9b8b7b6b5b4b3b2b1b0
GMA160x0FW1W0XXXXb9B8b7b6b5b4b3b2b1b0
Reserved0x10————————————————
Reserved0x11————————————————
VCOM0x12W1W0XXXXb9b8b7b6b5b4b3b2b1b0
Reserved0x13————————————————
Reserved0x14————————————————
Reserved0x15————————————————
Reserved0x16————————————————
Reserved0x17————————————————
VCOMMIN0x18W1W0XXXXb9b8b7b6b5b4b3b2b1b0
VCOMMAX0x19W1W0XXXXb9b8b7b6b5b4b3b2b1b0
Reserved
DO NOT
WRITE
0x1D————————————————
Reserved
DO NOT
WRITE
0x1E————————————————
Table 3. Register Description
