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MAX9485ETP+
Programmable Audio Clock Generator
General DescriptionThe MAX9485 programmable multiple-output clock
generator provides a cost-efficient solution for MPEG-2
audio systems such as DVD players, DVD drives for
multimedia PCs, digital HDTV systems, home entertain-
ment centers, and set-top boxes.
The MAX9485 accepts an input reference frequency of
27MHz from a crystal or system reference clock. The
device provides two buffered clock outputs of 256, 384,
or 768 times the chosen sampling frequency (fS) select-
ed through an I2C interface or hardwired inputs.
Sampling frequencies of 12kHz, 32kHz, 44.1kHz,
48kHz, 64kHz, 88.2kHz, or 96kHz are available. The
MAX9485 also offers a buffered 27MHz output and an
integrated voltage-controlled oscillator (VCXO) that is
tuned by a DC voltage generated from the MPEG
processor. The use of VCXO allows the audio system
clock to lock with the overall system clock.
The MAX9485 features the lowest jitter in its class, guar-
anteeing excellent dynamic performance with audio
ADCs and DACs in an MPEG-2 audio system. The
device operates with a 3.3V supply and is specified over
the -40°C to +85°C extended temperature range. The
MAX9485 is offered in 6.5mm x 4.4mm 20-pin TSSOP
and 4mm x 4mm 20-pin thin QFN packages.
ApplicationsDigital TVsDVD Players
Set-Top BoxesHDTVs
Home Entertainment
Centers
Features27MHz Crystal with ±30ppm Frequency ReferenceTwo Buffered Output Ports with Multiple Audio
Clocks: 256, 384, or 768 Times fSSupports Standard and Double Sampling Rates
(12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz,
and 96kHz)I2C Interface or Hardwired Output Clock SelectionSeparate Output Clock EnableLow Jitter Typical 21ps (RMS at 73.728MHz)No External Components for PLLIntegrated VCXO with ±200ppm Tuning RangeSmall Footprint, Thin QFN Package, 4mm x 4mm
MAX9485
Programmable Audio Clock GeneratorSAO2
SAO1
MCLK
VDDX1
TUN
GND_P
VDD_P
TOP VIEW
CLK_OUT2
GND
CLK_OUT1
MODESDA/FS1
SCL/FS0
VDD
RST
GNDGND
FS2
MAX9485
TSSOPMAX9485
EXPOSED PAD
(GROUND)1918
CLK_OUT1
GND
CLK_OUT2
VDD
VDD
TUNMODE5SCL/FS0
GND_PV
DD_P
SAO2
SAO1
SDA/FS1
FS2
GNDGND89
MCLK
RST
THIN QFN
Pin Configurations
Ordering Information19-3315; Rev 0; 7/04
*EP = Exposed pad.
EVALUATION KITAVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX9485ETP-40°C to +85°C20 Thin QFN-EP*
MAX9485EUP-40°C to +85°C20 TSSOP
MAX9485
Programmable Audio Clock Generator
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VDD= VDD_P = 3.0V to 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD= VDD_P= 3.3V.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, VDD_P to GND...............................................-0.3V to +4.0V
GND_P to GND...................................................................±0.3V
All Inputs and Outputs to GND...................-0.3V to (VDD+ 0.3V)
Short-Circuit Duration of Outputs to GND..................Continuous
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 11mW/°C above +70°C).........879mW
20-Lead Thin QFN (derate 16.9mW/°C
above +70°C).............................................................1349mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)...........> ±2kV
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVCMOS/LVTTL INPUTS (MODE, RST, X1) (Note 2)High Level-Input VoltageVIH12.0VDDV
Low Level-Input VoltageVIL10.00.8V
Input CurrentIIL1Input voltage = 0 or VDD-20+20µA
THREE-LEVEL INPUTS (FS0, FS1, FS2, SAO1, SAO2)High Level-Input VoltageVIH22.5VDDV
Low Level-Input VoltageVIL20.00.8V
Input Open LevelVIO2Input open1.32.0V
Input CurrentIINInput voltage = 0 or VDD-10+10µA
LVCMOS/LVTTL OUTPUTS (CLK_OUT1, CLK_OUT2, MCLK)Output High LevelVOH1IOH1 = -4mAVDD - 0.6V
Output Low LevelVOL1IOL1 = 4mA0.4V
2C INTERFACE INPUT AND OUTPUT (SCL, SDA)Input High LevelVIH30.7 x VDDVDDV
Input Low LevelVIL300.3 x VDDV
Input CurrentIINInput voltage = 0 or VDD-1+1µA
Low-Level OutputVOL3IOL3 = 4mA0.4V
Input CapacitanceCIN8.4pF
POWER SUPPLY (VDD, VDD_P)Power-Supply RangesVDD,
VDD_P3.03.33.6V
Power-Supply CurrentIDD+IDD_PCLK_OUT1, CLK_OUT2 at 73.728MHz,
no load, VTUN = 3.0V12mA
MAX9485
Programmable Audio Clock Generator
AC ELECTRICAL CHARACTERISTICS(VDD= VDD_P = 3.0V to 3.6V, TA= -40°C to +85°C, output frequency is 73.728MHz, CL = 20pF, unless otherwise noted. Typical values
are at TA = +25°C, VDD= VDD_P= 3.3V.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VCXO (MCLK)Crystal FrequencyfXTLNominal frequency27MHz
Crystal Accuracy±30ppm
Tuning Voltage RangeVTUN03.0VV
VCXO Tuning RangeVTUN = 0 to 3.0V-200+200ppm
TUN Input ImpedanceRTUN94kΩ
Output Clock FrequencyfMCLKVTUN = 1.75V27MHz
Output Clock AccuracyVTUN = 1.75V (Note 4)±50ppm
Output Duty Cycle455565%
Output JittertMJRMS28ps
Output Rise TimetMRFigure 82ns
Output Fall TimetMFFigure 82ns
Tuning Response TimetTUNFigure 910µs
Power-On Settling TimeTPO1Figure 95ms
CLOCK OUTPUTS (CLK_OUT1, CLK_OUT2)256 x fS8.19224.576
384 x fS12.28836.864Frequency Range (Note 5)fout
768 x fS24.57673.728
MHz
Clock Rise TimetR1Figure 82ns
Clock Fall TimetF1Figure 82ns
Duty Cycle455055%
CLK_OUT1, 2 at 73.728MHz
(Note 6)21Output Clock Period JittertRJRMS
CLK_OUT1, 2 at 36.864MHz37
Frequency Settling TimetFSTFigure 110ms
Power-On TimeTPO2Figure 915ms
MAX9485
Programmable Audio Clock Generator
Note1:All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design and characterization.
Note2:When X1 is used as an external reference.
Note3:Guaranteed by design and characterization; limits are set at ±6 sigma.
Note4:Includes crystal accuracy.
Note5:FXTL= 27MHz. Nominal frequency.
Note6:See frequency selection paragraph in the Applications Informationsection.
Note7:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note8:Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 VDDand 0.7 VDD.
Note9:Bus sink current is less than 6mA. Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 VDDand
0.7 VDD.
Note10:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
2C TIMING CHARACTERISTICS(VDD= VDD_P = 3.0V to 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD= VDD_P= 3.3V;
Figure7.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSerial ClockfSCL400kHz
Bus Free Time Between a STOP and
a START ConditiontBUF1.3µs
Hold Time (Repeated) START
ConditiontHD, STA0.6µs
Repeated START Condition Setup
TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD,DAT(Note 7)0.050.9µs
Data Setup TimetSU,DAT100ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.6µs
Ri se Ti m e of S D A and S C L, Recei vi ng tR(Notes 3, 8)20 + 0.1Cb300ns
Fall Time of SDA and SCL, ReceivingtF(Notes 3, 8)20 + 0.1Cb300ns
Fall Time of SDA, TransmittingtF(Notes 8, 9)20 + 0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Notes 3, 10)050ns
Capacitive Load for Each Bus LineCb400pF
MAX9485
Programmable Audio Clock Generator
SUPPLY CURRENT
vs. LOAD CAPACITANCEMAX9485 toc01
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)8070605040302010
VTUN = 1.5V
fCLK_OUT = 73.728MHz
SUPPLY CURRENT vs. VTUNMAX9485 toc02
VTUN (V)
SUPPLY CURRENT (mA)
CL = 20pF
fCLK_OUT = 73.728MHz
SUPPLY CURRENT
vs. OUTPUT FREQUENCYMAX9485 toc03
OUTPUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)605040302010
VTUN = 1.5V
CL = 20pF
OUTPUT CLOCK RISE/FALL TIME
vs. LOAD CAPACITANCEMAX9485 toc04
LOAD CAPACITANCE (pF)
RISE/FALL TIME (ns)1284
VTUN = 1.5V
fCLK_OUT = 73.728MHz
RISE TIME (tR)
FALL TIME (tF)
MCLK PULLING RANGE
vs. VTUNMAX9485 toc05
VTUN (V)
PULLING RANGE (ppm)
CX1 = CX2 = 5.6pF
CX1 = CX2 = 6.8pF
CX1 = CX2 = 4.7pF
MCLK PERIOD JITTER
vs. OUTPUT FREQUENCYMAX9485 toc06
OUTPUT FREQUENCY (MHz)
PERIOD JITTER (ps
RMS605040302010
VTUN = 1.5V
CL = 15pF
CLK_OUT PERIOD JITTER
vs. OUTPUT FREQUENCYMAX9485 toc07
OUTPUT FREQUENCY (MHz)
PERIOD JITTER (ps
RMS605040302010
VTUN = 1.5V
CL = 15pF
Typical Operating Characteristics(VDD= VDD_P= 3.3V, TA= +25°C.)
MAX9485
Programmable Audio Clock Generator
Pin Description
PIN
TSSOPTQFNNAMEFUNCTION119VDD_PPLL Power Supply. Bypass VDD_P with a 0.1µF and 0.001µF capacitor to GND_P.20GND_PPLL Ground1TUNVCXO Tuning Voltage Input. Apply 0 to 3V at TUN to adjust the VCXO frequency. Connect
TUN to VDD when driving X1 directly with a 27MHz input reference clock.X1Crystal Connection 1. Connect a fundamental mode crystal between X1 and X2 for use as a
VCXO, or drive X1 directly with a 27MHz input reference clock.X2Crystal Connection 2. Connect a fundamental mode crystal between X1 and X2 for use as a
VCXO, or leave X2 unconnected when driving X1 with a 27MHz system reference clock.
6, 174, 15VDDDigital Power Supply. Bypass VDD with a 0.1µF and 0.001µF capacitor to GND.SCL/FS0
Serial Clock/Function Selection Input 0. When MODE = low, SCL/FS0 functions as the I2C
serial clock input. When MODE = high, SCL/FS0 functions as a three-level input to select
sampling frequency.SDA/FS1
Serial Data I/O/Function Selection Input 1. When MODE = low, SDA/FS1 functions as the I2C
serial data input/output. When MODE = high, SDA/FS1 functions as a three-level input to
select output frequency scaling factor.7FS2Function Selection Input 2. When MODE = high, FS2 functions as a three-level input to select
sampling rate. When MODE = low, voltage levels at FS2 do not affect device operation.
10, 11, 158, 9, 13GNDGround10RSTReset Input. Drive RST low resets the I2C register to its default state. RST is internally pulled
to VDD.11MODE
Mode Control Input. When MODE = low, the I2C interface is active. When MODE = high, the
hardwired interface is active, and function selection is programmed by SCL/FS0, SDA/FS1,
and FS2. Mode is internally pulled to GND.12CLK_OUT1Output Clock Port 1. CLK_OUT1 operates at 256/384/768fs, depending on the function
selection. CLK_OUT1 is pulled low when disabled.14CLK_OUT2Output Clock Port 2. CLK_OUT2 operates at 256/384/768fs, depending on the function
selection. CLK_OUT2 is pulled low when disabled.16MCLKMaster System Clock Buffered Output. MCLK outputs the 27MHz clock generated by the
internal VCXO. MCLK is pulled low when disabled.17SAO12C Device Address Selection Input 1 or MCLK Output Enable Control Input.
When MODE = low, SAO1 is a three-level I2C device address programming input. When
MODE = high, SAO1 controls MCLK enable/disable.
20 18SAO22C Device Address Selection Input 2 or CLK_OUT Output Enable Control Input. When MODE
= low, SAO2 is a three-level I2C device address programming input. When MODE = high,
SAO2 controls CLK_OUT1 and CLK_OUT2 enable/disable.Exposed
PadEPExposed Pad. Connect EP to ground.
MAX9485
Programmable Audio Clock Generator
Functional DiagramMCLK
CLK_OUT1
SCL/FS0
SDA/FS1
FS2
CLK_OUT2
VDD
COUNTER NPHASE
DETECTOR
AND LOOP
FILTER
VCO
PLL
DIVIDING
COUNTER
CONTROL
REGISTERS
COUNTER M
RESET
VCXO
TUN
MODE
RST
MAX9485
VDD_P
GNDGND_PSAO1SAO2
Detailed DescriptionThe MAX9485 uses an input reference frequency of
27MHz from a crystal or system reference clock. The
device provides two buffered clock outputs of 256, 384,
or 768 times the chosen sampling frequency (fS) select-
ed through an I2C interface or hardwired inputs.
Sampling frequencies of 12kHz, 32kHz, 44.1kHz,
48kHz, 64kHz, 88.2kHz, or 96kHz are available. The
MAX9485 offers a buffered 27MHz output and an inte-
grated VCXO tuned by a DC voltage generated from the
MPEG system. The device operates with a 3.3V supply.
Reference and Output ClockThe MAX9485 uses the 27MHz crystal or reference
clock (master clock) from the audio system and gener-
ates an output of 256, 384, or 768 times the audio sys-
tem sampling frequency (fS). Connect a fundamental
mode crystal between X1 and X2 or drive X1 with a
27MHz system clock. The choices of sampling frequen-
cies are 12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz,
88.2kHz, and 96kHz. The MAX9485 offers two identical
outputs: CLK_OUT1 and CLK_OUT2. In the following,
the CLK_OUT is used to refer to both outputs. Table 1
shows the relations of fSand the output frequency.
Select the output frequency by programming the I2C
register or hardwiring inputs FS0, FS1, and FS2.
CLK_OUT settling is typically 15ms from power-on or
from applying the clock to X1. Delay time from sampling
frequency change to CLK_OUT settling is 10ms (typ).
Figure 1 illustrates CLK_OUT transient timing in the I2C
programmed case. The I2C register is set through a
master-write data transfer. The frequency settling time
tFSTis counted from the end of the next ACK pulse of
the written byte in SDA until the CLK_OUT is settled.
MAX9485
Voltage-Controlled Crystal Oscillator
(VCXO)The MAX9485 internal VCXO produces a 27MHz refer-
ence clock for the PLL used to generate CLK_OUT1
and CLK_OUT2. The oscillator uses a 27MHz crystal as
the base frequency reference and has a voltage-con-
trolled tuning input for micro adjustment in a range of
±200ppm. The tuning voltage VTUN can vary from 0 to
3V as shown in Figure 2. Use an AT-cut crystal that
oscillates at 27MHz on its fundamental mode with
±30ppm. Use a crystal shunt capacitor less than 12pF,
including board parasitic capacitance. Choose an
oscillator with a load capacitance less than 14pF to
achieve ±200ppm pullability. VCXO, a free-run oscilla-
tor, and the buffered output MCLK are not affected by
power-on reset and external reset. VCXO has a 5ms
settling time at power-on and 10µs at a change of the
VTUN voltage.
The MAX9485 can be used as a synthesizer with a
27MHz input reference clock. For this mode, connect
the 27MHz input clock to X1. Connect TUN to VDDand
leave X2 open. This configuration is for applications
where the micro tuning is not needed and there is a
27MHz system master clock available.
Chip Reset FunctionThe MAX9485 has an internal reset function. The
device resets at power-up or can be externally reset by
driving RSTlow. The reset function sets the registers to
default values. MODE sets the device’s programming
mode at power-up. When MODE = low, the device is
set to software-programmable mode. Set MODE = high
for hardwired mode. If MODE = low, the reset sets
default values for CLK_OUT1 and CLK_OUT2 to 256 xwith fS= 32kHz. If MODE = high, the reset sets
CLK_OUT1 and CLK_OUT2, according to the values of
the hardwired inputs.
Programmable Audio Clock Generator
Table1. Sampling Frequency and Output Clock
SAMPLING
FREQUENCYCLK_OUTfS (kHz)256 x fS (MHz)384 x fS (MHz)768 x fS (MHz)
SAMPLING RATE3.0724.6089.126Standard8.192012.288024.5760Standard
44.111.289616.934433.8688Standard12.288018.432036.8640Standard16.384024.576049.1520Double
88.222.579233.868867.7376Double24.576036.864073.7280Double
tFST
TRANSITIONSTABLESTABLE
ACK
PULSE
CLK_OUT
SDA
HIGH
LOW
Figure1. CLK_OUT Transient Timing
27.0054400ppm
VCXO OUTPUT FREQUENCY
(MHz)
26.9946VTUN3V
Figure2. VCXO Tuning Range
