MAX9374AEKA-T ,Differential LVPECL-to-LVDS TranslatorsApplications Ordering InformationPrecision Clock BufferTEMP PIN- TOPPARTLow-Jitter Data Repeater RA ..
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MAX9375EUA+T ,Single LVDS/Anything-to-LVPECL TranslatorELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential input voltage |V | = 0.1V to 3.0V, inpu ..
MAX9376EUB ,LVDS/Anything-to-LVPECL/LVDS Dual TranslatorELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential input voltage |V | = 0.1V to 3.0V, inpu ..
MAX9376EUB+ ,LVDS/Anything-to-LVPECL/LVDS Dual TranslatorElectrical Characteristics(V = +3.0V to +3.6V, differential input voltage |V | = 0.1V to 3.0V, inpu ..
MAX9380ESA ,Single-Ended-to-Differential LVECL/LVPECL 2:1 MultiplexerELECTRICAL CHARACTERISTICS(V - V = +3.0V to +3.8V, outputs terminated with 50Ω to V - 2.0V, unless ..
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I Full or Hall Duplex
Operation
I Completely Programmable
I Start Bit Generated
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MAX9374AEKA-T
Differential LVPECL-to-LVDS Translators
General DescriptionThe MAX9374 and MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators and are designed for tele-
com applications. They feature 250ps propagation
delay. The differential output conforms to the ANSI
TIA/EIA-644 LVDS standard. The inputs are biased with
internal resistors such that the output is differential low
when inputs are open. An on-chip VBBreference output
is available for single-ended operation.
The MAX9374 is designed for low-voltage operation
from a 2.375V to 2.625V power supply for use in 2.5V
systems. The MAX9374A is designed for 3.0V to 3.6V
operation in systems with a nominal 3.3V supply. Both
devices are offered in industry-standard 8-pin SOT23
and SO packages.
ApplicationsPrecision Clock Buffer
Low-Jitter Data Repeater
Central Office Clock Distribution
DSLAM/DLC
Base Station
Mass Storage
FeaturesGuaranteed 2.0GHz Operating Frequency250ps (typ) Propagation Delay1.0ps RMS Jitter (typ)2.375V to 2.625V Low-Voltage Supply Range
(MAX9374)On-Chip VBBReference for Single-Ended InputOutput Low for Open InputsOutput Conforms to ANSI TIA/EIA-644 LVDS
StandardESD Protection >2.0kV (Human Body Model)Available in Small 8-Pin SOT23 Package
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
Ordering Information
Typical Application Circuit19-2326; Rev 0; 1/02
Pin Configurations/Functional Diagrams appear at end of
data sheet.
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= 2.375V to 2.625V for MAX9374, VCC= 3.0V to 3.6V for MAX9374A, 100Ω±1% across outputs, VID= 0.095V to VCCor 3V,
whichever is less, VIHD= 1.2V to VCC, VILD= GND to VCC- 0.095V, unless otherwise noted. Typical values are at VIHD= 2.0V, VILD=
1.85V, VCC= 3.3V for MAX9374A, VCC= 2.5V for MAX9374.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................................4.0V
VD, VDto GND..............................................-0.3V to VCC+ 0.3Vto VD................................................................................3.0V
VBBSink/Source Current.......................................................1mA
Short-Circuit Duration (Q, Qto GND).........................Continuous
Short-Circuit Duration (Q to Q)...................................Continuous
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW
8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW
Junction-to-Ambient Thermal Resistance
8-Pin SOT23.............................................................+112°C/W
8-Pin SO...................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
8-Pin SOT23...............................................................+78°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin SOT23...............................................................+80°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (D, D, Q, Q).......................................2kV
Soldering Temperature (10s)...........................................+300°C
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.375V to 2.625V for MAX9374, VCC= 3.0V to 3.6V for MAX9374A, 100Ω±1% across outputs, VID= 0.095V to VCCor 3V,
(VCC= 2.375V to 2.625V for MAX9374, VCC= 3.0V to 3.6V for MAX9374A, 100Ω±1% across outputs, VIHD- VILD= 0.15V to VCCor
3V, whichever is less, VIHD= 1.2V to VCC, VILD= GND to VCC- 0.15V, fIN= 1GHz, input transition time = 125ps, input duty cycle =
50%, unless otherwise noted. Typical values are at VIHD= 2.0V, VILD= 1.85V, VCC= 3.3V for MAX9374A, VCC= 2.5V for MAX9374,
unless otherwise noted.) (Notes 1, 6)
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
Typical Operating Characteristics(MAX9374A, 100Ω±1% across outputs, fIN= 1GHz, input transition time = 125ps, input duty cycle = 50%, VCC= 3.3V, VIHD= 2.0V,
VILD= 1.85V, TA= +25°C, unless otherwise noted.)
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:DC parameters are production tested at TA= +25°C and guaranteed by design over the full operating temperature range.
Note 3:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 4:Use VBBas a reference for inputs on the same device only.
Note 5:100Ωacross the outputs, all other pins open except VCCand GND.
Note 6:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 7:Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 8:Device jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.375V to 2.625V for MAX9374, VCC= 3.0V to 3.6V for MAX9374A, 100Ω±1% across outputs, VIHD- VILD= 0.15V to VCCor
3V, whichever is less, VIHD= 1.2V to VCC, VILD= GND to VCC- 0.15V, fIN= 1GHz, input transition time = 125ps, input duty cycle =
50%, unless otherwise noted. Typical values are at VIHD= 2.0V, VILD= 1.85V, VCC= 3.3V for MAX9374A, VCC= 2.5V for MAX9374,
unless otherwise noted.) (Notes 1, 6)
MAX9374/MAX9374A
Differential LVPECL-to-LVDS TranslatorsFigure 1. MAX9374/MAX9374A Timing Diagram
MAX9374/MAX9374A
Detailed DescriptionThe MAX9374/MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators. The output is differential
LVDS and conforms to the ANSI TIA/EIA-644 LVDS
standard. The inputs are biased with internal resistors
such that the output is differential low when inputs are
open. An on-chip VBBreference output is available for
single-ended input operation.The MAX9374 is
designed for low-voltage operation from 2.375V to
2.625V in systems with a nominal 2.5V supply. The
MAX9374A is designed for 3.0V to 3.6V operation in
systems with a nominal 3.3V supply.
Differential LVPECL InputThe MAX9374/MAX9374A accept differential LVPECL
inputs and can be configured to accept single-ended
inputs through the use of the VBBvoltage reference out-
put. The maximum magnitude of the differential signal
applied to the input is 3.0V or VCC, whichever is less.
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
Specifications for the high and low voltages of a differ-
ential input (VIHDand VILD) and the differential input
voltage (VIHD- VILD) apply simultaneously.
Single-Ended Inputs and VBBThe differential inputs can be configured to accept a
single-ended input through the use of the VBBrefer-
ence voltage. A noninverting, single-ended input is pro-
duced by connecting VBBto the Dinput and applying a
single-ended input signal to the D input. Similarly, an
inverting input is produced by connecting VBBto the D
input and applying the input signal to the Dinput. With
a differential input configured as single ended (using
VBB), the single-ended input can be driven to VCCand
GND or with a single-ended LVPECL signal. Note that a
single-ended input must be at least VBB±95mV or a
differential input of at least 95mV to switch the outputs
to the VOHand VOLlevels specified in the DC Electrical
Characteristicstable.
When using the VBBreference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBBreference is
not used, leave it unconnected. Use VBBonly for inputs
that are on the same device as the VBBreference.
Input Bias ResistorsInternal biasing resistors ensure a (differential) output-
low condition in the event that the inputs are not connect-
ed. The inverting input (D) is biased with a 36.5kΩpull-
down to VCCand a 75kΩpullup to GND. The
noninverting input (D) is biased with a 75kΩpullup to
VCCand 75kΩpulldown to GND.
Differential LVDS OutputThe differential outputs conform to the ANSI TIA/EIA-644
LVDS standard. Typically, terminate the outputs with 100Ω
across Q and Q, as shown in the Typical Application
Circuit. The outputs are short-circuit protected.
Applications Information
Supply BypassingBypass VCCto GND with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel and as
close to the device as possible, with the 0.01µF capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBBref-
erence output, bypass it with a 0.01µF ceramic capaci-
tor to VCC(if the VBBreference is not used, it can be
left open).
Controlled-Impedance TracesInput and output trace characteristics affect the perfor-
mance of the MAX9374/MAX9374A. Connect high-fre-
quency input and output signals to 50Ωcharacteristic
impedance traces. Minimize the number of vias to pre-
vent impedance discontinuities. Reduce reflections by
maintaining the 50Ωcharacteristic impedance through
cables and connectors. Reduce skew within a differen-
tial pair by matching the electrical length of the traces.
Output TerminationTerminate the outputs with 100Ωacross Q and Qas
shown in the Typical Application Circuit. Both outputs
must be terminated.
Differential LVPECL-to-LVDS Translators
