MAX9324EUP+ ,One-to-Five LVPECL/LVCMOS Output Clock and Data DriverApplications*Future product—Contact factory for availability.**EP = Exposed paddle.Precision Clock ..
MAX9325EQI ,+2.375 V to +3.8 V, 2:8 differential LVPECL/LVECL/HSTL clock and data driverApplicationsFunctional Diagram appears at end of data sheet.Precision Clock DistributionLow-Jitter ..
MAX932CPA ,Ultra Low-Power, Low-Cost Comparators with 2eferenceGeneral Description ________
MAX932CSA ,Ultra Low-Power, Low-Cost Comparators with 2eferenceELECTRICAL CHARACTERISTICS—5V Operation (continued)(V+ = 5V, V- = GND = 0V, T = T to T , unless oth ..
MAX932CSA ,Ultra Low-Power, Low-Cost Comparators with 2eferenceGeneral Description ________
MAX932CSA+ ,Ultra-Low-Power, Low-Cost Comparators with 2% ReferenceFeaturesThe MAX931-MAX934 single, dual, and quad micropower, ♦ Ultra-Low 4μA Max Quiescent Currentl ..
MB8868A ,MOS Universal Asynchronous Receiver / Transmitter (UART)Features
I Full or Hall Duplex
Operation
I Completely Programmable
I Start Bit Generated
..
MB89121 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12509-6EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89120/1 ..
MB89123A ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12509-6EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89120/1 ..
MB89133A ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12510-9EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89130/1 ..
MB89153 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12506-4EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89150/1 ..
MB89163 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12405-2EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89160/1 ..
MAX9324EUP+
One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
General DescriptionThe MAX9324 low-skew, low-jitter, clock and data driver
distributes a differential LVPECL input to four differential
LVPECL outputs and one single-ended LVCMOS output.
All outputs default to logic low when the differential inputs
equal GND or are left open. The MAX9324 operates from
3.0V to 3.6V, making it ideal for 3.3V systems, and con-
sumes only 25mA (max) of supply current.
The MAX9324 features low 150ps (max) part-to-part
skew, low 15ps output-to-output skew, and low 1.7ps
RMS jitter, making the device ideal for clock and data
distribution across a backplane or board. CLK_EN and
SEOUT_Z control the status of the various outputs.
Asserting CLK_EN low configures the differential (Q_,
Q_) outputs to a differential low condition and SEOUT to
a single-ended logic-low state. CLK_EN operation is
synchronous with the CLK_ inputs. A logic high on
SEOUT_Z places SEOUT in a high-impedance state.
SEOUT_Z is asynchronous with the CLK (CLK) inputs.
The MAX9324 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range.
ApplicationsPrecision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Features15ps Differential Output-to-Output Skew1.7psRMSAdded Random Jitter150ps (max) Part-to-Part Skew450ps Propagation DelaySynchronous Output Enable/DisableSingle-Ended Monitor OutputOutputs Assert Low when CLK, CLKare Open or
at GND3.0V to 3.6V Supply Voltage Range-40°C to +85°C Operating Temperature Range
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Ordering Information19-2576; Rev 0; 10/02
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
PARTTEMP RANGEPIN-PACKAGEMAX9324EUP-40°C to +85°C20 TSSOP
MAX9324ETP*-40°C to +85°C20 Thin QFN-EP**
VCCSEOUT
N.C.
CLK_EN
GND
TOP VIEW
VCCCLK
SEOUT_Z
N.C.
GND
VCC
MAX9324
TSSOP**EXPOSED PADDLE
THIN QFN-EP** (4mm x 4mm)**CONNECT EXPOSED PADDLE TO GND.
SEOUT
GND
N.C.
SEOUT_Z
CLK
VCC
N.C.CLK_ENGNDQ0Q0
MAX9324
CLK
CLK
Pin Configurations*Future product—Contact factory for availability.
**EP = Exposed paddle.
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, differential outputs terminated with 50Ω±1% to (VCC- 2V), SEOUT_Z = GND, CLK_EN = VCC, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at VCC= 3.3V, TA= +25°C.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
Q_, Q_, CLK, CLK, SEOUT_Z, CLK_EN,
SEOUT to GND.......................................-0.3V to (VCC+ 0.3V)
CLK to CLK............................................................................±3V
SEOUT Short to GND.................................................Continuous
Continuous Output Current (Q_, Q_)..................................50mA
Surge Output Current (Q_, Q_).........................................100mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm ✕4mm Thin QFN (derate 16.9mW/°C)..1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP............................................................+91°C/W
20-Pin 4mm ✕4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP............................................................+20°C/W
20-Pin 4mm ✕4mm Thin QFN......................................+2°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (10s)...........................................+300°C
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (CLK_EN, SEOUT_Z)Input High VoltageVIH2VCCV
Input Low VoltageVIL00.8V
CLK_EN = VCC-5+5Input High CurrentIIHSEOUT_Z = VCC150µA
CLK_EN = GND-150Input Low CurrentIILSEOUT_Z = GND-5+5µA
DIFFERENTIAL INPUT (CLK, CLK)Differential Input High VoltageVIHDFigure 11.5VCCV
Differential Input Low VoltageVILDFigure 10VCC - 0.15V
Differential Input VoltageVIHD - VILD0.151.5V
Input CurrentICLKVIHD, VILD-5+150µA
DIFFERENTIAL OUTPUTS (Q_, Q_)Single-Ended Output HighVOHFigure 1VCC - 1.4VCC - 1.0V
Single-Ended Output LowVOLFigure 1VCC - 2.0VCC - 1.7V
Differential Output VoltageVOH - VOLFigure 10.60.85V
SINGLE-ENDED OUTPUT (SEOUT)Output High VoltageVOHIOH = -4mA2.4V
Output Low VoltageVOLIOL = 4mA0.4V
Output High-Impedance CurrentIOZSEOUT_Z = VCC, SEOUT = VCC or GND-10+10µA
Output Short-Circuit CurrentIOSVCLK = VCC, SEOUT = GND75mA
SUPPLYSupply CurrentICC(Note 4)25mA
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:DC parameters are production tested at TA= +25°C and guaranteed by design over the full operating temperature range.
Note 4:All pins open except VCCand GND.
Note 5:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 6:Measured from the differential input signal crosspoint to the differential output signal crosspoint.
Note 7:Measured between the differential outputs of the same part at the differential signal crosspoint for a same-edge transition.
Note 8:Measured between the differential outputs of different parts at the differential signal crosspoint under identical conditions
for a same-edge transition.
Note 9:Jitter added to the input signal.
Note 10:Measured at 50% of VCC.
AC ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, differential outputs terminated with 50Ω±1% to (VCC- 2V), fCLK≤266MHz, input duty cycle = 50%, input transi-
tion time = 125ps (20% to 80%), VIHD= 1.5V to VCC, VILD= GND to (VCC- 0.15V), VIHD- VILD= 0.15V to 1.5V, CLK_EN = VCC,
SEOUT_Z = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, VIHD= (VCC- 1V), VILD= (VCC-
1.5V), TA= +25°C.) (Note 5)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSVOH - VOL ≥ 0.6V, SEOUT_Z = VCC650800Switching FrequencyfMAXSEOUT_Z = GND, SEOUT125200MHz
Propagation DelaytPHL, tPLHCLK, CLK to Q_, Q_, Figure 1 (Note 6)100450600ps
Output-to-Output SkewtSKOO(Note 7)30ps
Part-to-Part SkewtSKPP(Note 8)150ps
Output Rise TimetR20% to 80%, Figure 1100217300ps
Output Fall TimetF80% to 20%, Figure 1100207300ps
Output Duty CycleODC485052%
Added Random JittertRJfCLK = 650MHz (Note 9)1.73ps(RMS)
Added Deterministic JittertDJ2e23 - 1 PRBS pattern, f = 650Mbps (Note 9)83100ps(P-P)
Added JittertAJVCC = 3.3V with 25mV superimposed
sinusoidal noise at 100kHz (Note 9)8.512ps(P-P)
Single-Ended Output Rise TimetRCL = 15pF, 20% to 80%, Figure 11.62ns
Single-Ended Output Fall TimetFCL = 15pF, 80% to 20%, Figure 11.62ns
Single-Ended Output Duty CycleODC(Note 10)405260%
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Typical Operating Characteristics(VCC= 3.3V, outputs terminated to (VCC- 2V) through 50Ω, SEOUT_Z = VCC, CLK_EN = VCC, TA= +25°C.)
SUPPLY CURRENT vs. TEMPERATUREMAX9324 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)35-1510
DIFFERENTIAL OUTPUT AMPLITUDE
(VOH - VOL) vs. FREQUENCY
MAX9324 toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (mV)
DIFFERENTIAL OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9324 toc03
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT RISE/FALL TIME (ps)3510-15
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9324 toc04
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ps)3510-15
tPHL
tPLH
MAX9324
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Pin Description
PIN
TSSOPQFNNAMEFUNCTION1, 52, 18GNDGround. Provide a low-impedance connection to the ground plane.19CLK_EN
Synchronous Output Enable. Connect CLK_EN to VCC or leave floating to enable the
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low, Q_ asserts high, and SEOUT asserts low. A 51kΩ pullup resistor to
VCC allows CLK_EN to be left floating.
3, 63, 20N.C.No Connect. Not internally connected.1SEOUT
LVCMOS/LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT
goes high impedance when SEOUT_Z = VCC. The maximum output frequency of SEOUT is
125MHz.4SEOUT_Z
Single-Ended Clock Output Enable/Disable. Connect SEOUT_Z to GND to enable the single-
ended clock output. Connect SEOUT_Z to VCC to disable the single-ended clock output. A
51kΩ pulldown resistor to GND allows SEOUT_Z to be left floating.5CLK
Noninverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the
outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or
at GND and the outputs are enabled.CLK
Inverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the
outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or
at GND and the outputs are enabled.
10, 13, 187, 10, 15VCC
Positive Supply Voltage. Bypass VCC to GND with three 0.01µF and one 0.1µF ceramic
capacitors. Place the 0.01µF capacitors as close to each VCC input as possible (one per VCC
input). Connect all VCC inputs together, and bypass to GND with a 0.1µF ceramic capacitor.8Q3Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.9Q3Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.11Q2Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.12Q2Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.13Q1Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.14Q1Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.16Q0Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.17Q0Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.
MAX9324
Detailed DescriptionThe MAX9324 low-skew, low-jitter, clock and data dri-
ver distributes a differential LVPECL input signal to four
differential LVPECL outputs and a single-ended LVC-
MOS output. The differential output drivers operate at
frequencies up to 800MHz. When SEOUT_Z = GND,
the single-ended LVCMOS output driver operates with
frequencies as high as 200MHz. The MAX9324 oper-
ates from 3.0V to 3.6V, making the device ideal for 3.3V
systems.
Data Inputs
Differential LVPECL InputsThe MAX9324 accepts a differential LVPECL input.
Each differential output duplicates the differential input
signal. Terminate CLK and CLKthrough 50Ωto (VCC-
2V) to minimize input signal reflections. Internal 51kΩ
pulldown resistors to GND ensure the outputs default to
differential low (Q_, Q_) or logic low (SEOUT) when the
CLK inputs are left open.
CLK_EN InputCLK_EN enables/disables the differential outputs of the
MAX9324. Connect CLK_EN to VCCto enable the dif-
ferential outputs. The (Q_, Q_) outputs are driven to a
differential low condition when CLK_EN = GND. Each
differential output pair disables following successive
rising and falling edges on CLK (falling and rising
edges on CLK), after CLK_EN connects to GND. Both a
rising and falling edge on CLK are required to com-
plete the enable/disable function (Figure 2).
One-to-Five LVPECL/LVCMOS Output Clock and
Data DrivertPLH
VOH - VOL
20%
80%80%
20%
Q_ - Q_
CLK
CLK
VOL
VOH
tPHLtF
20%
80%80%
20%
SEOUTtF
VILD
VIHD
Figure 1. MAX9324 Clock Input-to-Output Delay and Rise/Fall Time
