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MAX9317AECJ+T
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
General Description
The MAX9317/MAX9317A/MAX9317B/MAX9317C low-
skew, dual 1-to-5 differential drivers are designed for
clock and data distribution. The differential input is
reproduced at five LVDS outputs with a low output-to-
output skew of 5ps.
The MAX9317/MAX9317A are designed for low-voltage
operation from a 2.375V to 2.625V power supply for use
in 2.5V systems. The MAX9317B/MAX9317C operate
from a 3.0V to 3.6V power supply for use in 3.3V sys-
tems. The MAX9317A/MAX9317C feature 50Ωinput ter-
mination resistors to reduce component count.
The MAX9317 family is available in 32-pin 7mm ✕7mm
TQFP and space-saving 5mm ✕5mm QFN packages
and operate across the extended temperature range of
-40°C to +85°C. The MAX9317A is pin compatible with
ON Semiconductor’s MC100EP210S.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM Backplanes
Base Stations
ATE
FeaturesGuaranteed 1.0GHz Operating Frequency145ps (max) Part-to-Part Skew5ps Output-to-Output Skew330ps Propagation Delay from CLK_ to Q_2.375V to 2.625V Operation (MAX9317/MAX9317A)3.0V to 3.6V Operation (MAX9317B/MAX9317C)ESD Protection: ±2kV (Human Body Model)Internal 50ΩInput Termination Resistors
(MAX9317A/MAX9317C)
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Ordering Information
MAX9317
MAX9317A
MAX9317B
MAX9317C
QA0
QA0
QA1
QA1QA3QA3QA4QA4QB0QB0QB1QB1
QA2
QA211
QB4QB413
QB3QB315
QB2QB2
1, 8
9, 16
25, 32VCC
VTA
CLKA
CLKA
CLKB
VTB
GND
CLKB
RIN
50Ω
RIN
50Ω
RIN
50Ω
RIN
50Ω
MAX9317A/MAX9317C ONLY.
19-2543; Rev 0; 7/02
PA RT T EM P R AN G EPIN-
PA CK A G EO M IN A L
SU PPL Y
VO LT A G EV)
MAX9317ETJ*-40°C to +85°C32 Thin QFN2.5
MAX9317ECJ-40°C to +85°C32 TQFP2.5
MAX9317AETJ*-40°C to +85°C32 Thin QFN2.5
MAX9317AECJ-40°C to +85°C32 TQFP2.5
MAX9317BETJ*-40°C to +85°C32 Thin QFN3.3
MAX9317BECJ-40°C to +85°C32 TQFP3.3
MAX9317CETJ*-40°C to +85°C32 Thin QFN3.3
MAX9317CECJ-40°C to +85°C32 TQFP3.3
Pin Configurations appear at end of data sheet.*Future product—contact factory for availability.
Functional Diagram
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= 2.375V to 2.625V (MAX9317/MAX9317A), VCC= 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100Ω±1%
between Q_ and Q_, unless otherwise noted. Typical values are at VCC= 2.5V (MAX9317/MAX9317A), VCC= 3.3V
(MAX9317B/MAX9317C), VIHD= VCC- 1.0V, VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.1V
Input Pins to GND.......................................-0.3V to (VCC+ 0.3V)
Differential Input Voltage.............VCCor 3.0V, whichever is less
Continuous Output Current.................................................28mA
Surge Output Current..........................................................50mA
Continuous Power Dissipation (TA= +70°C)
32-Pin, 7mm ✕7mm TQFP
(derate 20.7mW/°C above +70°C).................................1.65W
32-Pin 5mm ✕5mm QFN
(derate 21.3mW/°C above +70°C)...................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin, 7mm ✕7mm TQFP......................................+48.4°C/W
32-Pin, 5mm ✕5mm QFN..........................................+47°C/W
Junction-to-Case Thermal Resistance
32-Pin, 7mm ✕7mm TQFP.........................................+12°C/W
32-Pin, 5mm ✕5mm QFN............................................+2°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (CLK_, CLK_, Q_, Q_, VT_).............±2kV
Soldering Temperature (10s)...........................................+300°C
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
INPUTS (CLK_, CLK_)
Differential Input
High VoltageVIHDFigure 11.2VCC1.2VCC1.2VCCV
Differential Input
Low VoltageVILDFigure 10VCC
- 0.10VCC
- 0.10VCC
- 0.1V
MAX9317/
MAX9317A0.1VCC0.1VCC0.1VCC
Differential Input
VoltageVIDVIHD -
VILDMAX9317B/
MAX9317C0.13.00.13.00.13.0
Input CurrentIIH, IIL
CLK_, or CLK_ =
VIHD or VILD,
MAX9317/MAX9317B
-60+60-60+60-60+60µA
Input Termination
ResistanceRINMAX9317A/MAX9317C,
Figure 2 (Note 4)435057435057435057Ω
OUTPUTS (Q_, Q_)
Output High
VoltageVOHFigure 11.61.61.6V
Output Low
VoltageVOLFigure 10.90.90.9V
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.375V to 2.625V (MAX9317/MAX9317A), VCC= 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100Ω±1%
between Q_ and Q_, unless otherwise noted. Typical values are at VCC= 2.5V (MAX9317/MAX9317A), VCC= 3.3V
(MAX9317B/MAX9317C), VIHD= VCC- 1.0V, VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
Differential
Output VoltageVODFigure 1250350450250350450250350450mV
Change in VOD
Between
Complementary
Output States
ΔVOD750650650mV
Output Offset
VoltageVOS1.1251.251.3751.1251.251.3751.1251.251.375V
Change in VOS
Between
Complementary
Output States
ΔVOS252525mV
Q_ shorted to Q_121212Output Short-
Circuit CurrentIOSCQ_ or Q_ shorted to
GND282828mA
POWER SUPPLY
MAX9317/9317A691077510780107Power-Supply
Current (Note 5)ICCMAX9317B/9317C751078110786107mA
AC ELECTRICAL CHARACTERISTICS
(VCC= 2.375V to 2.625V (MAX9317/MAX9317A) or VCC= 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100Ω±1%,
between Q_ and Q_, fIN≤1.0GHz, input transition time = 125ps (20% to 80%), VIHD- VILD= 0.15V to VCC, unless otherwise noted.
Typical values are at VCC= 2.5V (MAX9317/MAX9317A), VCC= 3.3V (MAX9317B/MAX9317C), fIN= 1.0GHz, VIHD= VCC- 1.0V,
VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1 and 4)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
Propagation
Delay CLK_,
CLK_ to Q_, Q_
tPHL
tPLHFigure 1250310600250330600250335600ps
Output-to-Output
SkewtSKEW1(Note 6)955545425ps
Part-to-Part SkewtSKEW2(Note 7)145145145ps
Added Random
JittertRJfIN = 1.0GHz, clock
pattern (Note 8)0.82.00.82.00.82.0ps(RMS)
Added
Deterministic JittertDJfIN = 1.0GHz, 223 - 1
PRBS pattern (Note 8)801058010580105ps(P-P)
Operating
FrequencyfMAXVOD ≥ 250mV1.01.01.0GHz
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
SUPPLY CURRENT vs. TEMPERATURE
MAX9317 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15-4085
INPUTS OPEN, OUTPUTS TERMINATED
WITH 100Ω DIFFERENTIAL
OUTPUT AMPLITUDE (VOH - VOL)
vs. CLK_ FREQUENCY
MAX9317 toc02
CLK_ FREQUENCY (GHz)
OUTPUT AMPLITUDE (mV)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9317 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)3510-15
FALL TIME
RISE TIME
CLK-TO-Q PROPAGATION DELAY
vs. TEMPERATURE
MAX9317 toc04
CLK-TO-Q PROPAGATION DELAY (ps)
tPLH
tPHL
CLK-TO-Q PROPAGATION DELAY vs. HIGH
VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9317 toc05
CLK-TO-Q PROPAGATION DELAY (ps)
tPLH
tPHL
Typical Operating Characteristics
(MAX9317, VCC= 2.5V, all outputs loaded with 100Ω±1%, between Q_ and Q_, fIN= 1.0GHz, input transition time = 125ps (20% to
80%), VIHD= VCC- 1.0V, VILD= VCC- 1.5V, unless otherwise noted.)
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4:Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma.
Note 5:All outputs loaded with 100Ωdifferential, all inputs biased differential high or low except VT_.
Note 6:Measured between outputs of the same device at the signal crossing points for a same-edge transition.
Note 7:Measured between outputs on different devices for identical transitions and VCClevels.
Note 8:Device jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.375V to 2.625V (MAX9317/MAX9317A) or VCC= 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100Ω±1%,
between Q_ and Q_, fIN≤1.0GHz, input transition time = 125ps (20% to 80%), VIHD- VILD= 0.15V to VCC, unless otherwise noted.
Typical values are at VCC= 2.5V (MAX9317/MAX9317A), VCC= 3.3V (MAX9317B/MAX9317C), fIN= 1.0GHz, VIHD= VCC- 1.0V,
VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1 and 4)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
Differential
Output Rise/Fall
Time
tR/tF20% to 80%, Figure 1140200300140205300140205300ps
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Pin Description
NAME
PINMAX9317
MAX9317B
MAX9317A
MAX9317C
FUNCTION
1, 8GNDGNDGround
N.C.—No Connection. Connect this pin to ground or leave floating.—VTA
CLKA Input Termination Voltage. This pin is connected to CLKA and CLKA through 50Ω
termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKA or
leave floating for an LVDS input signal.CLKACLKANoninverting Differential Clock Input ACLKACLKAInverting Differential Clock Input A
N.C.—No Connection. Connect this pin to ground or leave floating.—VTB
CLKB Input Termination Voltage. This pin is connected to CLKB and CLKB through 50Ω
termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKB or
leave floating for an LVDS input signal.CLKBCLKBNoninverting Differential Clock Input BCLKBCLKBInverting Differential Clock Input B
9, 16,
25, 32VCCVCC
Positive Supply Voltage. Bypass each VCC pin to ground with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the 0.01µF
capacitor closest to the device.QB4QB4CLKB Inverting Differential Output 4. Terminate with 100Ω to QB4.QB4QB4CLKB Noninverting Differential Output 4. Terminate with 100Ω to QB4.QB3QB3CLKB Inverting Differential Output 3. Terminate with 100Ω to QB3.QB3QB3CLKB Noninverting Differential Output 3. Terminate with 100Ω to QB3.QB2QB2CLKB Inverting Differential Output 2. Terminate with 100Ω to QB2.QB2QB2CLKB Noninverting Differential Output 2. Terminate with 100Ω to QB2.QB1QB1CLKB Inverting Differential Output 1. Terminate with 100Ω to QB1.QB1QB1CLKB Noninverting Differential Output 1. Terminate with 100Ω to QB1.QB0QB0CLKB Inverting Differential Output 0. Terminate with 100Ω to QB0.QB0QB0CLKB Noninverting Differential Output 0. Terminate with 100Ω to QB0.QA4QA4CLKA Inverting Differential Output 4. Terminate with 100Ω to QA4.QA4QA4CLKA Noninverting Differential Output 4. Terminate with 100Ω to QA4.QA3QA3CLKA Inverting Differential Output 3. Terminate with 100Ω to QA3.QA3QA3CLKA Noninverting Differential Output 3. Terminate with 100Ω to QA3.QA2QA2CLKA Inverting Differential Output 2. Terminate with 100Ω to QA2.QA2QA2CLKA Noninverting Differential Output 2. Terminate with 100Ω to QA2.QA1QA1CLKA Inverting Differential Output 1. Terminate with 100Ω to QA1.QA1QA1CLKA Noninverting Differential Output 1. Terminate with 100Ω to QA1.QA0QA0CLKA Inverting Differential Output 0. Terminate with 100Ω to QA0.QA0QA0CLKA Noninverting Differential Output 0. Terminate with 100Ω to QA0.EPEPExposed Pad. QFN package only. Internally connected to ground.
MAX9317/MAX9317A/MAX9317B/MAX9317C
Detailed Description
The MAX9317 family of low-skew, 1-to-5 dual differen-
tial drivers are designed for clock or data distribution.
Two independent 1-to-5 splitters accept a differential
input signal and reproduce it on five separate differen-
tial LVDS outputs. The output drivers are guaranteed to
operate at frequencies up to 1.0GHz with the LVDS out-
put levels conforming to the EIA/TIA-644 standard.
The MAX9317/MAX9317A operate from a 2.375V to
2.625V power supply for use in 2.5V systems. The
MAX9317B/MAX9317C operate from a 3.0V to 3.6V
supply for 3.3V systems.
Differential LVPECL and LVDS Input
The MAX9317 family has two input differential pairs:
CLKA and CLKA,and CLKB and CLKB. Each differen-
tial input pair can be configured or terminated indepen-
dently. The inputs are designed to be driven by either
LVPECL or LVDS signals with a maximum differential
voltage of VCCor 3.0V, whichever is less.
The MAX9317A/MAX9317C reduce external component
count by having the input 50Ωtermination resistors on
chip. Configure the MAX9317A/MAX9317C to receive
LVPECL signals by connecting VT_to VCC- 2V (Figure
2(a)). Leaving the VT_input floating configures the
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
CLK
CLK
Q_ - Q_
20%
80%
(DIFFERENTIAL)
DIFFERENTIAL
OUTPUT
WAVEFORM
20%
80%
VIHD
VILD
VOH
VOL
VIHD - VILD
VOD
tPLHtPHLtR
Figure 1. MAX9317 Timing Diagram
MAX9317A
MAX9317C
LVPECL
DRIVER
RIN
50Ω
RIN
50Ω
VCC -
2.0V
CLK_
VT_
CLK_
(a) MAX9317A/MAX9317C CONFIGURED FOR LVPECL INPUT SIGNALS.
MAX9317A
MAX9317C
LVDS
DRIVER
RIN
50Ω
RIN
50Ω
VT_
CLK_
CLK_
(b) MAX9317A/MAX9317C CONFIGURED FOR LVDS INPUT SIGNALS.
Figure 2. MAX9317A/MAX9317C Input Terminations

Partno	Mfg	Dc	Qty	Available	Descript
MAX9317AECJ+T	MAXIM	N/a	2372	avai	Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs