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MAX9310EUP
1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs
General DescriptionThe MAX9310 is a fast, low-skew 1:5 differential driver
with selectable LVPECL/HSTL inputs and LVDS out-
puts, designed for clock distribution applications. This
device features an ultra-low propagation delay of 345ps
with 45.5mA of supply current.
The MAX9310 operates from a 2.375V to 2.625V power
supply for use in 2.5V systems. A 2:1 input multiplexer
is used to select one of two differential inputs. The input
selection is controlled through the CLKSEL pin. This
device also features a synchronous enable function.
The MAX9310 is offered in a space-saving 20-pin
TSSOP package and operates over the extended tem-
perature range from -40°C to +85°C.
ApplicationsData and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM
Base Stations
ATE
FeaturesGuaranteed 1.0GHz Operating Frequency8ps Output-to-Output Skew345ps Propagation DelayAccepts LVPECL and Differential HSTL InputsSynchronous Output Enable/DisableTwo Selectable Differential Inputs2.375V to 2.625V Supply VoltageESD Protection: ±2kV (Human Body Model)Input Bias Resistors Drive Output Low for Open
Inputs
MAX9310
1:5 Clock Driver with Selectable VPECL Inputs and LVDS OutputsVCC
VCC
CLK1Q1
TOP VIEW
CLK1
I.C.
CLK0
CLK0Q3
CLKSEL
GNDQ4
MAX9310
TSSOP
Pin Configuration
Ordering Information100Ω
MAX9310
ZO = 50Ω
ZO = 50Ω
RECEIVER
Typical Application Circuit19-2541; Rev 0; 7/02
Functional diagram appears at end of data sheet.
PARTTEMP RANGEPIN-PACKAGEMAX9310EUP-40°C to +85°C20 TSSOP
MAX9310
1:5 Clock Driver with Selectable
LVPECL Inputs and LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC- GND = 2.375V to 2.625V, outputs terminated with 100Ω±1%, unless otherwise noted. Typical values are at VCC- GND = 2.5V,
VIHD= VCC- 1.0V, VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.1V
EN, CLKSEL, CLK_, CLK_, to GND............-0.3V to (VCC+ 0.3V)
CLK_ to CLK_...........................................................|VCC- GND|
Continuous Output Current.................................................24mA
Surge Output Current..........................................................50mA
Continuous Power Dissipation (TA= +70°C)
Single-Layer PC Board
20-Pin TSSOP (derate 7.69mW/°C above +70°C)......615mW
Multilayer PC Board
20-Pin TSSOP (derate 11mW/°C above +70°C).........879mW
Junction-to-Ambient Thermal Resistance in Still Air
Single-Layer PC Board
20-Pin TSSOP.........................................................+130°C/W
Multilayer PC Board
20-Pin TSSOP...........................................................+91°C/W
Junction-to-Ambient Thermal Resistance with 500LFPM
Airflow Single-Layer PC board
20-Pin TSSOP...........................................................+96°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP...........................................................+20°C/W
Operating Temperature Range..........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (inputs and outputs).......................±2kV
Lead Temperature (soldering, 10s).................................+300°C
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS
SINGLE-ENDED INPUTS (CLKSEL, EN)Input High
VoltageVIHVCC -
VCC -
VCC -
VCC -
VCC -
VCC -
0.88V
Input Low
VoltageVILVCC -
VCC -
VCC -
VCC -
VCC -
VCC -
1.475V
Input CurrentIINVIH(MAX),
VIL(MAX)-150+50-150+50-150+50µA
DIFFERENTIAL INPUTS (CLK_, CLK_)Differential Input
High VoltageVIHDFigure 1 1.2VCC1.2VCC 1.2VCCV
Differential Input
Low VoltageVILDFigure 1GNDVCC -
0.095GNDVCC -
0.095GNDVCC -
0.095V
Differential Input
VoltageVIDVIHD - VILD0.095VCC0.095VCC0.095VCCV
Input CurrentIIH, IILCLK_, or CLK_ =
VIHD or VILD-60+50-60+50-60+60µA
OUTPUTS (Q_, Q_)Output High
VoltageVOHFigure 11.61.61.6V
Output Low
VoltageVOLFigure 10.90.90.9V
Differential
Output VoltageVODVOH - VOL,
Figure 1250350450250350450250350450mV
MAX9310
1:5 Clock Driver with Selectable VPECL Inputs and LVDS Outputs
DC ELECTRICAL CHARACTERISTICS (continued)(VCC- GND = 2.375V to 2.625V, outputs terminated with 100Ω±1%, unless otherwise noted. Typical values are at VCC- GND = 2.5V,
VIHD= VCC- 1.0V, VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
AC ELECTRICAL CHARACTERISTICS(VCC- GND = 2.375V to 2.625V, outputs terminated with 100Ω±1%, fIN≤1.0GHz, input transition time = 125ps (20% to 80%),
VIHD- VILD= 0.15V to VCC, unless otherwise noted. Typical values are at VCC- GND = 2.5V, VIHD= VCC- 1.0V, VILD= VCC- 1.5V,
unless otherwise noted.) (Notes 1 and 5)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITSChange in VOD
Between
Complementary
Output States
ΔVOD404040mV
Output Offset
VoltageVOS1.1251.251.3751.1251.251.3751.1251.251.375mV
Change in VOS
Between
Complementary
Output States
ΔVOCM252525mV
Q_ shorted to Q_121212
Output Short-
Circuit CurrentIOSCQ_ or Q_ shorted
to GND282828
POWER SUPPLYPower-Supply
CurrentICC(Note 4)427545.57548.575mA
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITSPropagation
Delay CLK_,
CLK_ to Q_, Q_
tPHL,
tPLHFigure 1250335600250345600250345600ps
Output-to-
Output SkewtSKOO(Note 6)1025825525ps
Part-to-Part
SkewtSKPP(Note 7)145145145ps
Added Random
JittertRJ
fIN = 1.0GHz,
clock pattern
(Note 8)
0.41.00.41.00.41.0ps
(RMS)
Added
Deterministic
Jitter
tDJ
fIN = 1.0Gsps,23 - 1 PRBS
pattern (Note 8)5241524152ps
(P-P)
SUPPLY CURRENT vs. TEMPERATUREMAX9310 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
ALL PINS ARE OPEN EXCEPT VCC
AND GND OUTPUTS LOADED WITH 100Ω
DIFFERENTIAL
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL)
vs. FREQUENCYMAX9310 toc02
FREQUENCY (GHz)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
OUTPUT RISE/FALL vs. TEMPERATURE
MAX9310 toc03
TEMPERATURE (°C)
RISE/FALL TIME (ps)3510-15
fIN = 500MHz
Typical Operating Characteristics(VCC- GND = 2.5V, outputs terminated with 100Ω±1%, fIN= 1.0GHz, input transition time = 125ps (20% to 80%),VIHD= VCC- 1.0V,
VILD= VCC- 1.5V, unless otherwise noted.)
MAX9310
1:5 Clock Driver with Selectable
LVPECL Inputs and LVDS Outputs
AC ELECTRICAL CHARACTERISTICS (continued)(VCC- GND = 2.375V to 2.625V, outputs terminated with 100Ω±1%, fIN≤1.0GHz, input transition time = 125ps (20% to 80%),
VIHD- VILD= 0.15V to VCC, unless otherwise noted. Typical values are at VCC- GND = 2.5V, VIHD= VCC- 1.0V, VILD= VCC- 1.5V,
unless otherwise noted.) (Notes 1 and 5)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITSOperating
FrequencyfMAXVOD ≥ 250mV1.01.01.0GHz
Differential
Output Rise/Fall
Time
tR/tF20% to 80%,
Figure 1140205300140205300140205300ps
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:DC parameters are production tested at +25°C. DC limits are guaranteed by design and
characterized over the full operating temperature range.
Note 4:All pins are open except VCCand GND, all outputs are loaded with 100Ωdifferentially.
Note 5:Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6:Measured between outputs of the same part at the signal crossing points for a same-edge
transition.
Note 7:Measured between outputs of different parts at the signal crossing points under identical conditions
for a same-edge transition.
Note 8:Device jitter added to the input signal.
MAX9310
1:5 Clock Driver with Selectable VPECL Inputs and LVDS Outputsypical Operating Characteristics (continued)(VCC- GND = 2.5V, outputs terminated with 100Ω±1%, fIN= 1.0GHz, input transition time = 125ps (20% to 80%),VIHD= VCC- 1.0V,
VILD= VCC- 1.5V, unless otherwise noted.)
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT (VIHD)MAX9310 toc04
VIHD (V)
PROPAGATION DELAY (ps)
PROPAGATION DELAY vs. TEMPERATURE
MAX9310 toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)3510-15
Pin Description
PINNAMEFUNCTIONQ0Noninverting Differential Output 0. Typically terminated with 100Ω to Q0.Q0Inverting Differential Output 0. Typically terminated with 100Ω to Q0.Q1Noninverting Differential Output 1. Typically terminated with 100Ω to Q1.Q1Inverting Differential Output 1. Typically terminated with 100Ω to Q1.Q2Noninverting Differential Output 2. Typically terminated with 100Ω to Q2.Q2Inverting Differential Output 2. Typically terminated with 100Ω to Q2.Q3Noninverting Differential Output 3. Typically terminated with 100Ω to Q3.Q3Inverting Differential Output 3. Typically terminated with 100Ω to Q3.Q4Noninverting Differential Output 4. Typically terminated with 100Ω to Q4.Q4Inverting Differential Output 4. Typically terminated with 100Ω to Q4.GNDGroundCLKSELClock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1,
CLK1 input. Internal 60kΩ pulldown to GND.CLK0Noninverting Differential Clock Input 0. Internal 75kΩ pulldown to GND.CLK0Inverting Differential Clock Input 0. Internal 75kΩ pullup to VCC and 75kΩ pulldown to GND.I.C.Internally Connect. Do not connect externally.CLK1Noninverting Differential Input 1. Internal 75kΩ pulldown to GND.CLK1Inverting Differential Input 1. Internal 75kΩ pullup to VCC and 75kΩ pulldown to GND.
MAX9310
1:5 Clock Driver with Selectable
LVPECL Inputs and LVDS OutputsCLK
CLK
tPLHDtPHLD
VOH - VOL
VIHD - VILD
VIHD
VILD
Q_ - Q_
0V (DIFFERENTIAL)0V (DIFFERENTIAL)
20%
80%
20%
80%tF
VOL
VOH
Figure 1. MAX9310 Timing DiagramtHtS
tPLHD
OUTPUTS ARE LOWOUTPUTS STAY LOW
CLK
CLK
tS = SETUP TIME
tH = HOLD TIME
Pin Description (continued)
PINNAMEFUNCTION18, 20VCC
Positive Supply Voltage. Bypass each VCC to GND with 0.1µF and 0.01µF ceramic capacitors.
Place the capacitors as close to the device as possible with the smaller value capacitor closest
to the device.EN
Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected
clock input when EN is low. Outputs are synchronously driven to a differential low state on the
falling edge of the selected clock input when EN is high. Internal 60kΩ pulldown to GND
(Figure 2).
