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MAX9173EUE+-MAX9173EUE+T
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe19-2595; Rev 0; 10/02
General DescriptionThe MAX9173 quad low-voltage differential signaling
(LVDS) line receiver is ideal for applications requiring
high data rates, low power, and low noise. The
MAX9173 is guaranteed to receive data at speeds up
to 500Mbps (250MHz) over controlled-impedance
media of approximately 100Ω. The transmission media
can be printed circuit (PC) board traces or cables.
The MAX9173 accepts four LVDS differential inputs and
translates them to LVCMOS/LVTTL outputs. The
MAX9173 inputs are high impedance and require an
external termination resistor when used in a point-to-
point connection.
The device supports a wide common-mode input range
of 0.05V to VCC- 0.05V, allowing for ground potential
differences and common-mode noise between the dri-
ver and the receiver. A fail-safe feature sets the output
high when the inputs are open, or when the inputs are
undriven and shorted or undriven and parallel terminat-
ed. The EN and ENinputs control the high-impedance
outputs. The enables are common to all four receivers.
Inputs conform to the ANSI TIA/EIA-644 LVDS stan-
dard. The flow-through pinout simplifies board layout
and reduces crosstalk by separating the LVDS inputs
and LVCMOS/LVTTL outputs. The MAX9173 operates
from a single 3.3V supply, and is specified for opera-
tion from -40°C to +85°C. Refer to the MAX9121/
MAX9122 data sheet for lower jitter quad LVDS
receivers with parallel fail-safe. Refer to the MAX9123
data sheet for a quad LVDS line driver with flow-
through pinout.
The device is available in 16-pin TSSOP, SO, and
space-saving thin QFN packages.
ApplicationsDigital Copiers
Laser Printers
Cellular Phone Base Stations
Network Switches/Routers
Backplane Interconnect
Clock Distribution
LCD Displays
Telecom Switching Equipment
FeaturesAccepts LVDS and LVPECL InputsFully Compatible with DS90LV048ALow 1.0mA (max) Disable Supply CurrentIn-Path Fail-Safe CircuitryFlow-Through Pinout
Simplifies PC Board Layout
Reduces CrosstalkGuaranteed 500Mbps Data Rate400ps Pulse Skew (max)Conforms to ANSI TIA/EIA-644 LVDS StandardHigh-Impedance LVDS Inputs when Powered-OffAvailable in Tiny 3mm x 3mm QFN Package
Pin Configurations and Functional Diagram appear at end of
data sheet.
Ordering Information
PARTTEMP RANGEPIN-PACKAGEMAX9173EUE-40°C to +85°C16 TSSOP
MAX9173ESE-40°C to +85°C16 SO
MAX9173ETE*-40°C to +85°C16 Thin QFN-EP**
*Future product. Contact factory for availability.
**EP = Exposed pad.
MAX9123MAX9173
100Ω
100Ω
100Ω
100Ω
LVDS SIGNALS
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP BOARD TRACES
LVTTL/LVCMOS
DATA INPUTS
LVTTL/LVCMOS
DATA OUTPUTS
ypical Operating Circuit
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND ..........................................................-0.3V to +4.0V
IN_+, IN_- to GND.................................................-0.3V to +4.0V
OUT_, EN, ENto GND................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA = +70°C)
16-Pin TSSOP (derate 9.4mW/°C above TA= +70°C)..755mW
16-Pin SO (derate 8.7mW/°C above TA= +70°C)........696mW
16-Pin QFN (derate 14.7mW/°C above TA= +70°C)..1177mW
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection (Human Body Model, IN_+, IN_-) ............±7.0kV
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 1.2V, common-mode input voltage VCM= |VID/2| to VCC- |VID/2|, outputs
enabled, and TA= -40°C to +85°C. Typical values are at VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, and TA= +25°C, unless otherwise
noted.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High ThresholdVTH-450mV
Differential Input Low ThresholdVTL-100-45mV
Input Current (Noninverting Input)IIN_+Figure 1+0.5-2.5-5µA
Power-Off Input Current
(Noninverting Input)IIN_+OFFVIN_+ = 0 to 3.6V, VIN_- = 0 to 3.6V,
VCC = 0 or open (Figure 1)-0.50+0.5µA
Input Current (Inverting Input)IIN_-Figure 1-0.5+5.0+10µA
Power-Off Input Current
(Inverting Input)IIN_-OFFVIN_+ = 0 to 3.6V, VIN_- = 0 to 3.6V,
VCC = 0 or open, Figure 1-0.50+0.5µA
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
undriven parallel termination2.73.2Output High Voltage (Table 1)VOHIOH = -4.0mA
VID = 02.73.2
Output Low VoltageVOLIOL = +4.0mA, VID = -100mV0.10.25V
Output Short-Circuit CurrentIOSVOUT_ = 0 (Note 3)-45-77-120mA
Output High-Impedance CurrentIOZDisabled, VOUT_ = 0 or VCC-1+1µA
LOGIC INPUTS (EN, EN)
Input High VoltageVIH2.0VCCV
Input Low VoltageVIL00.8V
Input CurrentIINVIN = high or low-15+15µA
Input Clamp VoltageVCLICL = -18mA-0.88-1.5V
POWER SUPPLY
Supply CurrentICCInputs open1215mA
Disabled Supply CurrentICCZDisabled, inputs open0.561.0mA
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 2:Devices are 100% production tested at TA= +25°C and are guaranteed by design for TA= -40°C to +85°C as specified.
Note 3:Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 4:AC parameters are guaranteed by design and characterization.
Note 5:CLincludes scope probe and test jig capacitance.
Note 6:Pulse generator output conditions: tR= tF< 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, VOH= 1.3V, VOL=
1.1V. High-impedance delay pulse generator output conditions: tR = tF <3ns (0% to 100%), frequency = 1MHz, 50% duty
cycle, VOH= 3V and VOL= 0.
Note 7:Propagation delay and differential pulse skew decrease when |VID|is increased from 200mV to 400mV. Skew specifications
apply for 200mV ≤|VID|≤1.2V over the common-mode range VCM= |VID|/2 to VCC- |VID|/2.
Note 8:tSKD1is the magnitude of the difference of differential propagation delays in a channel. tSKD1= |tPHLD- tPLHD|.
Note 9:tSKD2is the magnitude of the difference of the tPLHDor tPHLDof one channel and the tPLHDor tPHLDof any other channel
on the same part.
Note 10:tSKD3is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions
at the same VCCand within 5°C of each other.
Note 11:tSKD4is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions.
Note 12:60% to 40% duty cycle, VOL= 0.4V (max), VOH= 2.7V (min), load = 15pF.
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, and TA= -40°C to +85°C. Typical values are at VCC= 3.3V and TA=
+25°C, unless otherwise noted.) (Notes 4–7)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Differential Propagation Delay
High to LowtPHLDFigures 2 and 31.22.012.7ns
Differential Propagation Delay
Low to HightPLHDFigures 2 and 31.22.072.7ns
Differential Pulse Skew
|tPHLD - tPLHD|tSKD1Figures 2 and 3 (Note 8)60400ps
Differential Channel-to-Channel
SkewtSKD2Figures 2 and 3 (Note 9)100500ps
tSKD3Figures 2 and 3 (Note 10)1Differential Part-to-Part SkewtSKD4Figures 2 and 3 (Note 11)1.5ns
Rise TimetTLHFigures 2 and 30.661.0ns
Fall TimetTHLFigures 2 and 30.621.0ns
Disable Time High to ZtPHZRL = 2kΩ, Figures 4 and 59.514ns
Disable Time Low to ZtPLZRL = 2kΩ, Figures 4 and 59.514ns
Enable Time Z to HightPZHRL = 2kΩ, Figures 4 and 5314ns
Enable Time Z to LowtPZLRL = 2kΩ, Figures 4 and 5314ns
Maximum Operating FrequencyfMAXAll channels switching (Note 12)250MHz
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Typical Operating Characteristics
(VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, f= 100MHz, input rise and fall time = 1ns (0% to 100%), CL= 15pF, and TA= +25°C, unless
otherwise noted.) (Figures 2 and 3)
SUPPLY CURRENT vs. FREQUENCY
MAX9173 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
CL = 15pF
ALL CHANNELS
SWITCHING
ONE CHANNEL
SWITCHING
SUPPLY CURRENT vs. TEMPERATURE
MAX9173 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)35-1510
ALL INPUTS OPEN
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9173 toc03
SUPPLY VOLTAGE (V)
DIFFERENTIAL INPUT THRESHOLD VOLTAGE (mV)
VTH
VTL
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9173 toc04
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
ALL INPUTS OPEN
OUTPUT HIGH-IMPEDANCE CURRENT
vs. SUPPLY VOLTAGE
MAX9173 toc05
SUPPLY VOLTAGE (V)
OUTPUT HIGH-IMPEDANCE CURRENT (nA)
EN = LOW, EN = HIGH, VOUT = 0
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9173 toc06
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
IOH = -4mA
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9173 toc07
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
IOL = 4mA
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9173 toc08
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9173 toc09
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)3510-15
tPLHD
tPHLD
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9173 toc10
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9173 toc11
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
MAX9173 toc12
LOAD (pF)
DIFFERENTIAL PROPAGATION DELAY (ns)3020
tPLHDtPHLD
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9173 toc13
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
tTLH
tTHL
TRANSITION TIME vs. TEMPERATURE
MAX9173 toc14
TEMPERATURE (°C)
TRANSITION TIME (ps)35-1510
tTLH
tTHL
TRANSITION TIME vs. LOAD
MAX9173 toc15
LOAD (pF)
TRANSITION TIME (ps)3020
tTLH
tTHL
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
MAX9173 toc16
SUPPLY VOLTAGE (V)
DIFFERENTIAL PULSE SKEW (ps)
DIFFERENTIAL PULSE SKEW
vs. INPUT TRANSITION TIMEMAX9173 toc17
INPUT TRANSITION TIME (ns)
DIFFERENTIAL PULSE SKEW (ps)
f = 50MHz
Typical Operating Characteristics (continued)(VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, f= 100MHz, input rise and fall time = 1ns (0% to 100%), CL= 15pF, and TA= +25°C, unless
otherwise noted.) (Figures 2 and 3)
MAX9173
Detailed DescriptionLVDS is a signaling method intended for point-to-point
communication over a controlled-impedance medium
as defined by the ANSI TIA/EIA-644 and IEEE 1596.3
standards. LVDS uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI and system susceptibility to noise.
The MAX9173 is a 500Mbps, four-channel LVDS receiv-
er intended for high-speed, point-to-point, low-power
applications. Each channel accepts an LVDS input and
translates it to an LVTTL/LVCMOS output. The receiver
is specified to detect differential signals as low as
100mV and as high as 1.2V within an input voltage
range of 0 to VCC. The 250mV to 400mV differential out-
put of an LVDS driver is nominally centered around a
1.2V offset. This offset, coupled with the receiver’s 0 to
VCCinput voltage range, allows more than ±1V shift in
the signal (as seen by the receiver). This allows for a
difference in ground references of the transmitter and
the receiver, the common-mode effects of coupled
noise, or both.
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
PIN
TSSOP/SOQFNNAMEFUNCTION15IN1-Inverting Differential Receiver Input for Receiver 116IN1+Noninverting Differential Receiver Input for Receiver 11IN2+Noninverting Differential Receiver Input for Receiver 22IN2-Inverting Differential Receiver Input for Receiver 23IN3-Inverting Differential Receiver Input for Receiver 34IN3+Noninverting Differential Receiver Input for Receiver 35IN4+Noninverting Differential Receiver Input for Receiver 46IN4-Inverting Differential Receiver Input for Receiver 4
9, 167, 14EN, EN
Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active.
For other combinations of EN and EN, the outputs are disabled and in high
impedance.8OUT4LVCMOS/LVTTL Receiver Output for Receiver 49OUT3LVCMOS/LVTTL Receiver Output for Receiver 310GNDGround11VCCPower-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
Place the smaller value cap as close to the pin as possible.12OUT2LVCMOS/LVTTL Receiver Output for Receiver 213OUT1LVCMOS/LVTTL Receiver Output for Receiver 1Exposed PadEPExposed Pad. Solder to ground plane for proper heat dissipation.
Pin Description
ENABLESINPUTSOUTPUTEN
(IN_+) - (IN_-)OUT_VID ≥ 0H
VID ≤ -100mVLHL or open
Open, undriven short, or undriven parallel terminationH
All other combinations of ENABLE pinsDon’t careZ
Table 1. Input/Output Function Table
Fail-SafeThe MAX9173 fail-safe drives the receiver output high
when the differential input is:OpenUndriven and shortedUndriven and terminated
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termi-
nation are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termina-
tion still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriv-
en, shorted input can occur due to a shorted cable.
“In-Path” vs. “Parallel” Fail-SafeThe MAX9173 has in-path fail-safe that is compatible
with in-path fail-safe receivers, such as the
DS90LV048A. Refer to the MAX9121/MAX9122 data
sheet for pin-compatible receivers with parallel fail-safe
and lower jitter. Refer to the MAX9130 data sheet for a
single LVDS receiver with parallel fail-safe in an SC70
package.
The MAX9173 with in-path fail-safe is designed with a
+45mV input offset voltage, a 2.5µA current source
between VCCand the noninverting input, and a 5µA
current sink between the inverting input and ground
(Figure 1). If the differential input is open, the 2.5µA
current source pulls the input to approximately VCC-
0.8V and the 5µA current sink pulls the inverting input
to ground, which drives the receiver output high. If the
differential input is shorted or terminated with a typical
value termination resistor, the +45mV offset drives the
receiver output high. If the input is terminated and float-
ing, the receiver output is driven high by the +45mV off-
set, and the 2:1 current sink to current source ratio
(5µA:2.5µA) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multi-
point bus because the change in common-mode volt-
age from ground to the typical driver offset voltage of
1.2V is not as much as the change from VCCto 1.2V
(parallel fail-safe pulls the bus to VCC).
ESD ProtectionESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The receiver inputs of
the MAX9173 have ±7.0kV of protection against static
electricity (per Human Body Model).
Figure 6a shows the Human Body Model, and Figure
6b shows the current waveform it generates when dis-
charged into a low-impedance load. This model con-
sists of a 100pF capacitor charged to the ESD test volt-
age, which is then discharged into the test device
through a 1.5kΩresistor.
Applications Information
Differential TracesInput trace characteristics affect the performance of the
MAX9173. Use controlled-impedance board traces. For
point-to-point connections, match the receiver input ter-
mination resistor to the differential characteristic imped-
ance of the board traces.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Cables and ConnectorsLVDS transmission media typically have controlled dif-
ferential impedance of 100Ω. Use cables and connec-
tors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as coaxial
cable. Balanced cables such as twisted pair offer
superior signal quality and tend to generate less EMI
due to magnetic field canceling effects. Balanced
cables pick up noise as common mode, which is reject-
ed by the LVDS receiver.
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-SafeFigure 1. Input with Fail-Safe Network
VCC
IN_-
IN_+
OUT_
45mV
5μA
2.5μA
