MAX9172ESA-MAX9172ESA+-MAX9172ESA+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX9172ESA+T ,Single/Dual LVDS Line Receivers with "In-Path" Fail-Safeapplications requiring minimum power consumption,♦ Space-Saving 8-Pin TDFN and SOT23 Packagesspace, ..
MAX9173EUE+ ,Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safeapplications requiring♦ Fully Compatible with DS90LV048Ahigh data rates, low power, and low noise. ..
MAX9173EUE+T ,Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-SafeELECTRICAL CHARACTERISTICS(V = 3.0V to 3.6V, differential input voltage |V | = 0.1V to 1.2V, common ..
MAX9174EUB+ ,670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 SplittersApplicationsMAX9174ETB* -40°C to +85°C 10 Thin QFN-EP**Protection SwitchingMAX9175EUB -40°C to +85° ..
MAX9175EUB ,670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splittersfeatures a fail-safe circuit that dri-♦ Low-Power CMOS Designves the outputs high when the input is ..
MAX9175EUB+ ,670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 SplittersELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, R = 100Ω ±1%, PD_ = high, differential input voltage ..
MB88346B ,R-2R TYPE 8-BIT D/A CONVERTER WITH OPERATIONAL AMPLIFIER OUTPUT BUFFERSFUJITSU SEMICONDUCTORDS04-13501-2EDATA SHEETLINEAR ICR-2R TYPE 8-BIT D/A CONVERTER WITHOPERATIONAL ..
MB88346BP ,R-2R type 8-bit D/A converter with operetional amplifier output buffersFEATURESPLASTIC SOP(FPT-20P-M01)• Conversion method : R-2R resistor ladder• 8-bit x 12-channel D/A ..
MB88346BPF ,R-2R type 8-bit D/A converter with operetional amplifier output buffersFUJITSU SEMICONDUCTORDS04-13501-2EDATA SHEETLINEAR ICR-2R TYPE 8-BIT D/A CONVERTER WITHOPERATIONAL ..
MB88346BPFV ,R-2R type 8-bit D/A converter with operetional amplifier output buffersFUJITSU SEMICONDUCTORDS04-13501-2EDATA SHEETLINEAR ICR-2R TYPE 8-BIT D/A CONVERTER WITHOPERATIONAL ..
MB88346L ,D/A Converter for Digital Tuning (12-channel, 8-bit, on-chip OP amp, low-voltage)FUJITSU SEMICONDUCTORDS04-13511-2EDATA SHEETLinear IC ConverterCMOSD/A Converter for Digital Tuni ..
MB88347 ,R-2R TYPE 8-BIT D/A CONVERTER WITH OPERATIONAL AMPLIFIER OUTPUT BUFFERSFUJITSU SEMICONDUCTORDS04-13506-1EDATA SHEETLINEAR ICR-2R TYPE 8-BIT D/A CONVERTER WITHOPERATIONAL ..

MAX9172ESA-MAX9172ESA+-MAX9172ESA+T
Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
General Description
The MAX9171/MAX9172 single/dual low-voltage differential
signaling (LVDS) receivers are designed for high-speed
applications requiring minimum power consumption,
space, and noise. Both devices support switching rates
exceeding 500Mbps while operating from a single 3.3V
supply.
The MAX9171 is a single LVDS receiver and the
MAX9172 is a dual LVDS receiver. Both devices con-
form to the ANSI TIA/EIA-644 LVDS standard and con-
vert LVDS to LVTTL/LVCMOS-compatible outputs. A
fail-safe feature sets the outputs high when the inputs
are undriven and open, terminated, or shorted. The
MAX9171/MAX9172 are available in 8-pin SO packages
and space-saving thin DFN and SOT23 packages.
For lower skew devices, refer to the MAX9111/ MAX9113
data sheet.
Applications
Multipoint Backplane Interconnect
Laser Printers
Digital Copiers
Cellular Phone Base Stations
LCD Displays
Network Switches/Routers
Clock Distribution
FeaturesInput Accepts LVDS and LVPECLIn-Path Fail-Safe CircuitSpace-Saving 8-Pin TDFN and SOT23 PackagesFail-Safe Circuitry Sets Output High for Open,
Undriven Shorted, or Undriven Terminated OutputFlow-Through Pinout Simplifies PCB LayoutGuaranteed 500Mbps Data RateSecond Source to DS90LV018A and DS90LV028A
(SO Packages Only)Conforms to ANSI TIA/EIA-644 Standard3.3V Supply Voltage-40°C to +85°C Operating Temperature RangeLow-Power Dissipation
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Ordering Information
19-2578; Rev 2; 6/07
PARTPIN-PACKAGETOP
MARK
PKG
CODE
MAX9171EKA-T8 SOT23-8AALXK8-1
MAX9171ESA8 SO—S8-2
MAX9171ETA*8 Thin DFN-EP**—T833-2
MAX9172EKA-T8 SOT23-8AALYK8-1
MAX9172ESA8 SO—S8-2
MAX9172ETA*8 Thin DFN-EP**—T833-25
SO/TDFN*
IN-
IN+
N.C.
N.C.GND
N.C.
OUT
VCCIN-
IN+
N.C.N.C.
GND
N.C.OUT
VCCIN1-
IN1+
IN2+
IN2-GND
OUT2
OUT1
VCCIN1-
IN1+
IN2-OUT2
GND
IN2+OUT1
VCC
MAX91715
SO/TDFN*
MAX91725
SOT23
MAX9172
SOT23
MAX9171
Pin Configurations
Note:All devices are specified over the -40°C to +85°C operating
temperature range.
*Future product—contact factory for availability.
**EP = Exposed pad.
T = Tape-and-reel.
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 1.2V, receiver input voltage = 0 to VCC, common-mode voltage VCM=
|VID/2| to (VCC- |VID/2|), TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, |VID| = 0.2V, VCM= 1.2V, = +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND.................................................-0.3V to +4.0V
OUT_ to GND............................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C) ...........714mW
8-Pin SO (derate 5.9mW/°C above +70°C) .................471mW
8-Pin TDFN (derate 24.4mW/°C above +70°C) ........1951mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
ESD Protection
Human Body Model (IN_+, IN_-) ...................................±13kV
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High ThresholdVTHFigure 1-400mV
Differential Input Low ThresholdVTLFigure 1-100-40mV
Input Current (Noninverting Input)IIN+Figure 1+0.5-2.1-5.0µA
Power-Off Input Current
(Noninverting Input)IIN+OFFVIN+ = 0 to 3.6V, VIN- = 0 to 3.6V, VCC = 0
or open (Figure 1)-0.50+0.5µA
Input Current (Inverting Input)IIN-Figure 1-0.5+4.4+10.0µA
Power-Off Input Current
(Inverting Input)IIN-OFFVIN+ = 0 to 3.6V, VIN- = 0 to 3.6V, VCC = 0
or open (Figure 1)-0.50+0.5µA
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
undriven parallel termination2.73.2Output High VoltageVOHIOH = -4.0mA
VID = 0V2.73.2
Output Low VoltageVOLIOL = 4.0mA, VID = -100mV0.10.4V
Output Short-Circuit CurrentIOSVOUT_ = 0 (Note 3)-45-77-120mA
POWER SUPPLY
MAX91713.66Supply CurrentICCInputs openMAX91727.09mA
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to GND
except VTH, VTL, and VID.
Note 2:All devices are 100% production tested at TA= +25°C and are guaranteed by design for TA= -40°C to +85°C, as specified.
Note 3:Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 4:AC parameters are guaranteed by design and not production tested.
Note 5:CLincludes scope probe and test jig capacitance.
Note 6:Pulse generator output conditions: tR= tF< 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, VOH= 1.3V, VOL= 1.1V.
Note 7:tSKD1is the magnitude of the difference of differential propagation delays in a channel. tSKD1= |tPHLD- tPLHD|.
Note 8:tSKD2is the magnitude of the difference of the tPLHDor tPHLDof one channel and the tPLHDor tPHLDof the other channel on
the same part.
Note 9:tSKD3is the magnitude of the difference of any differential propagation delays between parts at the same VCCand within
5°C of each other.
Note 10:tSKD4is the magnitude of the difference of any differential propagation delays between parts operating over the rated
supply and temperature ranges.
SWITCHING CHARACTERISTICS
(VCC= 3.0V to 3.6V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC=
3.3V, TA= +25°C.) (Notes 4, 5, 6)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Differential Propagation Delay
High to LowtPHLDFigures 2, 31.01.652.5ns
Differential Propagation Delay
Low to HightPLHDFigures 2, 31.01.622.5ns
Differential Pulse Skew
|tPHLD - tPLHD|tSKD1Figures 2, 3 (Note 7)30400ps
Differential Channel-to-Channel
Skew (MAX9172)tSKD2Figures 2, 3 (Note 8)40500ps
tSKD3Figures 2, 3 (Note 9)1Differential Part-to-Part SkewtSKD4Figures 2, 3 (Note 10)1.5ns
Rise TimetTLHFigures 2, 30.550.8ns
Fall TimetTHLFigures 2, 30.510.8ns
Maximum Operating FrequencyfMAXAll channels switching, VOL(MAX) = 0.4V,
VOH(MIN) = 2.7V, 40% < duty cycle < 60%250300MHz
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Typical Operating Characteristics
(VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, fIN= 200MHz, CL= 15pF, TA= +25°C, unless otherwise specified.)
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9171 toc01
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
IOH = -4mA
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9171 toc02
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
IOL = +4mA
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9171 toc03
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
VID = +200mV, OUTPUT
SHORTED TO GROUND
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9171 toc04
SUPPLY VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE (mV)
HIGH-LOW
LOW-HIGH
MAX9172 SUPPLY CURRENT
vs. FREQUENCY
MAX9171 toc05
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
BOTH CHANNELS
SWITCHING
ONE CHANNEL
SWITCHING
MAX9172 SUPPLY CURRENT
vs. TEMPERATURE
MAX9171 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
f = 1MHz
BOTH CHANNELS SWITCHING
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9171 toc07
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9171 toc08
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)3510-15
tPHLD
tPLHD
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
MAX9171 toc09
SUPPLY VOLTAGE (V)
DIFFERENTIAL PULSE SKEW (ps)
DIFFERENTIAL PULSE SKEW
vs. TEMPERATURE
MAX9171 toc10
TEMPERATURE (°C)
DIFFERENTIAL PULSE SKEW (ps)3510-15
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9171 toc11
DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY (ns)
fIN = 20MHz
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9171 toc12
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
fIN = 20MHz
tPHLD
tPLHD
TRANSITION TIME vs. TEMPERATURE
MAX9171 toc13
TEMPERATURE (°C)
TRANSITION TIME (ps)3510-15
tTLH
tTHL
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
MAX9171 toc14
LOAD (pF)
DIFFERENTIAL PROPAGATION DELAY (ns)3020
fIN = 20MHz
tPHLD
tPLHD
TRANSITION TIME vs. LOAD
MAX9171 toc15
LOAD (pF)
TRANSITION TIME (ps)3020
tTLH
tTHL
DIFFERENTIAL PULSE SKEW
vs. INPUT TRANSITION TIME
MAX9171 toc16
INPUT TRANSITION TIME (ns)
DIFFERENTIAL PULSE SKEW (ps)
1.03.0ypical Operating Characteristics (continued)
(VCC= 3.3V, VCM= 1.2V, |VID| = 0.2V, fIN= 200MHz, CL= 15pF, TA= +25°C, unless otherwise specified.)
MAX9171/MAX9172
Detailed Description
LVDS Inputs
The MAX9171/MAX9172 feature LVDS inputs for inter-
facing high-speed digital circuitry. The LVDS interface
standard is a signaling method intended for point-to-
point communication over controlled-impedance
media, as defined by the ANSI TIA/EIA-644 standards.
The technology uses low-voltage signals to achieve fast
transition times and minimize power dissipation and
noise immunity. The MAX9171/MAX9172 convert LVDS
signals to LVCMOS/LVTTL signals at rates in excess of
500Mbps. These devices are capable of detecting dif-
ferential signals as low as 100mV and as high as 1.2V
within a 0 to VCCinput voltage range. Table 1 is the
input-output function table.
Fail-Safe
The MAX9171/MAX9172 fail-safe drives the receiver
output high when the differential input is:OpenUndriven and shortedUndriven and terminated
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termi-
nation are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termina-
tion still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriv-
en, shorted input can occur due to a shorted cable.
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
MAX9171 Pin Description
PIN
SOT23SO/TDFNNAMEFUNCTIONVCCPositive Power-Supply Input. Bypass with a 0.1µF and a 0.001µF capacitor to GND with the
smallest capacitor closest to the pin.5GNDGround7OUTReceiver Output
4, 5, 63, 4, 6N.C.No Connection. Not internally connected.2IN+Noninverting Differential Receiver Input1IN-Inverting Differential Receiver Input( TD FN onl y) EPExposed Paddle. Solder to PCB ground.
MAX9172 Pin Description
PIN
SOT23SO/TDFNNAMEFUNCTIONVCCPositive Power-Supply Input. Bypass with a 0.1µF and a 0.001µF capacitor to GND with the
smallest capacitor closest to the pin.5GNDGround7OUT1Receiver Output 16OUT2Receiver Output 24IN2-Inverting Differential Receiver Input 23IN2+Noninverting Differential Receiver Input 22IN1+Noninverting Differential Receiver Input 11IN1-Inverting Differential Receiver Input 1( TD FN onl y) EPExposed Paddle. Solder to PCB ground.
INPUTSOUTPUT
(IN_+) - (IN_-)OUT_
≥ 0mVHigh
≤ -100mVLow
OpenHigh
Undriven shortHigh
Undriven parallel terminationHigh
Table 1. Input-Output Function Table

Partno	Mfg	Dc	Qty	Available	Descript
MAX9172ESA	MAXIM	N/a	2372	avai	Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
MAX9172ESA+ \|MAX9172ESA	MAXIM	N/a	2400	avai	Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
MAX9172ESA+T	MAXIM	N/a	7500	avai	Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe