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MAX9159ESA
Dual LVDS Line Receiver
General DescriptionThe MAX9159 dual low-voltage differential signaling
(LVDS) receiver is ideal for applications requiring high
speed, low power, and low noise. The MAX9159 is pin
compatible with the SN65LVDS9637. The MAX9159
conforms to the ANSI TIA/EIA-644 LVDS standard and
converts LVDS to LVTTL-compatible outputs. A fail-safe
feature sets the output high when the inputs are undriv-
en and open, terminated, or shorted. The MAX9159 is
available in an 8-pin SO package and fully specified for
the -40°C to +85°C extended temperature range.
Refer to the MAX9111/MAX9113 data sheet for higher
performance single/dual LVDS line receivers in SOT23
and SO packages. Refer to the MAX9110/MAX9112
data sheet for single/dual LVDS line drivers in SOT23
and SO packages.
ApplicationsNetwork Switches/Routers
Telecom Switching Equipment
Cellular Phone Base Stations
Digital Copiers
LCD Displays
Backplane Interconnect
Clock Distribution
FeaturesPin Compatible with SN65LVDS9637Fail-Safe Circuit Sets Output High for Undriven
InputsConforms to ANSI TIA/EIA-644 StandardSingle 3.3V SupplyDesigned for Data Rates up to 400Mbps±100mV (max) Differential Input Threshold2.2ns (typ) Propagation Delay41mW (typ) Power Dissipation per Receiver at
200MHz±8kV ESD Protection for LVDS InputsLow-Voltage TTL (LVTTL) Logic Output Levels
MAX9159
Dual LVDS Line Receiver
Ordering Information
Typical Operating Circuit19-2274; Rev 0; 1/02
Pin Configuration
MAX9159
Dual LVDS Line Receiver
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 0.6V, common-mode input voltage VCM= |VID/2| to 2.4V - |VID/2|, TA=
-40°C to +85°C. Typical values are at VCC= 3.3V, TA= +25°C, unless otherwise noted.) (Notes 1 and 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND..............................................................-0.5V to +4V
1A, 1B, 2A, 2B to GND ............................................-0.5V to +4V
Y1, Y2 to GND............................................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation................................(TA= +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection LVDS Inputs (1A, 1B, 2A, 2B)
Human Body Model........................................................±8kV
Lead Temperature (soldering, 10s).................................+300°C
MAX9159
Dual LVDS Line Receiver
Note 1:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except VTH, VTL, and VID.
Note 3:AC parameters are guaranteed by design and characterization.
Note 4:CLincludes scope probe and test jig capacitance.
Note 5:All input pulses are supplied by a generator having the following characteristics: tRor tF≤1ns, pulse repetition rate (PRR) =
50Mpps, pulse width = 10 ±0.2ns.
Note 6:tSK(O)is the skew between specified outputs of a single device with all driving inputs connected together and the outputs
switching in the same direction while driving identical specified loads.
Note 7:tSK(PP)is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits.
SWITCHING CHARACTERISTICS(VCC= 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 0.6V, common-mode input voltage VCM= |VID/2| to 2.4V - |VID/2|, CL=
10pF, TA= -40°C to +85°C. Typical values are at VCC= 3.3V, TA= +25°C, unless otherwise noted.) (Figures 2 and 3) (Notes 3, 4,
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9159 toc01
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9159 toc02
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
OUTPUT SHORT-CIRCUIT
CURRENT vs. SUPPLY VOLTAGE
MAX9159 toc03
SUPPLY VOLTAGE (V)
SHORT-CIRCUIT CURRENT (mA)
Typical Operating Characteristics(VCC= 3.3V, |VID| = 200mV, VCM= 1.2V, fIN= 200MHz, CL= 10pF, TA= +25°C, unless otherwise noted.)
MAX9159
Dual LVDS Line ReceiverPULSE SKEW vs. TEMPERATURE
MAX9159 toc10
TEMPERATURE (°C)
PULSE SKEW (ps)
PROPAGATION DELAY vs. DIFFERENTIAL
INPUT VOLTAGE
MAX9159 toc11
DIFFERENTIAL INPUT VOLTAGE (mV)
PROPAGATION DELAY (ns)
PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9159 toc12
COMMON-MODE VOLTAGE (V)
PROPAGATION DELAY (ns)1.01.50.52.02.53.0
DIFFERENTIAL INPUT THRESHOLD
VOLTAGE vs. SUPPLY VOLTAGE
MAX9159 toc04
SUPPLY VOLTAGE (V)
DIFFERENTIAL INPUT THRESHOLD (mV)
SUPPLY CURRENT vs. FREQUENCY
MAX9159 toc05
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
MAX9159 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9159 toc07
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
PROPAGATION DELAY vs. TEMPERATURE
MAX9159 toc08
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
PULSE SKEW vs. SUPPLY VOLTAGE
MAX9159 toc09
SUPPLY VOLTAGE (V)
PULSE SKEW (ps)
Typical Operating Characteristics (continued)
(VCC= 3.3V, |VID| = 200mV, VCM= 1.2V, fIN= 200MHz, CL= 10pF, TA= +25°C, unless otherwise noted.)
MAX9159
Dual LVDS Line ReceiverTRANSITION TIME vs. TEMPERATURE
MAX9159 toc13
TEMPERATURE (°C)
TRANSITION TIME (ns)
PROPAGATION DELAY
vs. LOAD CAPACITANCE
MAX9159 toc14
LOAD CAPACITANCE (pF)
PROPAGATION DELAY (ns)
TRANSITION TIME
vs. LOAD CAPACITANCE
MAX9159 toc15
LOAD CAPACITANCE (pF)
TRANSITION TIME (ns)
ypical Operating Characteristics (continued)(VCC= 3.3V, |VID| = 200mV, VCM= 1.2V, fIN= 200MHz, CL= 10pF, TA= +25°C, unless otherwise noted.)
Detailed DescriptionLVDS is intended for point-to-point communication over
a controlled-impedance medium as defined by the
ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS
uses a lower voltage swing than other common commu-
nication standards, achieving higher data rates with
reduced power consumption, while reducing EMI
emissions and system susceptibility to noise.
The MAX9159 is a dual LVDS line receiver ideal for
applications requiring high data rates, low power, and
low noise. The device accepts an LVDS input and
translates it to an LVTTL output. The receiver detects
differential signals as low as 100mV and as high as
0.6V within an input voltage range of 0 to 2.4V.
The 250mV to 450mV differential output of an LVDS dri-
ver is nominally centered around a 1.25V offset. This
offset, coupled with the receiver’s 0 to 2.4V input volt-
age range, allows an approximate ±1V shift in the sig-
nal (as seen by the receiver). This allows for a
difference in ground references of the driver and the
receiver, the common-mode effects of coupled noise,
or both. The LVDS standards specify an input voltage
range of 0 to 2.4V referenced to receiver ground.
Fail-SafeThe fail-safe feature of the MAX9159 sets the output
high and reduces supply current when:Inputs are open.Inputs are undriven and shorted.Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the input may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when an LVDS driver output is in high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to VCC- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage is
less than VCC- 0.3V and the fail-safe circuit is not acti-
MAX9159
Dual LVDS Line Receivervated. If the inputs are open or if the inputs are undriven
and shorted or undriven and parallel terminated, there is
no input current. In this case, a pullup resistor in the fail-
safe circuit pulls both inputs above VCC- 0.3V, activating
the fail-safe circuit and forcing the output high.
Applications Information
Power-Supply BypassingBypass VCCwith high-frequency surface-mount ceram-
ic 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smaller value capacitor
closest to the device.
Differential TracesInput trace characteristics affect the performance of the
MAX9159. Use controlled-impedance PC board traces,
typically 100Ω. Match the termination resistor to this
characteristic impedance. Eliminate reflections and
ensure that noise couples as common mode by running
the differential traces close together. Reduce skew by
matching the electrical length of the traces. Excessive
skew can result in a degradation of magnetic field can-
cellation. Input differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Cables and ConnectorsTransmission media should typically have a controlled
differential impedance of 100Ω. Use cables and con-
nectors that have matched differential impedance to
minimize impedance discontinuities. Avoid the use of
unbalanced cables such as ribbon or simple coaxial
cable. Balanced cables such as twisted pair offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
LVDS receiver.
TerminationIn point-to-point connections, the MAX9159 requires an
external termination resistor. The termination resistor
should match the differential impedance of the transmis-
sion line. Termination resistance is typically 100Ω, but
may range between 90Ωto 132Ω, depending on the
characteristic impedance of the transmission medium.
When using the MAX9159, minimize the distance
between the input termination resistor and the
MAX9159 inputs. Use 1% surface-mount resistors.
Board LayoutFor LVDS applications, use a four-layer PC board with
separate layers for power, ground, and input/output. To
minimize crosstalk, do not run the output in parallel with
the inputs.
Chip InformationTRANSISTOR COUNT: 461
PROCESS: CMOS
Figure 1. Input Fail-Safe Network
Figure 2. Propagation Delay and Transition-Time Test Circuit
Figure 3. Propagation Delay and Transition-Time Waveforms
