MAX9152ESE+ ,800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switchapplications requiring high speed, low power, and low-2 x 2 Crosspoint Switchnoise signal distribut ..
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MAX9152EUE+ ,800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint SwitchELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, NC/RSEL = open for R = 75Ω ±1%, NC/RSEL = high for R ..
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MAX9152ESE+-MAX9152ESE+T-MAX9152EUE+
800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch
General DescriptionThe MAX9152 2 x 2 crosspoint switch is designed for
applications requiring high speed, low power, and low-
noise signal distribution. This device includes two
LVDS/LVPECL inputs, two LVDS outputs, and two logic
inputs that set the internal connections between differ-
ential inputs and outputs.
The MAX9152 can be programmed to connect any
input to either or both outputs, allowing it to be used in
the following configurations: 2 ✕2 crosspoint switch, 2:1
mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexi-
bility makes the MAX9152 ideal for protection switching
in fault-tolerant systems, loopback switching for diag-
nostics, fanout buffering for clock/data distribution, and
signal regeneration for communication over extended
distances.
Ultra-low 120psPK-PK(max) PRBS jitter ensures reliable
communications in high-speed links that are highly sen-
sitive to timing error, especially those incorporating
clock-and-data recovery, or serializers and deserializ-
ers. The high-speed switching performance guarantees
an 800Mbps data rate and less than 50ps (max) skew
between channels.
LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS inputs are
designed to also accept LVPECL signals directly, and
PECL signals with an attenuation network. The LVDS
outputs are designed to drive 75Ωor 100Ωloads, and
feature a selectable differential output resistance to
minimize reflections.
The MAX9152 is available in 16-pin TSSOP and SO
packages, and consumes only 109mW while operating
from a single +3.3V supply over the -40°C to +85°C
temperature range.
ApplicationsCell Phone Base Stations
Add/Drop Muxes
Digital Crossconnects
DSLAMs
Network Switches/Routers
Protection Switching
Loopback Diagnostics
Clock/Data Distribution
Cable Repeaters
FeaturesPin-Programmable Configuration
2 x 2 Crosspoint Switch
2:1 Mux
1:2 Demux
1:2 Splitter
Dual RepeaterUltra-Low 120psPK-PK(max) Jitter with 800Mbps,
PRBS = 223-1 Data Pattern Low 50ps (max) Channel-to-Channel Skew109mW Power DissipationCompatible with ANSI TIA/EIA-644 LVDS StandardInputs Accept LVDS/LVPECL SignalsLVDS Output Rated for 75Ωand 100ΩLoadsPin-Programmable Differential Output ResistancePin-Compatible Upgrade to DS90CP22
(SO Package)Available in 16-Pin TSSOP Package
(Half the Size of SO)
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch19-2003; Rev 0; 4/01
EN0
SEL0
IN0+
IN0-
IN1+
IN1-
MAX915201
EN1
SEL1
OUT1-OUT1+OUT0-OUT0+
Functional Diagram
PARTTEMP. RANGEPIN-PACKAGEMAX9152ESE-40°C to +85°C16 SO
MAX9152EUE-40°C to +85°C16 TSSOP
Ordering Information
Pin Configuration appears at end of data sheet.
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω±1%, NC/RSEL = high for RL= 100Ω±1%, differential input voltage |VID| =
0.1V to VCC, input voltage (VIN+, VIN-) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA= -40°C to +85°C. Typical values at
VCC= +3.3V, |VID| = 0.2V, input common-mode voltage VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_-, OUT_+, OUT_- to GND.......................-0.3V to +4.0V
EN_, SEL_, NC/RSEL to GND.....................-0.3V to (VCC+ 0.3V)
Short-Circuit Duration (OUT_+, OUT_-).....................Continuous
Continuous Power Dissipation (TA= +70°C)
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection
Human Body Model, IN_+, IN_-, OUT_+, OUT_-...........±7kV
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVCMOS/LVTTL INPUTS (EN_, SEL_)Input High VoltageVIH2.0VCCV
Input Low VoltageVILGND0.8V
Input High CurrentIIHVIN = VCC or 2.0V020μA
Input Low CurrentIILVIN = 0 or 0.8V-1010μA
NC/RSEL INPUTInput High VoltageVIH2.0VCCV
Input Low VoltageVILGND0.8V
Input High CurrentIIHVIN = VCC or 2.0V020μA
Input Low CurrentIILVIN = 0 or 0.8V-1010μA
DIFFERENTIAL INPUTS (IN_+, IN_-)Differential Input High ThresholdVTH100mV
Differential Input Low ThresholdVTL-100mV
VIN+ = VCC or 0, VIN- = VCC or 0-11
Input CurrentIIN+, IIN-V I N + = 3. 6 V o r 0 , V I N - = 3 . 6 V or 0 , C C = 0 -11μA
LVDS OUTPUTS (OUT_+, OUT_-)NC/RSEL = low or open6090118Differential Output Impedance
(Note 2)RDIFFNC/RSEL = high85122155Ω
RL = 75Ω, NC/RSEL = open, Figure 1Differential Output VoltageVODRL = 100Ω, NC/RSEL = high, Figure 1280382470mV
RL = 75Ω, NC/RSEL = open, Figure 1Change in Magnitude of VOD
Between Complementary Output
States
ΔVOD
RL = 100Ω, NC/RSEL = high, Figure 1mV
RL = 75Ω, NC/RSEL = open, Figure 1Offset Common-Mode VoltageVOSRL = 100Ω, NC/RSEL = high, Figure 11.1501.430V
RL = 75Ω, NC/RSEL = open, Figure 1Change in Magnitude of VOS
Between Complementary Output
States
ΔVOS
RL = 100Ω, NC/RSEL = high, Figure 1mV
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint SwitchELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω±1%, NC/RSEL = high for RL= 100Ω±1%, differential input voltage |VID| =
0.1V to VCC, input voltage (VIN+, VIN-) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA= -40°C to +85°C. Typical values at
VCC= +3.3V, |VID| = 0.2V, input common-mode voltage VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω±1%, NC/RSEL = high for RL= 100Ω±1%, CL= 5pF, differential input voltage
|VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage
(VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA= -40°C to +85°C. Typical values
at VCC= +3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVID = +100mV, VOUT_+ = 0, other output
openOutput Short-Circuit CurrentIOS
VID = -100mV, VOUT_- = 0,
other output open
-12-20mA
VID = +100mV, VOUT_+ = 0, VOUT_- = 0Both Output Short-Circuit CurrentIOSBVID = -100mV, VOUT_+ = 0, VOUT_- = 0-12-20mA
Output High-Z CurrentIOZ+, IOZ-Disabled, VOUT_+ = VCC or 0,
VOUT_- = VCC or 0-11μA
Power-Off Output CurrentIOFF+, IOFF-VCC = 0, VOUT_+ = 3.6V or 0,
VOUT_- = 3.6V or 0-11μA
SUPPLY CURRENTRL = 75Ω, CL = 5pF, enabled, quiescent,
Figure 53855
RL = 100Ω, CL = 5pF, enabled, quiescent,
Figure 53350
RL = 75Ω, CL = 5pF, enabled, switching
at 400MHz (800Mbps), Figure 5 (Note 2)5870
Supply CurrentICC
RL = 100Ω, CL = 5pF, enabled, switching
at 400MHz (800Mbps), Figure 5 (Note 2)5265
High-Z Supply CurrentICCZDisabled1525mA
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput to SEL Setup Time (Note 5)tSETFigures 2, 30.4ns
Input to SEL Hold Time (Note 5)tHOLDFigures 2, 30.6ns
SEL to Switched OutputtSWITCHFigures 2, 31.82.53.5ns
Disable Time High to ZtPHZFigure 43.8ns
Disable Time Low to ZtPLZFigure 43.8ns
Enable Time Z to HightPZHFigure 43.2ns
Enable Time Z to LowtPZLFigure 43.2ns
Figures 5, 61.72.33.4Propagation Low-to-High DelaytPLHDVCC = +3.3V, TA = +25°C; Figures 5, 62.02.32.9ns
Figures 5, 61.72.33.4Propagation High-to-Low DelaytPHLDVCC = +3.3V, TA = +25°C; Figures 5, 62.02.32.9ns
DIFFERENTIAL OUTPUT EYE PATTERN
IN 1:2 SPLITTER MODE AT 800MbpsCONDITIONS: 3.3V, PRBS = 223 -1 DATA PATTERN,
|VID| = 200mV, VCM = +1.2V
HORIZONTAL SCALE = 200ps/div
VERTICAL SCALE = 100mV/div
MAX9152 toc01
DIFFERENTIAL
OUTPUT VOLTAGE vs. LOAD
MAX9152 toc02
LOAD RESISTOR (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
NC/RSEL = LOW OR OPEN
NC/RSEL = HIGH
SUPPLY CURRENT vs. DATA RATE
MAX9152 toc03
DATA RATE (Mbps)
SUPPLY CURRENT (mA)
Typical Operating Characteristics(VCC= +3.3V, RL= 100Ω, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID= 200mV, PRBS = 223- 1 data
pattern, VCM= +1.2V, TA= +25°C, unless otherwise noted.)
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPulse Skew |tPLHD -tPHLD| (Note 6)tSKEWFigures 5, 62590ps
Output Channel-to-Channel SkewtCCSFigures 5, 72050ps
Output Low-to-High Transition
Time (20% to 80%)tLHTFigures 5, 6160270480ps
Output High-to-Low Transition
Time (20% to 80%)tHLTFigures 5, 6160270480ps
VID = 200mV, VCM = 1.2V, 50% duty
cycle, 800Mbps, input transition time =
600ps (20% to 80%)30
LVDS Data Path Peak-to-Peak
Jitter (Note 7)tJIT
VID = 200mV, VCM = 1.2V, PRBS = 223 - 1
data pattern, 800Mbps, input transition
time = 600ps (20% to 80%)120
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, NC/RSEL = open for RL= 75Ω±1%, NC/RSEL = high for RL= 100Ω±1%, CL= 5pF, differential input voltage
|VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage
(VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA= -40°C to +85°C. Typical values
at VCC= +3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VOD, and ΔVOD.
Note 2:Guaranteed by design and characterization, not production tested.
Note 3:AC parameters are guaranteed by design and characterization.
Note 4:CLincludes scope probe and test jig capacitance.
Note 5:tSETand tHOLDtime specify that data must be in a stable state before and after the SEL transition.
Note 6:tSKEWis the magnitude difference of differential propagation delay over rated conditions; tSKEW= |tPHLD- tPLHD|.
Note 7:Specification includes test equipment jitter.
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint SwitchPEAK-TO-PEAK OUTPUT JITTER
AT VCM = VID/2 vs. DATA RATE
MAX9152 toc04
DATA RATE (Mbps)
PEAK-TO-PEAK JITTER (ps)VID = 0.8V
VID = 0.4V
VID = 0.2V
PEAK-TO-PEAK OUTPUT JITTER
AT VCM = +1.2V vs. DATA RATE
MAX9152 toc05
DATA RATE (Mbps)
PEAK-TO-PEAK JITTER (ps)
VID = 0.8V
VID = 0.4V
VID = 0.2V
PEAK-TO-PEAK OUTPUT JITTER
AT VCM = +3.3V - (VID/2) vs. DATA RATE
MAX9152 toc06
DATA RATE (Mbps)
PEAK-TO-PEAK JITTER (ps)
VID = 0.8V
VID = 0.2V
VID = 0.4V
PEAK-TO-PEAK OUTPUT JITTER
AT VCM = +0.4V vs. DATA RATE
MAX9152 toc07
DATA RATE (Mbps)
PEAK-TO-PEAK JITTER (ps)
VID = 0.8V
VID = 0.4V
VID = 0.2V
PEAK-TO-PEAK OUTPUT JITTER
AT VCM = +1.6V vs. DATA RATE
MAX9152 toc08
DATA RATE (Mbps)
PEAK-TO-PEAK JITTER (ps)
VID = 0.8V
VID = 0.4V
VID = 0.2V
Typical Operating Characteristics (continued)(VCC= +3.3V, RL= 100Ω, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID= 200mV, PRBS = 223- 1 data
pattern, VCM= +1.2V, TA= +25°C, unless otherwise noted.)
Detailed DescriptionThe LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a
lower voltage swing than other common communication
standards, achieving higher data rates with reduced
power consumption while reducing EMI emissions and
system susceptibility to noise.
The MAX9152 is an 800Mbps 2 x 2 crosspoint switch
designed for high-speed, low-power point-to-point and
multidrop interfaces. The device accepts LVDS or dif-
ferential LVPECL signals and routes them to outputs
depending on the selected mode of operation.
A differential input with a magnitude of 0.1V to VCCwith
single-ended voltage levels at or within the MAX9152's
VCCand ground switches the output. A differential input
with a magnitude of at least 0.15V with single-ended volt-
age levels at or within the MAX9152's VCCand ground is
required to meet the AC specifications.
In the 1:2 splitter mode, the outputs repeat the selected
input. This is useful for distributing a signal or creating
a copy for use in protection switching. In the repeater
mode, the device operates as a two-channel buffer.
Repeating restores signal amplitude, allowing isolation
of media segments or longer media drive. The device is
a crosspoint switch where any input can be connected
to any output or outputs. In 2:1 mux mode, primary and
backup signals can be selected to provide a protec-
tion-switched, fault-tolerant application.
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
Pin Description
PINNAMEFUNCTION1, 2SEL1, SEL0LVCMOS/LVTTL Logic Inputs. Allow the switch to be configured as a mux, repeater, or splitter.
3, 4IN0+, IN0-LVDS/LVPECL Differential Input 0
5VCCPower-Supply Input. Bypass VCC to GND with 0.1μF and 0.001μF ceramic capacitors.
6, 7IN1+, IN1-LVDS/LVPECL Differential Input 1NC/RSELLogic Input. Selects differential output resistance. Set NC/RSEL to open or low when RL = 75Ω,
set to high when RL = 100Ω.NCNo Connect
10, 11OUT1-,
OUT1+LVDS Differential Output 1GNDGround
13, 14OUT0-,
OUT0+LVDS Differential Output 0
15, 16EN1, EN0
LVCMOS/LVTTL Logic Inputs. Enables or disables the outputs. Setting EN0 or EN1 high
enables the corresponding output, OUT0 or OUT1. Setting EN0 or EN1 low puts the
corresponding output into high impedance (differential output resistance is also high
impedance).
1/2 MAX9152
ENABLED
OUT_+
OUT_-
ΔVOD = VOD - VOD*
ΔVOS = VOS - VOS*
VOD AND VOS ARE MEASURED WITH VID = +100mV.
VOD* AND VOS* ARE MEASURED WITH VID = -100mV.
VID = (VIN_+) - (VIN_-)
RL/2
RL/2
IN_+
IN_-
VOSVOD
Figure 1. Test Circuit for VODand VOS
