MAX9130EXT+T Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX9130EXT+T
Single 500Mbps LVDS Line Receiver in SC70
General Description
The MAX9130 is a single low-voltage differential signal-
ing (LVDS) line receiver ideal for applications requiring
high data rates, low power, and low noise. The device
is guaranteed to receive data at speeds up to 500Mbps
(250MHz).
The MAX9130 accepts an LVDS differential input and
translates it to an LVTTL/LVCMOS output. The fail-safe
feature sets the output high when the inputs are undriv-
en and open, terminated, or shorted. The device sup-
ports a wide common-mode input range, allowing a
ground potential difference and common-mode noise
between the driver and the receiver. The MAX9130
conforms to the ANSI/TIA/EIA-644 LVDS standard.
The MAX9130 operates from a single +3.3V supply,
and is specified for operation from -40°C to +85°C. It is
available in a space-saving 6-pin SC70 package. Refer
to the MAX9110/MAX9112 data sheet for single/dual
LVDS line drivers. Refer to the MAX9115 for a lower
speed (200Mbps) single LVDS line receiver in SC70.
Applications
Clock Distribution
Cellular Phone Base Stations
Digital Cross-Connects
Network Switches/Routers
DSLAMs
FeaturesSpace-Saving SC70 Package (50% Smaller than
SOT23)Guaranteed 500Mbps Data RateLow 250ps (max) Pulse SkewHigh-Impedance LVDS Inputs When Powered Off
Allow Hot SwappingConforms to ANSI TIA/EIA-644 LVDS StandardSingle +3.3V SupplyFail-Safe Circuit Sets Output High for Undriven
Inputs (Open, Terminated, or Shorted)Low 150µA (typ) Supply Current in Fail-Safe Mode
MAX9130
Single 500Mbps LVDS Line Receiver in SC70
Ordering Information
19-2155; Rev 0; 10/01
PARTTEMP.
RANGE
PIN-
PACKAGE
TOP
MARK
MAX9130EXT-T-40°C to +85°C6 SC70-6ABB
MAX9130
CLOCK
INPUT
CLOCK
SOURCE
CLOCK
INPUT
CLOCK
INPUT
MAX9130
LVDS SIGNALS
REFERENCE CLOCK DISTRIBUTION
USING MAX9130 IN A MULTIDROP CONFIGURATION
MAX9130
100Ω
TERMINATION
Typical Application Circuit
GND
IN+IN-
OUTVCC
MAX9130
SC70
TOP VIEW
GND
Pin Configuration
MAX9130
Single 500Mbps LVDS Line Receiver in SC70
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, differential input voltage |VID| = 0.05V to 1.0V, input common voltage VCM= |VID/2| to 2.4V - |VID/2|, = -40°C to +85°C, unless otherwise noted. Typical values at VCC= +3.3V, TA= +25°C.) (Notes 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:Package leads soldered to a PC board having copper ground and VCCplanes. Do not exceed Maximum Junction Temperature.
VCCto GND...........................................................-0.3V to +4.0V
IN+, IN- to GND.....................................................-0.3V to +4.0V
OUT to GND...............................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
6-Pin SC70 (derate 3.1mW/°C above +70°C).............245 mW
Output Short to GND (OUT) (Note 1)........................................1s
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
ESD Protection
Human Body Model (IN+, IN-).........................................±6kV
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUTS (IN+, IN-)
Differential Input High ThresholdVTH50mV
Differential Input Low ThresholdVTL-50mV
0.05V ≤VID≤ 0.6V-2020Input CurrentIIN+, IIN-0.6V <VID≤ 1.0V-2525μA
0.05V ≤VID≤ 0.6V, VCC = 0-2020Power-Off Input CurrentIINO0.6V <VID≤ 1.0V, VCC = 0-2525μA
RIN1VCC = +3.6V or 0, Figure 135Input ResistanceRIN2VCC = +3.6V or 0, Figure 1132kΩ
LVTTL/LVCMOS OUTPUT (OUT)
Inp uts op en or und r i ven shor t
or und r i ven 100Ω ter m i nati onVCC - 0.3Output High VoltageVOHIOH = - 8.0m A
VID = +50mVVCC - 0.3
V
Output Low VoltageVOLIOL = +8.0mA, VID = -50mV0.25 V
Output Short-Circuit CurrentIOSVID = +50mV, VOUT = 0-125 mA
SUPPLY CURRENT
No load, inputs undriven (fail-safe)150300μASupply CurrentICCNo load, inputs driven7 mA
MAX9130
Single 500Mbps LVDS Line Receiver in SC70
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, CL= 15pF, differential input voltage |VID| = 0.15V to 1.0V, input common voltage VCM= |VID/2| to 2.4V - |VID
/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 250MHz, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues at VCC= +3.3V, |VID| = 0.2V, VCM= 1.2V, TA= +25°C.) (Figures 2 and 3) (Notes 4 and 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Differential Propagation Delay
High to LowtPHLD 1.2 1.8 3ns
Differential Propagation Delay
Low to HightPLHD 1.2 1.8 3ns
Differential Pulse Skew
|tPHLD - tPLHD| (Note 6)tSKD1 250ps
Differential Part-to-Part Skew
(Note 7)tSKD2 1.3ns
Differential Part-to-Part Skew
(Note 8)tSKD3 1.8ns
Rise TimetTLH 0.5 0.8ns
Fall TimetTHL 0.5 0.8ns
Maximum Operating Frequency
(Note 9)fMAX 250MHz
Note 2:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 4:AC parameters are guaranteed by design and characterization.
Note 5:CLincludes scope probe and test jig capacitance.
Note 6:tSKD1is the magnitude difference of differential propagation delays. tSKD1= |tPHLD- tPLHD|.
Note 7:tSKD2is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCCand within 5°C of each other.
Note 8:tSKD3is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 9:fMAXpulse generator output conditions: rise time = fall time = 1ns (0% to 100%), 50% duty cycle, VOH= +1.3V, VOL= +1.1V.
MAX9130 output criteria: 60% to 40% duty cycle, VOL= 0.25V max, VOH= 2.7V min, load = 15pF.
MAX9130
Single 500Mbps LVDS Line Receiver in SC70
Typical Operating Characteristics
(VCC= +3.3V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 250MHz, 50%
duty cycle, TA= +25°C, unless otherwise noted.) 101001000
SUPPLY CURRENT
vs. FREQUENCY
MAX9130 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
MAX9130 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9130 toc03
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9130 toc04
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9130 toc05
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9130 toc06
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9130 toc07
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
MAX9130
Single 500Mbps LVDS Line Receiver in SC70
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
MAX9130 toc08
SUPPLY VOLTAGE (V)
DIFFERENTIAL PULSE SKEW (ps)
DIFFERENTIAL PULSE SKEW
vs. TEMPERATURE
MAX9130 toc09
TEMPERATURE (°C)
DIFFERENTIAL PULSE SKEW (ps)
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9130 toc10
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9130 toc11
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
TRANSITION TIME
vs. LOAD CAPACITANCE
MAX9130 toc12
LOAD CAPACITANCE (pF)
TRANSITION TIME (ns)
tTLH
tTHL
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9130 toc13
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
tTHL
tTLH
Typical Operating Characteristics (continued)
(VCC= +3.3V, CL= 15pF, |VID| = 0.2V, VCM= 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 250MHz, 50%
duty cycle, TA= +25°C, unless otherwise noted.)
MAX9130
Detailed Description
LVDS is intended for point-to-point communication over
a controlled-impedance medium as defined by the
ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS
uses a lower voltage swing than other common com-
munication standards, achieving higher data rates with
reduced power consumption while reducing EMI emis-
sions and system susceptibility to noise.
The MAX9130 is a single LVDS line receiver ideal for
applications requiring high data rates, low power, and
low noise. The device accepts an LVDS input and
translates it to an LVTTL/LVCMOS output. The receiver
detects differential signals as low as 50mV and as high
as 1V within an input voltage range of 0 to +2.4V.
The 250mV to 450mV differential output of an LVDS dri-
ver is nominally centered around a +1.25V offset. This
offset, coupled with the receiver’s 0 to +2.4V input volt-
age range, allows an approximate ±1V shift in the sig-
nal (as seen by the receiver). This allows for a
difference in ground references of the driver and the
receiver, the common-mode effects of coupled noise,
or both. The LVDS standards specify an input voltage
range of 0 to +2.4V referenced to receiver ground.
Fail-Safe
The fail-safe feature of the MAX9130 sets the output
high and reduces supply current to 150µA when:inputs are openinputs are undriven and shortedinputs are undriven and terminated
A fail-safe circuit is important because under these
conditions, noise at the input may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when an LVDS driver output is in high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to VCC- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage
is less than VCC- 0.3V and the fail-safe circuit is not
activated. If the inputs are open or if the inputs are
undriven and shorted or undriven and parallel terminat-
ed, there is no input current. In this case, a pullup resis-
tor in the fail-safe circuit pulls both inputs above VCC-
0.3V, activating the fail-safe circuit and forcing the out-
put high.
Applications Information
Power-Supply Bypassing
Bypass VCCwith a high-frequency surface-mount
ceramic 0.01µF capacitor as close to the device as
possible.
Single 500Mbps LVDS Line Receiver in SC70
Pin Description
PINNAMEFUNCTION
1VCCPower-Supply Input. Bypass VCC to
GND with a 0.01µF ceramic capacitor.
2, 5GNDGroundIN-Inverting LVDS Differential InputIN+Noninverting LVDS Differential InputOUTLVTTL/LVCMOS Output
IN+
IN-
GND
OUT
MAX9130
VCC
RIN2
VCC - 0.3V
RIN1
RIN1
Figure 1. Fail-Safe Input Network
MAX9130
PULSE
GENERATOROUT
*50Ω REQUIRED FOR PULSE GENERATOR.
IN+
IN-
*50Ω*50Ω
Figure 2. Propagation Delay and Transition Time Test Circuit

Partno	Mfg	Dc	Qty	Available	Descript
MAX9130EXT+T \|MAX9130EXTT	MAXIM	N/a	18	avai	Single 500Mbps LVDS Line Receiver in SC70