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MAX9125ESE-MAX9126ESE-MAX9126EUE
Quad LVDS Line Receivers with Integrated Termination
General DescriptionThe MAX9125/MAX9126 quad low-voltage differential
signaling (LVDS) line receivers are ideal for applica-
tions requiring high data rates, low power, and reduced
noise. The MAX9125/MAX9126 are guaranteed to
receive data at speeds up to 500Mbps (250MHz) over
controlled-impedance media of approximately 100Ω.
The transmission media may be printed circuit (PC)
board traces or cables.
The MAX9125/MAX9126 accept four LVDS differential
inputs and translate them to 3.3V CMOS outputs. The
MAX9126 features integrated parallel termination resis-
tors (nominally 115Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
length. The MAX9125 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range
of 0.05V to 2.35V, allowing for ground potential differ-
ences and common-mode noise between the driver
and the receiver. A fail-safe feature sets the output high
when the inputs are open, or when the inputs are
undriven and shorted or parallel terminated. The EN
and ENinputs control the high-impedance output and
are common to all four receivers. Inputs conform to the
ANSI TIA/EIA-644 LVDS standard. The MAX9125/
MAX9126 operate from a single +3.3V supply, are
specified for operation from -40°C to +85°C, and are
available in 16-pin TSSOP and SO packages. Refer to
the MAX9124 data sheet for a quad LVDS line driver.
ApplicationsDigital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
FeaturesIntegrated Termination Eliminates Four External
Resistors (MAX9126)Pin Compatible with DS90LV032AGuaranteed 500Mbps Data Rate300ps Pulse Skew (max)Conform to ANSI TIA/EIA-644 LVDS StandardSingle +3.3V SupplyLow 70µAShutdown Supply CurrentFail-Safe Circuit
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Ordering Information
Typical Application Circuit
Pin Configuration appears at end of data sheet.
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential input voltage |VID|= 0.1V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V - |VID/2|, TA=
-40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND.................................................-0.3V to +4.0V
EN, ENto GND...........................................-0.3V to (VCC+ 0.3V)
OUT_ to GND.............................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection (Human Body Model) IN_+, IN_-, OUT_............±7.5kV
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, differential input voltage |VID|= 0.1V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V - |VID/2|, TA=
-40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, CL= 10pF, differential input voltage |VID|= 0.2V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V
- |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCM= 1.2V, |VID|= 0.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
Typical Operating Characteristics(VCC= +3.3V, |VID|= 200mV, VCM= +1.2V, CL= 10pF, frequency = 10MHz, TA= +25°C, unless otherwise noted.) (Figures 2 and 3)
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 2:Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 3:AC parameters are guaranteed by design and characterization.
Note 4:CLincludes scope probe and test jig capacitance.
Note 5:tSKD1is the magnitude difference of differential propagation delays in a channel; tSKD1= |tPHLD- tPLHD|.
Note 6:tSKD2is the magnitude difference of the tPLHDor tPHLDof one channel and the tPLHDor tPHLDof any other channel on the
same part.
Note 7:tSKD3is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCCand within 5°C of each other.
Note 8:tSKD4is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 9:fMAXgenerator output conditions: tR= tF< 1ns (0% to 100%), 50% duty cycle, VOL= 1.1V, VOH= 1.3V. Receiver output
criteria: 60% to 40% duty cycle, VOL= 0.4V (max), VOH= 2.7V (min), load = 10pF.
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, CL = 10pF, differential input voltage |VID|= 0.2V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V
- |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCM= 1.2V, |VID|= 0.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Typical Operating Characteristics (continued)(VCC= +3.3V, |VID|= 200mV, VCM= +1.2V, CL= 10pF, frequency = 10MHz, TA= +25°C, unless otherwise noted (Figures 2 and 3).)
Pin Description
MAX9125/MAX9126
Detailed DescriptionThe LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9125/MAX9126 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate ±1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS
standards specify an input voltage range of 0 to 2.4V
referenced to receiver ground.
The MAX9126 has an integrated termination resistor
internally connected across each receiver input. The
internal termination saves board space, eases layout,
and reduces “stub length” compared to an external ter-
mination resistor. In other words, the transmission line
is terminated on the IC.
Quad LVDS Line Receivers with
Integrated Termination
Table 1. Input/Output Function Table
