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MAX9125ESE+
Quad LVDS Line Receivers with Integrated Termination
General DescriptionThe MAX9125/MAX9126 quad low-voltage differential
signaling (LVDS) line receivers are ideal for applica-
tions requiring high data rates, low power, and reduced
noise. The MAX9125/MAX9126 are guaranteed to
receive data at speeds up to 500Mbps (250MHz) over
controlled-impedance media of approximately 100Ω.
The transmission media may be printed circuit (PC)
board traces or cables.
The MAX9125/MAX9126 accept four LVDS differential
inputs and translate them to 3.3V CMOS outputs. The
MAX9126 features integrated parallel termination resis-
tors (nominally 115Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
length. The MAX9125 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range
of 0.05V to 2.35V, allowing for ground potential differ-
ences and common-mode noise between the driver
and the receiver. A fail-safe feature sets the output high
when the inputs are open, or when the inputs are
undriven and shorted or parallel terminated. The EN
and ENinputs control the high-impedance output and
are common to all four receivers. Inputs conform to the
ANSI TIA/EIA-644 LVDS standard. The MAX9125/
MAX9126 operate from a single +3.3V supply, are
specified for operation from -40°C to +85°C, and are
available in 16-pin TSSOP and SO packages. Refer to
the MAX9124 data sheet for a quad LVDS line driver.
ApplicationsDigital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
FeaturesIntegrated Termination Eliminates Four External
Resistors (MAX9126)Pin Compatible with DS90LV032AGuaranteed 500Mbps Data Rate300ps Pulse Skew (max)Conform to ANSI TIA/EIA-644 LVDS StandardSingle +3.3V SupplyLow 70µAShutdown Supply CurrentFail-Safe Circuit
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Ordering Information115Ω
MAX9124MAX9126
115Ω
115Ω
115Ω
LVDS SIGNALS
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
LVTTL/LVCMOS
DATA INPUT
LVTTL/LVCMOS
DATA OUTPUT
Typical Application Circuit19-1908; Rev 0; 5/01
EVALUATION KIT
AVAILABLE
PARTTEMP. RANGEPIN-PACKAGE
MAX9125EUE-40°C to +85°C16 TSSOP
MAX9125ESE-40°C to +85°C16 SO
MAX9126EUE-40°C to +85°C16 TSSOP
MAX9126ESE-40°C to +85°C16 SO
Pin Configuration appears at end of data sheet.
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential input voltage |VID|= 0.1V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V - |VID/2|, TA=
-40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND.................................................-0.3V to +4.0V
EN, ENto GND...........................................-0.3V to (VCC+ 0.3V)
OUT_ to GND.............................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection (Human Body Model) IN_+, IN_-, OUT_............±7.5kV
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUTS (IN_+, IN_-)Differential Input High ThresholdVTH100mV
Differential Input Low ThresholdVTL-100mV
0.1V ≤VID≤ 0.6V,-2020Input Current (MAX9125)IIN_+,
IIN_-0.6V <VID≤ 1.0V-2525µA
0.1V ≤VID≤ 0.6V, VCC = 0-2020Power-Off Input Current
(MAX9125)
IIN_+,
IIN_-0.6V <VID≤ 1.0V, VCC = 0-2525µA
Input Resistor 1RIN1VCC = +3.6V or 0, Figure 135kΩ
Input Resistor 2RIN2VCC = +3.6V or 0, Figure 1132kΩ
Differential Input Resistance
(MAX9126)RDIFFVCC = +3.6V or 0, Figure 190115132Ω
LVCMOS/LVTTL OUTPUTS (OUT_)Open, undriven short, or
undriven 100Ω parallel
termination
2.73.2IOH =
-4.0mA
(MAX9125)
VID = +100mV2.73.2
Open or undriven short2.73.2
Output High VoltageVOH
IOH =
-4.0mA
(MAX9126)VID = +100mV2.73.2
Output Low VoltageVOLIOL = +4.0mA, VID = -100mV0.10.25V
Output Short-Circuit CurrentIOSEnabled, VID = +100mV, VOUT_ = 0 (Note 2)-15-120mA
Output High-Impedance CurrentIOZDisabled, VOUT_ = 0 or VCC-10+10µA
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, differential input voltage |VID|= 0.1V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V - |VID/2|, TA=
-40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, CL= 10pF, differential input voltage |VID|= 0.2V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V
- |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCM= 1.2V, |VID|= 0.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS (EN, EN)Input High VoltageVIH2.0VCCV
Input Low VoltageVIL00.8V
Input CurrentIINVIN = VCC or 0-1515µA
SUPPLYSupply CurrentICCEnabled, inputs open915mA
Disabled Supply CurrentICCZDisabled, inputs open70500µA
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential Propagation Delay
High to LowtPHLDFigures 2 and 31.82.43.3ns
Differential Propagation Delay
Low to HightPLHDFigures 2 and 31.82.33.3ns
Differential Pulse Skew
[tPHLD - tPLHD] (Note 5)tSKD1Figures 2 and 3100300ps
Differential Channel-to-Channel
Skew (Note 6)tSKD2Figures 2 and 3400ps
Differential Part-to-Part Skew
(Note 7)tSKD3Figures 2 and 30.8ns
Differential Part-to-Part Skew
(Note 8)tSKD4Figures 2 and 31.5ns
Rise TimetTLHFigures 2 and 30.341.2ns
Fall TimetTHLFigures 2 and 30.321.2ns
Disable Time High to ZtPHZRL = 2kΩ, Figures 4 and 512ns
Disable Time Low to ZtPLZRL = 2kΩ, Figures 4 and 512ns
Enable Time Z to HightPZHRL = 2kΩ, Figures 4 and 517ns
Enable Time Z to LowtPZLRL = 2kΩ, Figures 4 and 517ns
Maximum Operating Frequency
(Note 9)fMAXAll channels switching250300MHz
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9125/6 toc03
DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLDtPLHD
Typical Operating Characteristics(VCC= +3.3V, |VID|= 200mV, VCM= +1.2V, CL= 10pF, frequency = 10MHz, TA= +25°C, unless otherwise noted.) (Figures 2 and 3)
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 2:Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 3:AC parameters are guaranteed by design and characterization.
Note 4:CLincludes scope probe and test jig capacitance.
Note 5:tSKD1is the magnitude difference of differential propagation delays in a channel; tSKD1= |tPHLD- tPLHD|.
Note 6:tSKD2is the magnitude difference of the tPLHDor tPHLDof one channel and the tPLHDor tPHLDof any other channel on the
same part.
Note 7:tSKD3is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCCand within 5°C of each other.
Note 8:tSKD4is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 9:fMAXgenerator output conditions: tR= tF< 1ns (0% to 100%), 50% duty cycle, VOL= 1.1V, VOH= 1.3V. Receiver output
criteria: 60% to 40% duty cycle, VOL= 0.4V (max), VOH= 2.7V (min), load = 10pF.
SUPPLY CURRENT vs. SWITCHING
FREQUENCY, FOUR CHANNELS SWITCHING
MAX9125/6 toc01
SWITCHING FREQUENCY (MHz)
SUPPLY CURRENT (mA)
VCC = +3.6V
VCC = +3.3V
VCC = +3V
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9125/6 toc02
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, CL = 10pF, differential input voltage |VID|= 0.2V to 1.0V, common-mode voltage VCM= |VID/2|to 2.4V
- |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCM= 1.2V, |VID|= 0.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
Typical Operating Characteristics (continued)(VCC= +3.3V, |VID|= 200mV, VCM= +1.2V, CL= 10pF, frequency = 10MHz, TA= +25°C, unless otherwise noted (Figures 2 and 3).)
PINNAMEFUNCTION1, 7, 9, 15IN_-Inverting Differential Receiver Inputs
2, 6, 10, 14IN_+Noninverting Differential Receiver Inputs
3, 5, 11, 13OUT_LVCMOS/LVTTL Receiver Outputs
4, 12EN, ENReceiver Enable Inputs. When EN = low and EN = high, the outputs are disabled and in high
impedance. For other combinations of EN and EN, the outputs are active.GNDGroundVCCPower Supply Input. Bypass VCC to GND with 0.1μF and 0.001μF ceramic capacitors.
Pin DescriptionDIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9125/6 toc04
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
PULSE SKEW vs. TEMPERATURE
MAX9125/6 toc07
TEMPERATURE (°C)
SKEW (ps)
TRANSITION TIME vs. CAPACITIVE LOAD
MAX9125/6 toc08
CAPACITIVE LOAD (pF)
TRANSITION TIME (ps)
tTLH
tTHL
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9125/6 toc05
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
PULSE SKEW vs. SUPPLY VOLTAGE
MAX9125/6 toc06
SUPPLY VOLTAGE (V)
SKEW (ps)
MAX9125/MAX9126
Detailed DescriptionThe LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9125/MAX9126 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate ±1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS
standards specify an input voltage range of 0 to 2.4V
referenced to receiver ground.
The MAX9126 has an integrated termination resistor
internally connected across each receiver input. The
internal termination saves board space, eases layout,
and reduces “stub length” compared to an external ter-
mination resistor. In other words, the transmission line
is terminated on the IC.
Quad LVDS Line Receivers with
Integrated Termination
ENABLESINPUTSOUTPUTEN
(IN_+) - (IN_-)OUT_XZ
VID ≥ +100mVH
VID ≤ -100mVL
MAX9125
Open, undriven short, or
undriven 100Ω parallel
termination
All other combinations of ENABLE inputs
MAX9126Open or undriven short
Table 1. Input/Output Function TableIN_+
VCC - 0.3V
IN_-
OUT_
MAX9125MAX9126
RIN2
VCC
RIN1
RIN1
IN_+
VCC - 0.3V
IN_-
OUT_
RIN2
VCC
RIN1
RDIFF
RIN1
Figure 1. Inputs with Internal Fail-Safe Circuitry
