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MAX9124ESE ,Quad LVDS Line DriverApplications CircuitDigital Copiers DSLAMsLVDS SIGNALSLaser Printers NetworkSwitches/RoutersCell Ph ..
MAX9124ESE ,Quad LVDS Line Driverapplications requiring high Guaranteed 800Mbps Data Ratedata rates, low power, and low noise. The ..
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MAX9124ESE
Quad LVDS Line Driver
General Description
The MAX9124 quad low-voltage differential signaling
(LVDS) line driver is ideal for applications requiring high
data rates, low power, and low noise. The MAX9124 is
guaranteed to transmit data at speeds up to 800Mbps
(400MHz) over controlled impedance media of approxi-
mately 100Ω. The transmission media may be printed
circuit (PC) board traces, backplanes, or cables.
The MAX9124 accepts four LVTTL/LVCMOS input levels
and translates them to LVDS output signals. Moreover,
the MAX9124 is capable of setting all four outputs to a
high-impedance state through two enable inputs, EN andEN, thus dropping the device to an ultra-low-power state
of 16mW (typ) during high impedance. The enables are
common to all four transmitters. Outputs conform to the
ANSI TIA/EIA-644 LVDS standard.
The MAX9124 operates from a single +3.3V supply and is
specified for operation from -40°C to +85°C. It is available
in 16-pin TSSOP and SO packages. Refer to the MAX9125/
MAX9126 data sheet for quad LVDS line receivers.
Applications
FeaturesPin Compatible with DS90LV031AGuaranteed 800Mbps Data Rate250ps Maximum Pulse Skew Conforms to TIA/EIA-644 LVDS StandardSingle +3.3V Supply16-Pin TSSOP and SO Packages
MAX9124
Quad LVDS Line Driver
Pin Configuration
Ordering Information
Typical Applications Circuit
19-1991; Rev 0; 4/01
* Future product—contact factory for availability.
Digital Copiers
Laser Printers
Cell Phone Base
Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network
Switches/Routers
Backplane
Interconnect
Clock Distribution
MAX9124
Quad LVDS Line Driver
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω±1%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise
noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_, EN, ENto GND....................................-0.3V to (VCC+ 0.3V)
OUT_+, OUT_- to GND..........................................-0.3V to +3.9V
Short-Circuit Duration (OUT_+, OUT_-).....................Continuous
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection
Human Body Model, OUT_+, OUT_-..............................±6kV
MAX9124
Quad LVDS Line Driver
SWITCHING CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless
Note 1:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at TA= +25°C.
Note 2:Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
VOD.
Note 3:Guaranteed by correlation data.
Note 4:AC parameters are guaranteed by design and characterization.
Note 5:CLincludes probe and jig capacitance.
Note 6:Signal generator conditions for dynamic tests: VOL= 0, VOH= 3V, f = 100MHz, 50% duty cycle, RO= 50Ω, tR≤1ns, tF≤
1ns (0% to 100%).
Note 7:tSKD1is the magnitude difference of differential propagation delay. tSKD1= |tPHLD- tPLHD|.
Note 8:tSKD2is the magnitude difference of tPHLDor tPLHDof one channel to the tPHLDor tPLHDof another channel on the same
device.
Note 9:tSKD3is the magnitude difference of any differential propagation delays between devices at the same VCCand within 5°C
of each other.
Note 10:tSKD4is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 11:fMAXsignal generator conditions: VOL= 0, VOH= 3V, f = 400MHz, 50% duty cycle, RO= 50Ω, tR≤1ns, tF≤1ns (0% to
100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD≥250mV.
MAX9124
Quad LVDS Line Driver
Typical Operating Characteristics
(TA= +25°C)
MAX9124
Quad LVDS Line Driver
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9124 is an 800Mbps quad differential LVDS
driver that is designed for high-speed, point-to-point,
and low-power applications. This device accepts
LVTTL/LVCMOS input levels and translates them to
LVDS output signals.
The MAX9124 generates a 2.5mA to 4.0mA output cur-
rent using a current-steering configuration. This current-
steering approach induces less ground bounce and no
shoot-through current, enhancing noise margin and sys-
tem speed performance. The driver outputs are short-
circuit current limited and enter a high-impedance state
when the device is not powered or is disabled.
The current-steering architecture of the MAX9124
requires a resistive load to terminate the signal and
complete the transmission loop. Because the device
switches current and not voltage, the actual output volt-
age swing is determined by the value of the termination
resistor at the input of an LVDS receiver. Logic states
are determined by the direction of current flow through
the termination resistor. With a typical 3.7mA output
current, the MAX9124 produces an output voltage of
370mV when driving a 100Ωload.
Termination
Because the MAX9124 is a current-steering device, no
output voltage will be generated without a termination
resistor. The termination resistors should match the dif-
ferential impedance of the transmission line. Output
voltage levels depend upon the value of the termination
resistor. The MAX9124 is optimized for point-to-point
interface with 100Ωtermination resistors at the receiver
inputs. Termination resistance values may range
between 90Ωand 132Ω, depending on the characteris-
tic impedance of the transmission medium.
Applications Information
Power-Supply Bypassing
Bypass VCCwith high-frequency, surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
capacitor closest to VCC.
Differential Traces
Output trace characteristics affect the performance of
the MAX9124. Use controlled-impedance traces to
match trace impedance to the transmission medium.
Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90°turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables, such as twisted
pair, offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
Chip Information
TRANSISTOR COUNT: 2007
PROCESS: CMOS
MAX9124
Quad LVDS Line Driver
Figure 4. Driver High-Impedance Delay Test Circuit

Partno	Mfg	Dc	Qty	Available	Descript
MAX9124ESE	MAX	N/a	80	avai	Quad LVDS Line Driver
MAX9124ESE	MAXIM	N/a	2	avai	Quad LVDS Line Driver