MAX9123ESE-MAX9123EUE-MAX9123EUE+-MAX9123EUE+T Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX9123ESE-MAX9123EUE-MAX9123EUE+-MAX9123EUE+T
Quad LVDS Line Driver with Flow-Through Pinout
General Description
The MAX9123 quad low-voltage differential signaling
(LVDS) differential line driver is ideal for applications
requiring high data rates, low power, and low noise. The
MAX9123 is guaranteed to transmit data at speeds up to
800Mbps (400MHz) over controlled impedance media of
approximately 100Ω. The transmission media may be
printed circuit (PC) board traces, backplanes, or cables.
The MAX9123 accepts four LVTTL/LVCMOS input levels
and translates them to LVDS output signals. Moreover,
the MAX9123 is capable of setting all four outputs to a
high-impedance state through two enable inputs, EN and
EN, thus dropping the device to an ultra-low-power state
of 16mW (typ) during high impedance. The enables are
common to all four transmitters. Outputs conform to the
ANSI TIA/EIA-644 LVDS standard. Flow-through pinout
simplifies PC board layout and reduces crosstalk by sep-
arating the LVTTL/LVCMOS inputs and LVDS outputs.
The MAX9123 operates from a single +3.3V supply and is
specified for operation from -40°C to +85°C. It is available
in 16-pin TSSOP and SO packages. Refer to the MAX9121/
MAX9122* data sheet for quad LVDS line receivers with
integrated termination and flow-through pinout.
Applications
FeaturesFlow-Through Pinout
Simplifies PC Board Layout
Reduces CrosstalkPin Compatible with DS90LV047AGuaranteed 800Mbps Data Rate250ps Maximum Pulse Skew Conforms to TIA/EIA-644 LVDS StandardSingle +3.3V Supply16-Pin TSSOP and SO Packages
MAX9123
Quad LVDS Line Driver with
Flow-Through PinoutOUT1-
OUT1+
OUT2+
OUT2-
OUT3-
OUT3+
OUT4+
OUT4-
TOP VIEW
MAX9123
TSSOP/SO
IN1
IN2
IN3
VCC
GND
IN4
Pin Configuration
Ordering Information
107Ω
MAX9123MAX9122*
107Ω
107Ω
107Ω
LVDS SIGNALS
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
LVTTL/CMOS
DATA INPUT
LVTTL/CMOS
DATA OUTPUT
Typical Applications Circuit
19-1927; Rev 0; 2/01
PARTTEMP. RANGEPIN-PACKAGE
MAX9123EUE-40°C to +85°C16 TSSOP
MAX9123ESE-40°C to +85°C16 SO
* Future product—contact factory for availability.
Digital Copiers
Laser Printers
Cell Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network
Switches/Routers
Backplane
Interconnect
Clock Distribution
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω±1%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise
noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN_, EN, ENto GND....................................-0.3V to (VCC+ 0.3V)
OUT_+, OUT_- to GND..........................................-0.3V to +3.9V
Short-Circuit Duration (OUT_+, OUT_-).....................Continuous
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection
Human Body Model, IN_, OUT_+, OUT_-.......................±4kV
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS OUTPUT (OUT_+, OUT_-)
Differential Output VoltageVODFigure 1250368450mV
Change in Magnitude of VOD
Between Complementary Output
States
ΔVODFigure 1135mV
Offset VoltageVOSFigure 11.1251.251.375V
Change in Magnitude of VOS
Between Complementary Output
States
ΔVOSFigure 1425mV
Output High VoltageVOH1.6V
Output Low VoltageVOL0.90V
Differential Output Short-Circuit
Current (Note 3)IOSDEnabled, VOD = 0-9mA
Output Short-Circuit CurrentIOSOUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_
= 0, enabled-3.8-9mA
Output High-Impedance CurrentIOZEN = low and EN = high, OUT_+ = 0 or VCC,
OUT_- = 0 or VCC , RL = ∞-1010µA
Power-Off Output CurrentIOFFVCC = 0 or open, OUT_+ = 0 or 3.6V, OUT_-
= 0 or 3.6V, RL = ∞-2020µA
INPUTS (IN_, EN, EN)
High-Level Input VoltageVIH2.0VCCV
Low-Level Input VoltageVILGND0.8V
Input CurrentIININ_, EN, EN = 0 or VCC-2020µA
SUPPLY CURRENT
No-Load Supply CurrentICCRL = ∞, IN_ = VCC or 0 for all channels9.211mA
Loaded Supply CurrentICCLRL = 100Ω, IN_ = VCC or 0 for all channels22.730mA
Disabled Supply CurrentICCZD i sab l ed , IN _ = V C C or 0 for all channel s,N = 0, EN = VCC4.96mA
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
SWITCHING CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 15pF, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless
otherwise noted.) (Notes 4, 5, 6)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Differential Propagation Delay
High to LowtPHLDFigures 2 and 30.71.7ns
Differential Propagation Delay
Low to HightPLHDFigures 2 and 30.71.7ns
Differential Pulse Skew (Note 7)tSKD1Figures 2 and 30.040.25ns
Differential Channel-to-Channel
Skew (Note 8)tSKD2Figures 2 and 30.070.35ns
Differential Part-to-Part Skew
(Note 9)tSKD3Figures 2 and 30.130.8ns
Differential Part-to-Part Skew
(Note 10)tSKD4Figures 2 and 30.431.0ns
Rise TimetTLHFigures 2 and 30.20.391.0ns
Fall TimetTHLFigures 2 and 30.20.391.0ns
Disable Time High to ZtPHZFigures 4 and 52.75ns
Disable Time Low to ZtPLZFigures 4 and 52.75ns
Enable Time Z to HightPZHFigures 4 and 52.37ns
Enable Time Z to LowtPZLFigures 4 and 52.37ns
Maximum Operating Frequency
(Note 11)fMAX400MHz
Note 1:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at TA= +25°C.
Note 2:Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
VOD.
Note 3:Guaranteed by correlation data.
Note 4:AC parameters are guaranteed by design and characterization.
Note 5:CLincludes probe and jig capacitance.
Note 6:Signal generator conditions for dynamic tests: VOL= 0, VOH= 3V, f = 100MHz, 50% duty cycle, RO= 50Ω, tR≤1ns, tF≤
1ns (0% to 100%).
Note 7:tSKD1is the magnitude difference of differential propagation delay. tSKD1= |tPHLD- tPLHD|.
Note 8:tSKD2is the magnitude difference of tPHLDor tPLHDof one channel to the tPHLDor tPLHDof another channel on the same
device.
Note 9:tSKD3is the magnitude difference of any differential propagation delays between devices at the same VCCand within 5°C
of each other.
Note 10:tSKD4is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 11:fMAXsignal generator conditions: VOL= 0, VOH= 3V, f = 400MHz, 50% duty cycle, RO= 50Ω, tR≤1ns, tF≤1ns (0% to
100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD≥250mV.
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
Typical Operating Characteristics
(VCC= +3.3V, RL= 100Ω, CL= 15pF, TA= +25°C, unless otherwise noted.)
OUTPUT HIGH VOLTAGE
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc01
POWER-SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
OUTPUT LOW VOLTAGE
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc02
POWER-SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc03
OUTPUT SHORT-CIRCUIT CURRENT (mA)
POWER-SUPPLY VOLTAGE (V)
VIN = VCC or
GND
MAX9123 toc04
OUTPUT HIGH-IMPEDANCE STATE CURRENT
vs. POWER-SUPPLY VOLTAGE
OUTPUT HIGH-IMPEDANCE STATE CURRENT (pA)
POWER-SUPPLY VOLTAGE (V)
VIN = VCC or
GND
DIFFERENTIAL OUTPUT VOLTAGE
vs. POWER SUPPLY
MAX9123 toc05
POWER-SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
MAX9123 toc06
LOAD RESISTOR (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
OFFSET VOLTAGE
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc07
POWER-SUPPLY VOLTAGE (V)
OFFSET VOLTAGE (V)
POWER-SUPPLY CURRENT
vs. FREQUENCY
MAX9123 toc08
FREQUENCY (MHz)
POWER-SUPPLY CURRENT (mA)
VIN = 0 to 3V
ALL SWITCHING
ONE SWITCHING20.0
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc09
POWER-SUPPLY VOLTAGE (V)
POWER-SUPPLY CURRENT (mA)
FREQ = 1MHz
VIN = 0 to 3V
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
POWER-SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
MAX9123 toc10
AMBIENT TEMPERATURE (°C)
POWER-SUPPLY CURRENT (mA)
FREQ = 1MHz
VIN = 0 to 3V
DIFFERENTIAL PROPAGATION DELAY
vs. POWER SUPPLY
MAX9123 toc11
POWER-SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
FREQ = 1MHz
tPLHD
tPHLD
DIFFERENTIAL PROPAGATION DELAY
vs. AMBIENT TEMPERATURE
MAX9123 toc12
AMBIENT TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
FREQ = 1MHz
DIFFERENTIAL SKEW
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc13
POWER-SUPPLY VOLTAGE (V)
DIFFERENTIAL SKEW (ps)
FREQ = 1MHz
DIFFERENTIAL SKEW
vs. AMBIENT TEMPERATURE
MAX9123 toc14
AMBIENT TEMPERATURE (°C)
DIFFERENTIAL SKEW (ps)
FREQ = 1MHz
TRANSITION TIME
vs. POWER-SUPPLY VOLTAGE
MAX9123 toc15
POWER-SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
FREQ = 1MHz
tTLH
tTHL
TRANSITION TIME
vs. AMBIENT TEMPERATURE
MAX9123 toc16
AMBIENT TEMPERATURE (°C)
TRANSITION TIME (ps)
FREQ = 1MHz
tTLH
tTHL
Typical Operating Characteristics (continued)
(VCC= +3.3V, RL= 100Ω, CL= 15pF, TA= +25°C, unless otherwise noted.)
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
Pin Description
PINNAMEFUNCTION
1EN
Driver Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN =
high and EN = low or open, the outputs are active. For other combinations of EN and EN, the
outputs are disabled and are high impedance.
2, 3, 6, 7IN_LVTTL/LVCMOS Driver Inputs
4VCCPower-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.GNDGroundENDriver Enable Input. The transmitter is disabled when EN is high. EN is internally pulled down.
9, 12, 13, 16OUT_-Inverting LVDS Driver Outputs
10, 11, 14, 15OUT_+Noninverting LVDS Driver Outputs
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9123 is an 800Mbps quad differential LVDS
driver that is designed for high-speed, point-to-point,
and low-power applications. This device accepts
LVTTL/LVCMOS input levels and translates them to
LVDS output signals.
The MAX9123 generates a 2.5mA to 4.0mA output cur-
rent using a current-steering configuration. This current-
steering approach induces less ground bounce and no
shoot-through current, enhancing noise margin and sys-
tem speed performance. The driver outputs are short-
circuit current limited, and enter a high-impedance state
when the device is not powered or is disabled.
The current-steering architecture of the MAX9123
requires a resistive load to terminate the signal and
complete the transmission loop. Because the device
switches current and not voltage, the actual output volt-
age swing is determined by the value of the termination
resistor at the input of an LVDS receiver. Logic states
are determined by the direction of current flow through
the termination resistor. With a typical 3.7mA output
current, the MAX9123 produces an output voltage of
370mV when driving a 100Ωload.
Termination
Because the MAX9123 is a current-steering device, no
output voltage will be generated without a termination
resistor. The termination resistors should match the dif-
ferential impedance of the transmission line. Output
voltage levels depend upon the value of the termination
resistor. The MAX9123 is optimized for point-to-point
interface with 100Ωtermination resistors at the receiver
inputs. Termination resistance values may range
between 90Ωand132Ω, depending on the characteris-
tic impedance of the transmission medium.
Applications Information
Power-Supply Bypassing
Bypass VCCwith high-frequency, surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to VCC.
Differential Traces
Output trace characteristics affect the performance of
the MAX9123. Use controlled-impedance traces to
match trace impedance to the transmission medium.
ENABLESINPUTSOUTPUTSENIN_OUT_+OUT_ -L or openLLHL or openHHL
All other combinations
of ENABLE pins
Don’t
careZZ
Table 1. Input/Output Function Table

Partno	Mfg	Dc	Qty	Available	Descript
MAX9123ESE	MAXIM	N/a	14	avai	Quad LVDS Line Driver with Flow-Through Pinout
MAX9123EUE	MAX	N/a	6	avai	Quad LVDS Line Driver with Flow-Through Pinout
MAX9123EUE	MAXIM	N/a	33	avai	Quad LVDS Line Driver with Flow-Through Pinout
MAX9123EUE+ \|MAX9123EUE	MAX	N/a	170	avai	Quad LVDS Line Driver with Flow-Through Pinout
MAX9123EUE+T \|MAX9123EUET	MAXIM	N/a	10000	avai	Quad LVDS Line Driver with Flow-Through Pinout