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MAX9121EUE-MAX9122ESE-MAX9122EUE-MAX9122EUE+
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout
General DescriptionThe MAX9121/MAX9122 quad low-voltage differential sig-
naling (LVDS) differential line receivers are ideal for appli-
cations requiring high data rates, low power, and low
noise. The MAX9121/MAX9122 are guaranteed to receive
data at speeds up to 500Mbps (250MHz) over controlled-
impedance media of approximately 100Ω. The transmis-
sion media may be printed circuit (PC) board traces or
cables.
The MAX9121/MAX9122 accept four LVDS differential
inputs and translate them to LVCMOS outputs. The
MAX9122 features integrated parallel termination resis-
tors (nominally 107Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
lengths. The MAX9121 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range of
0.05V to 2.35V, allowing for ground potential differences
and common-mode noise between the driver and the
receiver. A fail-safe feature sets the output high when the
inputs are open, or when the inputs are undriven and
shorted or parallel terminated. The EN and ENinputs con-
trol the high-impedance output. The enables are common
to all four receivers. Inputs conform to the ANSI TIA/EIA-
644 LVDS standard. Flow-through pinout simplifies PC
board layout and reduces crosstalk by separating the
LVDS inputs and LVCMOS outputs. The MAX9121/
MAX9122 operate from a single +3.3V supply, and are
specified for operation from -40°C to +85°C. These
devices are available in 16-pin TSSOP and SO packages.
Refer to the MAX9123 data sheet for a quad LVDS line dri-
ver with flow-through pinout.
ApplicationsDigital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
____________________________FeaturesIntegrated Termination Eliminates Four External
Resistors (MAX9122)Flow-Through Pinout
Simplifies PC Board Layout
Reduces CrosstalkPin Compatible with DS90LV048AGuaranteed 500Mbps Data Rate300ps Pulse Skew (max)Conform to ANSI TIA/EIA-644 LVDS StandardSingle +3.3V SupplyFail-Safe Circuit
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Typical Application Circuit19-1909; Rev 0; 6/01
EVALUATION KIT
AVAILABLE
Ordering Information
PARTTEMP. RANGEPIN-PACKAGE
MAX9121EUE-40°C to +85°C16 TSSOP
MAX9121ESE-40°C to +85°C16 SO
MAX9122EUE-40°C to +85°C16 TSSOP
MAX9122ESE-40°C to +85°C16 SO
Pin Configuration appears at end of data sheet.MAX9123MAX9122
107Ω
107Ω
107Ω
107Ω
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
LVDS SIGNALS
LVTTL/LVCMOS
DATA OUTPUT
LVTTL/LVCMOS
DATA INPUT
VCCto GND...........................................................-0.3V to +4.0V
IN_+, IN_- to GND.................................................-0.3V to +4.0V
EN, ENto GND...........................................-0.3V to (VCC+ 0.3V)
OUT_ to GND.............................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection
(Human Body Model, IN_+, IN_-)....................................±8kV
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM= |VID/2| to 2.4V - |VID/2|, = -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUTS (IN_+, IN_-)Differential Input High ThresholdVTH100mV
Differential Input Low ThresholdVTL-100mV
0.1V ≤VID≤ 0.6V-2020µAInput Current (MAX9121)IIN_+, IIN_-0.6V <VID≤ 1.0V-2525µA
0.1V ≤VID≤ 0.6V, VCC = 0-2020µAPower-Off Input Current
(MAX9121) IINOFF0.6V <VID≤ 1.0V, VCC = 0-2525µA
Input Resistor 1RIN1VCC = 3.6V or 0, Figure 135kΩ
Input Resistor 2RIN2VCC = 3.6V or 0, Figure 1132kΩ
Differential Input Resistance
(MAX9122)RDIFFVCC = 3.6V or 0, Figure 190107132Ω
LVCMOS/LVTTL OUTPUTS (OUT_)Open, undriven short, or
undriven 100Ω parallel
termination
2.73.2IOH = -4.0mA
(MAX9121)
VID = +100mV2.73.2
Open or undriven short2.73.2
Output High Voltage (Table 1)VOH
IOH = -4.0mA
(MAX9122)VID = +100mV2.73.2
Output Low VoltageVOLIOL = +4.0mA, VID = -100mV0.10.25V
Output Short-Circuit CurrentIOSEnabled, VID = 0.1V, VOUT_ = 0 (Note 2)-15-120mA
Output High-Impedance CurrentIOZDisabled, VOUT = 0 or VCC-10+10µA
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS (EN, EN)Input High VoltageVIH2.0VCCV
Input Low VoltageVIL00.8V
Input CurrentIINVIN_ = VCC or 0-1515µA
SUPPLYSupply CurrentICCEnabled, inputs open915mA
Disabled Supply CurrentICCZDisabled, inputs open0.070.5mA
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, CL= 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM= |VID/2| to 2.4V -
|VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCM= 1.2V, |VID| = 0.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential Propagation Delay
High to LowtPHLDFigures 2 and 31.21.932.7ns
Differential Propagation Delay
Low to HightPLHDFigures 2 and 31.21.792.7ns
Differential Pulse Skew [tPHLD -
tPLHD] (Note 5)tSKD1Figures 2 and 3140300ps
Differential Channel-to-Channel
Skew (Note 6)tSKD2Figures 2 and 3400ps
Differential Part-to-Part Skew
(Note 7)tSKD3Figures 2 and 30.8ns
Differential Part-to-Part Skew
(Note 8)tSKD4Figures 2 and 31.5ns
Rise-TimetTLHFigures 2 and 30.551.0ns
Fall-TimetTHLFigures 2 and 30.541.0ns
Disable Time High to ZtPHZRL = 2kΩ, Figures 4 and 514ns
Disable Time Low to ZtPLZRL = 2kΩ, Figures 4 and 514ns
Enable Time Z to HightPZHRL = 2kΩ, Figures 4 and 570ns
Enable Time Z to LowtPZLRL = 2kΩ, Figures 4 and 570ns
Maximum Operating Frequency
(Note 9)fMAXAll channels switching250300MHz
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM= |VID/2| to 2.4V - |VID/2|, = -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Typical Operating Characteristics(VCC= +3.3V, VCM= +1.2V, |VID| = 0.2V, CL= 15pF, TA = +25°C, unless otherwise noted.) (Figures 2 and 3)
SUPPLY CURRENT
vs. FREQUENCY
MAX9121/22 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
ALL
CHANNELS
SWITCHING
ONE
SWITCHING
SUPPLY CURRENT vs.
TEMPERATURE
MAX9121/22 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9121/22 toc03
SUPPLY VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE (mV)
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, and VID.
Note 2:Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 3:AC parameters are guaranteed by design and characterization.
Note 4:CLincludes scope probe and test jig capacitance.
Note 5:tSKD1is the magnitude difference of differential propagation delays in a channel. tSKD1= |tPHLD- tPLHD|.
Note 6:tSKD2is the magnitude difference of the tPLHDor tPHLDof one channel and the tPLHDor tPHLDof any other channel on the same part.
Note 7:tSKD3is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCCand within 5°C of each other.
Note 8:tSKD4is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 9:fMAXgenerator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, VOH= +1.3V, VOL= +1.1V,
MAX9121/MAX9122 output criteria: 60% to 40% duty cycle, VOL= 0.4V (max), VOH= 2.7V (min), load = 15pF.
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9121/22 toc04
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)-70
OUTPUT HIGH-IMPEDANCE CURRENT
vs. SUPPLY VOLTAGE
MAX9121/22 toc05
SUPPLY VOLTAGE (V)
OUTPUT HIGH-IMPEDANCE CURRENT (nA)
OUTPUT HIGH VOLTAGE vs.
SUPPLY VOLTAGE
MAX9121/22 toc06
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, CL= 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM= |VID/2| to 2.4V -
|VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCM= 1.2V, |VID| = 0.2V, TA= +25°C, unless otherwise noted.) (Notes 3, 4)
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Typical Operating Characteristics (continued)(VCC= +3.3V, VCM= +1.2V, |VID| = 0.2V, CL= 15pF, TA = +25°C, unless otherwise noted.) (Figures 2 and 3)
TRANSITION TIME vs.
SUPPLY VOLTAGE
MAX9121/22 toc13
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
tTLH
tTHL
TRANSITION TIME vs.
TEMPERATURE
MAX9121/22 toc14
TEMPERATURE (°C)
TRANSITION TIME (ps)
tTLH
tTHL
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9121/22 toc07
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9121/22 toc08
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9121/22 toc09
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
MAX9121/22 toc10
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9121/22 toc11
DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PULSE SKEW vs.
SUPPLY VOLTAGE
MAX9121/22 toc12
SUPPLY VOLTAGE (V)
DIFFERENTIAL PULSE SKEW (ps)
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Detailed Description The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS stan-
dard uses a lower voltage swing than other common
communication standards, achieving higher data rates
with reduced power consumption while reducing EMI
emissions and system susceptibility to noise.
The MAX9121/MAX9122 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate ±1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS stan-
dards specify an input voltage range of 0 to +2.4V
referenced to receiver ground.
The MAX9122 has an integrated termination resistor
that is internally connected across each receiver input.
The internal termination saves board space, eases lay-
out, and reduces stub length compared to an external
termination resistor. In other words, the transmission
line is terminated on the IC.
Fail-SafeThe fail-safe feature of the MAX9121/MAX9122 sets an
output high when:Inputs are open.Inputs are undriven and shorted.Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
Pin Description
PINNAMEFUNCTION1, 4, 5, 8IN_-Inverting Differential Receiver Inputs
2, 3, 6, 7IN_+Noninverting Differential Receiver Inputs
9, 16EN, ENReceiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For
other combinations of EN and EN, the outputs are disabled and in high impedance.
10, 11, 14, 15OUT_LVCMOS/LVTTL Receiver OutputsGNDGroundVCCPower-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
Table 1. Input/Output Function Table
ENABLESINPUTSOUTPUTEN
(IN_+) - (IN_-)OUT_VID ≥ +100mVH
VID ≤ -100mVL
MAX9121Open, undriven short, or undriven
100Ω parallel terminationL or open
MAX9122Open or undriven short
All other combinations of ENABLE pinsDon’t careZ
