MAX8855ETJ+T ,Dual, 5A, 2MHz Step-Down Regulatorsapplications. Total output♦ ±1% Output Accuracy Over Load, Line,error is less than ±1% over load, l ..
MAX8856ETD+T ,USB/AC Adapter, Li+ Linear Battery Charger with Integrated 50mΩ Battery Switch in TDFNApplicationsTypical Operating CircuitCellular Phones, Smartphones, PDAsDigital Cameras, MP3 Players ..
MAX8857AETL+ ,Smallest, All-Internal MOSFET, 7-Channel 2 AA DSC PMICFeaturesThe MAX8857A PMIC provides a complete power-sup- ♦ 95% Efficient Synchronous-Rectified DC-D ..
MAX8857AETL+T ,Smallest, All-Internal MOSFET, 7-Channel 2 AA DSC PMICMAX8857AABRIDGED19-0987; Rev 1; 2/12Smallest, All-Internal MOSFET,7-Channel 2 AA DSC PMIC
MAX8858ETJ+T ,Smallest, All-Internal MOSFET, 6-Channel DSC PMIC in a 5mm x 5mm TQFNFeaturesThe MAX8858 PMIC provides a complete power-supply ♦ 95% Efficient Synchronous-Rectified DC- ..
MAX8860EUA18+ ,Low-Dropout, 300mA Linear Regulator in µMAXMAX886019-1422; Rev 2; 1/01Low-Dropout, 300mA Linear Regulator in µMAX
MB86626 , KeyWave AFE ADSL Analog Front End
MB86831 ,Microprocessor SPARClite CMOSapplications. Conforming to the SPARC * architecture, the MB86830 series is upward code-compatible ..
MB86831 ,Microprocessor SPARClite CMOSfeatures of the MB86830 series achieves high levels of speed, flexibility, and efficiency, making i ..
MB86831-80PFV ,32-bit Embedded Controllerapplications. Conforming to the SPARC * architecture, the MB86830 series is upward code-compatible ..
MB86833 ,Microprocessor SPARClite CMOSfeatures of the MB86830 series achieves high levels of speed, flexibility, and efficiency, making i ..
MB86836 ,Microprocessor SPARClite CMOSapplications. Conforming to the SPARC * architecture, the MB86830 series is upward code-compatible ..
MAX8855ETJ+-MAX8855ETJ+T
Dual, 5A, 2MHz Step-Down Regulators
General DescriptionThe MAX8855/MAX8855A high-efficiency, dual step-down
regulators are capable of delivering up to 5A at each out-
put. The devices operate from a 2.25V to 3.6V supply, and
provide output voltages from 0.6V to 0.9 x VIN, making them
ideal for on-board point-of-load applications. Total output
error is less than ±1% over load, line, and temperature.
The MAX8855/MAX8855A operate in PWM mode with a
switching frequency ranging from 0.5MHz to 2MHz, set
by an external resistor. It can also be synchronized to
an external clock in the same frequency range. Two
internal switching regulators operate 180°out-of-phase
to reduce the input ripple current, and consequently
reduce the required input capacitance. The high
operating frequency minimizes the size of external
components. High efficiency, internal dual-nMOS
design keeps the board cool under heavy loads. The
voltage-mode control architecture and the high-band-
width (> 15MHz typ) voltage-error amplifier allow a type
III compensation scheme to be utilized to achieve fast
response under both line and load transients, and also
allow for ceramic output capacitors.
Programmable soft-start reduces input inrush current.
Two enable inputs allow the turning on/off of each out-
put individually, resulting in great flexibility for system-
level designs. A reference input is provided to facilitate
output-voltage tracking applications. The MAX8855/
MAX8855A are available in a 32-pin TQFN (5mm x 5mm)
package with 0.8mm max height.
ApplicationsASIC/CPU/DSP Power Supplies
DDR Power Supplies
Set-Top Box Power Supplies
Printer Power Supplies
Network Power Supplies
Features27mΩOn-Resistance Internal MOSFETsDual, 5A, PWM Step-Down RegulatorsFully Protected Against Overcurrent,Short Circuit, and Overtemperature±1% Output Accuracy Over Load, Line,and TemperatureOperates from 2.25V to 3.6V SupplyREFIN on One Channel for Tracking orExternal ReferenceIntegrated Boost DiodesAdjustable Output from 0.6V to 0.9 x VINSoft-Start Reduces Inrush Supply Current0.5MHz to 2MHz Adjustable Switching,or FSYNC InputAll-Ceramic-Capacitor Design180°Out-of-Phase Operation Reduces InputRipple CurrentIndividual Enable Inputs and PWRGD OutputsSafe-Start into Prebiased OutputAvailable in 5mm x 5mm Thin QFN PackageSink/Source Current in DDR Applications
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
Ordering Information19-0726; Rev 4; 10/11
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
EVALUATION KITAVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX8855ETJ+-40°C to +85°C32 TQFN-EP*
MAX8855AETJ+-40°C to +85°C32 TQFN-EP*
Pin Configuration appears at end of data sheet.FB2
EN2
COMP2
LX2
BST2
GND
PGND2
INPUT1
2.25V TO 3.6V
EN1
BST1
COMP1
FB1
PGND1
LX1
IN1IN2
TYPE III
COMPENSATION
OUTPUT1
1.2V / 5A
INPUT2
2.25V TO 3.6V
PWRGD1PWRGD2
OFF
MAX8855/
MAX8855A
TYPE III
COMPENSATION
OUTPUT2
1.5V / 5A
OFF
Typical Operating Circuit
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VIN_ = VVDD = VVDL = 3.3V, VFB_ = 0.5V, VSS_ = VREFIN= 600mV, PGND_ = GND, RFSYNC= 10kΩ, L = 0.47μH, CBST_= 0.1μF,
CSS_= 0.022μF, PWRGD_ not connected; TA= -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN_, LX_, VDD, VDL, PWRGD_ to GND..................-0.3V to +4.5V
VDD, VDL to IN_.....................................................-0.3V to +4.5V
EN_, SS_, COMP_, FB_, REFIN, FSYNC to GND ......-0.3V to the
lower of (VVDD+ 0.3V) and (VVDL+ 0.3V)
Continuous LX_ Current (Note 1)...................................5.5ARMS
BST_ to LX_...........................................................-0.3V to +4.5V
PGND_ to GND......................................................-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
32-Pin TQFN (5mm x 5mm)
(derate 34.5mW/°C above +70°C)..........................2758.6mW
Operating Ambient Temperature Range.............-40°C to +85°C
Operating Junction Temperature Range...........-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERCONDITIONSMINTYPMAXUNITS
IN1, IN2, VDL, VDDMAX88552.353.60
IN_, VDL, and VDD Voltage Range(Note 3)MAX8855A2.253.60V
VIN_ = 2.5V1.93.5IN_ Supply Current1MHz switching, no loadVIN_ = 3.3V2.85mA
VVDD = 2.5V7.2VDD + VDL Supply Current1MHz switching, VDD = VDLVVDD = 3.3V1015mA
TA = +25°C11Shutdown Supply Current
(IIN1 + IIN2 + IVDD + IVDL)
VIN_ = VVDD = VVDL = V B S T _ - L X _ = 3.6V , V E N _ = 0V TA = +85°C0.3μA
Rising2.02.2IN_, VDD Undervoltage Lockout Threshold
UVLO Monitors VDD, IN1, and IN2Falling1.81.9V
IN_, VDD Undervoltage Lockout Deglitch2μs
BST1, BST2TA = +25°C2Shutdown BST_ CurrentVIN _ = VVD D = VVD L = VBS T_ =
3.6V, VEN _ = 0V, VLX _ = 0 or 3.6V TA = +85°C0.02μA
COMP1, COMP2COMP_ Clamp Voltage, HighVVDD = VIN_ = 2.25V to 3.6V, VFB_ = 0.7V1.802.002.25V
COMP_ Slew Rate1.40V/μs
COMP_ Shutdown ResistanceFrom COMP_ to GND, VEN_ = 0V725Ω
Note 1:LX_ have internal clamp diodes to PGND_ and IN_. Applications that forward bias these diodes should take care not to
exceed the IC’s package power-dissipation limits.
Note 2:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 2)TQFN
Junction-to-Ambient Thermal Resistance (θJA)...........29°C/W
Junction-to-Case Thermal Resistance (θJC)...............1.7°C/W
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
PARAMETERCONDITIONSMINTYPMAXUNITS
ERROR AMPLIFIERV D D = V I N _ = 2.5V to
3.3V ( M AX 8855) FB_ Regulation VoltageV C OM P _ = 1V to
2V V V D D = V I N _ = 2.25V to
3.3V ( M AX 8855A)
0.5940.6000.606VV D D = V I N _ = 2.5V to
3.3V ( M AX 8855) FB_ Regulation Voltage with External
ReferenceV C OM P _ = 1V to
2V V V D D = V I N _ = 2.25V to
3.3V ( M AX 8855A)
0.5940.6000.606V
Error Amplifier Common-Mode-Input Range0VVDD -
1.6V
Error Amplifier Maximum Output Current1mA
TA = +25°C40300FB_ Input Bias CurrentVFB_ = 0.605VTA = +85°C37nA
REFIN, SS2TA = +25°C90500REFIN Input Bias CurrentVFB_ = 0.610VTA = +85°C65nA
MAX8855VVDD = 2.35V to 2.6V
MAX8855AVVDD = 2.25V to 2.6V0VVDD -
REFIN Common-Mode Range
VVDD = 2.6V to 3.6V0VVDD -
LX1, LX2 (ALL PINS COMBINED)IN _ = VBS T_ - VLX _ = 3.3V 3152LX_ On-Resistance, HighILX_ = -2AV IN _ = VBS T_ - VLX _ = 2.5V34mΩ
VIN _ = 3.3V2746LX_ On-Resistance, LowILX_ = -2AVIN _ = 2.5V29mΩ
LX_ Current-Limit ThresholdHigh-side sourcing and freewheeling7.08.39.6A
TA = +25°C+0.1VLX_ = 3.6VTA = +85°C-0.1
TA = +25°C-10LX_ Leakage CurrentVIN_ = 3.6V,
VEN_ = 0V
VLX_ = 0VTA = +85°C-0.1
RFSYNC = 10kΩ0.91.01.1LX_ Switching FrequencyRFSYNC = 4.75kΩ1.802.02.2MHz
LX_ Minimum Off-Time50ns
LX_ Minimum On-Time95ns
LX_ Maximum Duty CycleRFSYNC = 10kΩ9095%
Maximum LX_ Output Current3ARMS
ELECTRICAL CHARACTERISTICS (continued)(VIN_ = VVDD = VVDL = 3.3V, VFB_ = 0.5V, VSS_ = VREFIN= 600mV, PGND_ = GND, RFSYNC= 10kΩ, L = 0.47μH, CBST_= 0.1μF,
CSS_= 0.022μF, PWRGD_ not connected; TA= -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2)
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
ELECTRICAL CHARACTERISTICS (continued)(VIN_ = VVDD = VVDL = 3.3V, VFB_ = 0.5V, VSS_ = VREFIN= 600mV, PGND_ = GND, RFSYNC= 10kΩ, L = 0.47μH, CBST_= 0.1μF,
CSS_= 0.022μF, PWRGD_ not connected; TA= -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETERCONDITIONSMINTYPMAXUNITS
EN1, EN2EN_ Logic-Low0.7V
EN_ Logic-High1.7V
TA = +25°C-1+1EN_ Input CurrentVEN_ = 0 or 3.6V,
VVDD = 3.6VTA = +85°C0.01μA
SS1, SS2SS_ Charging CurrentVSS_ = 300mV5811μA
REFIN, SS2Discharge ResistanceIn shutdown or a fault condition335Ω
THERMAL SHUTDOWNThermal-Shutdown Threshold
(Independent Channels)+165°C
Thermal-Shutdown Hysteresis20°C
Note 2:All devices 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 3: VVDDmust equal VVDLand be equal to or greater than VIN_.
EFFICIENCY
vs. LOAD CURRENT WITH 3.3V INPUTMAX8855/MAX8855A toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010,000
VOUT_ = 2.5VVOUT_ = 1.2V
VOUT_ = 1.8V
EFFICIENCY
vs. LOAD CURRENT WITH 2.5V INPUTMAX8855/MAX8855A toc02
LOAD CURRENT (mA)
EFFICIENCY (%)
10010,000
VOUT_ = 1.2V
VOUT_ = 1.8V
SWITCHING FREQUENCY vs. RFSYNCMAX8855/MAX8855A toc03
RFSYNC (kΩ)
SWITCHING FREQUENCY (kHz)
Typical Operating Characteristics
(VIN1= VIN2= 3.3V, MAX8855/MAX8855A, circuit of Figure 6, TA= +25°C, unless otherwise noted.)
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
SWITCHING FREQUENCY
vs. TEMPERATUREMAX8855/MAX8855A toc04
AMBIENT TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
FEEDBACK VOLTAGE
vs. TEMPERATURE
MAX8855/MAX8855A toc05
AMBIENT TEMPERATURE (°C)
FEEDBACK VOLTAGE (mV)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX8855/MAX8855A toc06
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (nA)
IIN1 + IIN2 + IVDL + IVDD
LOAD TRANSIENTMAX8855/MAX8855A toc07
20µs/div
IOUT_
VOUT_
1A/div
100mV/div
1.8V OUTPUT
3.0A
1.5A1.5A
SWITCHING WAVEFORMSMAX8855/MAX8855A toc08
400ns/div
IL2
IL1
VLX2
VLX12V/div
2V/div
2A/div
2A/div
SOFT-START AND SHUTDOWNMAX8855/MAX8855A toc09
400µs/div
IIN2
VOUT2
VPWRGD2
VEN25V/div
2V/div
1V/div
1A/div
Typical Operating Characteristics (continued)(VIN1= VIN2= 3.3V, MAX8855/MAX8855A, circuit of Figure 6, TA= +25°C, unless otherwise noted.)
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
Typical Operating Characteristics (continued)(VIN1= VIN2= 3.3V, MAX8855/MAX8855A, circuit of Figure 6, TA= +25°C, unless otherwise noted.)
OUTPUT TRACKING (EN1 = EN2)MAX8855/MAX8855A toc13
1ms/div
DDR TRACKING 1.8V, 0.9V
VOUT1
VOUT2
VPWRGD1
VPWRGD2
1V/div
1V/div
2V/div
2V/div
EXTERNAL SYNCHRONIZATIONMAX8855/MAX8855A toc14
400ns/div
VLX1
VLX22V/div
2V/div
2V/div
PULSE GENERATOR SIGNAL. A 10kΩ RESISTOR
IS CONNECTED BETWEEN THE PULSE
GENERATOR AND FSYNC
STARTING INTO PREBIASED OUTPUTMAX8855/MAX8855A toc15
40µs/div
VOUT1
VEN1
VPWRGD1
OUTPUT PEAK CURRENT LIMIT
vs. OUTPUT VOLTAGEMAX8855/MAX8855A toc10
OUTPUT VOLTAGE (V)
OUTPUT PEAK CURRENT LIMIT (A)
SHORT CIRCUIT AND RECOVERY
MAX8855/MAX8855A toc11
1ms/div
IL1
VOUT1500mV/div
2A/div
OUTPUT SEQUENCING (EN2 = PWRGD1)MAX8855/MAX8855A toc12
1ms/div
VOUT1
VOUT2
VPWRGD1
VPWRGD2
1V/div
1V/div
2V/div
2V/div
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
Pin Description
PINNAMEFUNCTIONPWRGD1
Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when VREFIN ≥ 0.54V and
VFB1 ≥ 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VDD or IN1 is below UVLO, the
thermal shutdown is activated, or when VFB1 < 0.9 x VREFIN.REFIN
External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1
to use the internal reference. REFIN is discharged to GND through 335Ω when EN1 is low or regulator 1 is
shut down due to a fault condition.
3VDDSupply Voltage. Connect a 10Ω resistor from VDD to VDL and connect a 0.1μF capacitor from VDD to GND.GNDAnalog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes
together at a single point near the IC.N.C.No ConnectionVDLSupply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage
less than 3.6V. Connect a 1μF capacitor from VDL to the power ground plane.FSYNC
Frequency Set and Synchronization. Connect a 4.75kΩ to 20.5kΩ resistor from FSYNC to GND to set the
switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching.
RFSYNC = (T - 0.05μs) x (10kΩ/0.95μs), where T is the oscillator period.PWRGD2
Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when VSS2 ≥ 0.54V and VFB2
≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VDD or IN2 is below UVLO, the thermal
shutdown is activated, or when VFB2 < 0.9 x VSS2.SS2S oft- S tar t for Reg ul ator 2. C onnect a cap aci tor fr om S S 2 to GN D to set the soft- star t ti m e. S ee the S etti ng the S oft- tar t Ti m e secti on. S S 2 i s i nter nal l y p ul l ed l ow w i th 335Ω w hen E N 2 i s l ow or r eg ul ator 2 i s i n a faul t cond i ti on.FB2Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of VIN2. FB2 is high impedance when the IC is shut down.COMP2
Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external
compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally
pulled to GND when the output is shut down.EN2Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on
operation, connect EN2 to VDD.
13, 14IN2Power-Supply Input for Regulator 2. The voltage range is 2.35V (MAX8855A) to 3.6V. Connect two 10μF and
one 0.1μF ceramic capacitors from IN2 to PGND2.
15, 16, 17PGND2Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
18, 19LX2Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high
impedance when the IC is shut down.BST2
Bootstrap Connection for Regulator 2. Connect a 0.1μF capacitor from BST2 to LX2. BST2 is the supply for
the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX2 to BST2 and from VDL to BST2.BST1
Bootstrap Connection for Regulator 1. Connect a 0.1μF capacitor from BST1 to LX1. BST1 is the supply for
the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX1 to BST1 and from VDL to BST1.
22, 23LX1Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high
impedance when the IC is shut down.
24, 25, 26PGND1Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down Regulators
Pin Description (continued)
PINNAMEFUNCTION27, 28IN1P ow er - S up p l y Inp ut for Reg ul ator 1. The vol tag e r ang e i s 2.35V to 3.6V for the M AX 8855. The vol tag e r ang e i s
2.30V to 3.6V for the M AX 8855A. C onnect tw o 10μF and one 0.1μF cer am i c cap aci tor s fr om IN 1 to P G N D 1.EN1Enable Input for Regulator 1. Drive EN1 high to enable regulator 1, or low for shutdown. For always-on
operation, connect EN1 to VDD.COMP1
Compensation for Regulator 1. COMP1 is the output of the internal voltage-error amplifier. Connect external
compensation network from COMP1 to FB1. See the Compensation Design section. COMP1 is internally
pulled to GND when the output is shut down.FB1Feedback Input for Regulator 1. Connect FB1 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of VIN1. FB1 is high impedance when the IC is shut down.SS1
Soft-Start for Regulator 1. Connect a capacitor from SS1 to GND to set the startup time. See the Setting the
Soft-Start Time section. When E1 is disabled (pulled low), or regulator 1 is in shutdown mode due to a fault
condition, SS1 is internally pulled low with 335Ω resistor.EPExposed Pad. Connect the exposed pad to the power ground plane.
Detailed Description
PWM ControllerThe controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the control
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. It also contains the break-before-
make logic and the timing for charging the bootstrap
capacitors. The error signal from the voltage-error
amplifier is compared with the ramp signal generated
by the oscillator at the PWM comparator and, thus, the
required PWM signal is produced. The high-side switch
is turned on at the beginning of the oscillator cycle and
turns off when the ramp voltage exceeds the VCOMP_
signal or the current-limit threshold is exceeded. The
low-side switch is then turned on for the remainder of
the oscillator cycle. The two switching regulators oper-
ate at the same switching frequency with 180°phase
shift to reduce the input-capacitor ripple current
requirement. Figure 1 shows the MAX8855/MAX8855A
functional diagram.
Current LimitThe MAX8855/MAX8855A provide both peak and valley
current limitsto achieve robust short-circuit protection.
During the high-side MOSFET’s on-time, if the drain-
source current reaches the peak current-limit threshold
(specified in the Electrical Characteristics table), the
high-side MOSFET turns off and the low-side MOSFET
turns on, allowing the current to ramp down. At the next
clock, the high-side MOSFETis turned on only if the
Otherwise, the PWM cycle is skipped to continue ramp-
ing down the inductor current. When the inductor current
stays above the valley current limit for 12μs and the FB_
is below 0.7 x VREFIN, the regulator enters hiccup mode.
During hiccup mode, the SS_ capacitor is discharged to
zero and the soft-start sequence begins after a predeter-
mined time period.
Undervoltage Lockout (UVLO)When the VDDsupply voltage drops below the falling
undervoltage threshold (typically 1.9V), the MAX8855/
MAX8855A enter the undervoltage lockout mode
(UVLO). UVLO forces the devices to a dormant state
until the input voltage is high enough to allow the
device to function reliably. In UVLO, LX_ nodes of both
regulators are in the high-impedance state. PWRGD1
and PWRGD2 are forced low in UVLO. When VVDD
rises above the rising undervoltage threshold (typically
2V), the IC powers up normally as described in the
Startup and Sequencingsection.
The UVLO circuitry also monitors the IN1 and IN2 sup-
plies. When the IN_ voltage drops below the falling
undervoltage threshold (typically 1.9V), the correspond-
ing regulator shuts down, and corresponding PWRGD_
goes low. The regulator powers up when VIN_rises
above the rising undervoltage threshold (typically 2V).
Power-Good Output (PWRGD_)PWRGD1 and PWRGD2 are open-drain outputs that
indicate when the corresponding output is in regulation.
PWRGD1 is high impedance when VREFIN≥0.54V and
VFB1≥0.9 x VREFIN. PWRGD1 is low when VREFIN <
0.54V, EN1 is low, VVDDor VIN1is below VUVLO, the
thermal-overload protection is activated, or when VFB1
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down RegulatorsFigure 1. Functional Diagram
VDD
PGND1
LX1
IN1
VDL
BST1
EN1
EN2
SS2
REFIN
FB1
COMP1
SS1
SHUTDOWN
CONTROL
UVLO
CIRCUITRY
CURRENT-LIMIT
COMPARATOR
ILIM
THRESHOLD
ILIM
THRESHOLD
BST CAP
CHARGING
SWITCH
VDDBIAS
GENERATOR
VOLTAGE
REFERENCE
REF
FROM SS2 (0.6V)
SOFT-START 1
ERROR
AMPLIFIER
PWM
COMPARATOR
SOFT-START 2
VDL
FB2
ERROR
AMPLIFIER
PWM
COMPARATOR
SHDN
COMP LOW
DETECTOR
COMP2
COMP LOW
DETECTOR
IN1IN2
CONTROL
LOGIC
CLOCK
THERMAL
SHUTDOWN1
EN1
LX1
IN1
PGND2
FSYNC
LX2
IN2
BST2
CURRENT-LIMIT
COMPARATOR
BST CAP
CHARGING
SWITCH+
CONTROL
LOGIC
CLOCKTHERMAL
SHUTDOWN2
EN2
PWRGD1
LX2
IN2
OSCILLATOR
GND
CLOCK
FB1
0.9 x VREFIN
REFIN
REF
540mV
SHDN+
PWRGD2
FB2
0.9 x VSS2
SS2
540mV
THERMAL
SHUTDOWNTHERMAL
SHUTDOWN2
THERMAL
SHUTDOWN1
MAX8855/MAX8855A
The power-good, open-drain output for regulator 2
(PWRGD2) is high impedance when VSS2 ≥0.54V and
VFB2 ≥0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V,
EN2 is low, VVDDor VIN2is below VUVLO, the thermal-over-
load protection is activated, or when VFB2< 0.9 x VSS2.
External Reference Input (REFIN)The MAX8855/MAX8855A have an external reference
input. Connect an external reference between 0 and
VVDD - 1.6V to REFIN to set the FB1 regulation voltage.
To use the internal 0.6V reference, connect REFIN to
SS1. When the IC is shut down, REFIN is pulled to GND
through 335Ω.
Startup and SequencingThe MAX8855/MAX8855A feature separate enable
inputs (EN1 and EN2) for the two regulators. Driving
EN_ high enables the corresponding regulator; driving
EN_ low turns the regulator off. Driving both EN1 and
EN2 low puts the IC in low-power shutdown mode,
reducing the supply current typically to 30nA. The
MAX8855/MAX8855A regulators power up when the fol-
lowing conditions are met (see Figure 2):EN_ is logic-high.
•VVDDis above the UVLO threshold.
•VIN_is above the UVLO threshold.The internal reference is powered.The IC is not in thermal overload (TJ < +165°C).
Once these conditions are met, the MAX8855/
MAX8855A begin soft-start. FB2 regulates to the volt-
age at SS2. During soft-start, the SS2 capacitor is
charged with a constant 8μA current source so that its
voltage ramps up for the soft-start time. See the Setting
the Soft-Start Timesection to select the SS2 capacitor
for the desired soft-start time. FB1 regulates to the volt-
age at REFIN. Connect REFIN to SS1 to use the internal
MAX8855/MAX8855A
Dual, 5A, 2MHz Step-Down RegulatorsFigure 2. Startup Control Diagram
UVLO
UVLO
THERM
SHDN
THERM
SHDN
REF
BIAS
GEN
REF
RDYUVLO
VDD
RRUVB
RRUVB
RRUVB
EN1
EN2
REG1 ON
REG2 ONUVLO
UVLO
TLIM
TLIM
IN1
IN2
Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms
EN1
SS2
PWRGD1EN1
OUT1
OUT2
PWRGD2
EN2
SS1
PWRGD2
VDD
REFIN
EN2
EN2
PWRGD1
10kΩ
10kΩEN1
