MAX8833ETJ+-MAX8833ETJ+T Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX8833ETJ+-MAX8833ETJ+T
Dual, 3A, 2MHz Step-Down Regulator
General Description
The MAX8833 high-efficiency, dual step-down regulator
is capable of delivering up to 3A at each output. The
device operates from a 2.35V to 3.6V supply, and pro-
vides output voltages from 0.6V to 0.9 x VIN, making it
ideal for on-board point-of-load applications. Total output
error is less than ±1% over load, line, and temperature.
The MAX8833 operates in PWM mode with a switching
frequency ranging from 0.5MHz to 2MHz, set by an
external resistor. It can also be synchronized to an
external clock in the same frequency range. Two inter-
nal switching regulators operate 180°out-of-phase to
reduce the input ripple current, and consequently
reduce the required input capacitance. The high
operating frequency minimizes the size of external
components. High efficiency, internal dual-nMOS
design keeps the board cool under heavy loads. The
voltage-mode control architecture and the high-band-
width (> 15MHz typ) voltage-error amplifier allow a type
III compensation scheme to be utilized to achieve fast
response under both line and load transients, and also
allow for ceramic output capacitors.
Programmable soft-start reduces input inrush current.
Two enable inputs allow the turning on/off of each out-
put individually, resulting in great flexibility for system-
level designs. A reference input is provided to facilitate
output-voltage tracking applications. The MAX8833 is
available in a 32-pin thin QFN (5mm x 5mm) package
with 0.8mm max height.
Applications
ASIC/CPU/DSP Power Supplies
DDR Power Supplies
Set-Top Box Power Supplies
Printer Power Supplies
Network Power Supplies
Features35mΩOn-Resistance Internal MOSFETsDual, 3A, PWM Step-Down RegulatorsFully Protected Against Overcurrent,Short Circuit, and Overtemperature±1% Output Accuracy over Load, Line,and TemperatureOperates from 2.35V to 3.6V SupplyREFIN on One Channel for Tracking orExternal ReferenceIntegrated Boost DiodesAdjustable Output from 0.6V to 0.9 x VINSoft-Start Reduces Inrush Supply Current0.5MHz to 2MHz Adjustable Switching,or FSYNC InputAll-Ceramic-Capacitor Design180°Out-of-Phase Operation Reduces InputRipple CurrentIndividual Enable Inputs and PWRGD OutputsSafe-Start into Prebiased OutputAvailable in 5mm x 5mm Thin QFN PackageSink/Source Current in DDR Applications
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
Ordering Information
19-0725; Rev 2; 4/09
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
EVALUATION KITAVAILABLE
PARTTEMP RANGEPIN-PACKAGE
MAX8833ETJ+-40°C to +85°C32 Thin QFN-EP*
Pin Configuration appears at end of data sheet.
FB2
EN2
COMP2
LX2
BST2
GND
PGND2
INPUT1
2.35V TO 3.6V
EN1
BST1
COMP1
FB1
PGND1
LX1
IN1IN2
TYPE III
COMPENSATION
OUTPUT1
1.2V / 3A
INPUT2
2.35V TO 3.6V
PWRGD1PWRGD2
OFF
MAX8833
TYPE III
COMPENSATION
OUTPUT2
1.5V / 3A
OFF
Typical Operating Circuit
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN_ = VVDD = VVDL = 3.3V, VFB_ = 0.5V, VSS_ = VREFIN= 600mV, PGND_ = GND, RFSYNC= 10kΩ, L = 0.47μH, CBST_= 0.1μF,
CSS_= 0.022μF, PWRGD_ not connected; TA= -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN_, LX_, VDD, VDL, PWRGD_ to GND..................-0.3V to +4.5V
VDD, VDL to IN_.....................................................-0.3V to +4.5V
EN_, SS_, COMP_, FB_, REFIN, FSYNC to GND ......-0.3V to the
lower of (VVDD+ 0.3V) and (VVDL+ 0.3V)
Continuous LX_ Current (Note 1)...................................5.5ARMS
BST_ to LX_...........................................................-0.3V to +4.5V
PGND_ to GND......................................................-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (5mm x 5mm)
(derate 34.5mW/°C above +70°C)..........................2758.6mW
Operating Ambient Temperature Range.............-40°C to +85°C
Operating Junction Temperature Range...........-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
θJC...................................................................................1.7°C/W
PARAMETERCONDITIONSMINTYPMAXUNITS
IN1, IN2, VDL, VDD
IN_, VDL, and VDD Voltage Range(Note 3)2.353.60V
VIN_ = 2.5V1.93.5IN_ Supply Current1MHz switching, no loadVIN_ = 3.3V2.85mA
VVDD = 2.5V7.2VDD + VDL Supply Current1MHz switching, VDD = VDLVVDD = 3.3V1015mA
TA = +25°C11Shutdown Supply Current
(IIN1 + IIN2 + IVDD + IVDL)
VIN_ = VVDD = VVDL = VBST_
- VLX_ = 3.6V, VEN_ = 0VTA = +85°C0.3μA
Rising2.02.2IN_, VDD Undervoltage Lockout Threshold
UVLO Monitors VDD, IN1, and IN2Falling1.81.9V
IN_, VDD Undervoltage Lockout Deglitch2μs
BST1, BST2
TA = +25°C2Shutdown BST_ CurrentV IN _ = V V D D = V V D L = V BS T _ =
3.6V , V E N _ = 0V , V LX _ = 0 or 3.6V TA = +85°C0.02μA
COMP1, COMP2
COMP_ Clamp Voltage, HighVVDD = VIN_= 2.3V to 3.6V, VFB_ = 0.7V1.802.002.25V
COMP_ Slew Rate1.40V/μs
COMP_ Shutdown ResistanceFrom COMP_ to GND, VEN_ = 0V725Ω
ERROR AMPLIFIER
FB_ Regulation VoltageVCOMP_ = 1V to 2VV V D D = V I N _ = 2.5V to 3.3V 0.5940.6000.606V
FB_ Regulation Voltage with
External ReferenceVCOMP_ = 1V to 2VV V D D = V I N _ = 2.5V to 3.3V 0.5940.6000.606V
Error Amplifier Common-Mode-Input Range0VVDD -
1.6V
Error Amplifier Maximum Output Current1mA
TA = +25°C40300FB_ Input Bias CurrentVFB_ = 0.605VTA = +85°C37nA
Note 1:LX_ have internal clamp diodes to PGND_ and IN_. Applications that forward bias these diodes should take care not to
exceed the IC’s package power-dissipation limits.
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
PARAMETERCONDITIONSMINTYPMAXUNITS
REFIN, SS2
TA = +25°C90500REFIN Input Bias CurrentVFB_ = 0.610VTA = +85°C65nA
VVDD = 2.35V to 2.6V0VVDD -
REFIN Common-Mode Range
VVDD = 2.6V to 3.6V0VVDD -
LX1, LX2 (All Pins Combined)
VIN_ = VBST_ - VLX_ =4055LX_ On-Resistance, HighILX_ = -2AVIN_ = VBST_ - VLX_ =42mΩ
VIN_ = 3.3V3554LX_ On-Resistance, LowILX_ = -2AVIN_ = 2.5V37mΩ
LX_ Current-Limit ThresholdHigh-side sourcing and freewheeling4.65.56.4A
TA = +25°C10VLX_ = 3.6VTA = +85°C-0.1
TA = +25°C-10LX_ Leakage CurrentVIN_ = 3.6V,
VEN_ = 0V
VLX_ = 0VTA = +85°C-0.1
RFSYNC = 10kΩ0.91.01.1LX_ Switching FrequencyRFSYNC = 4.75kΩ1.802.02.2MHz
LX_ Minimum Off-Time50ns
LX_ Minimum On-Time95ns
LX_ Maximum Duty CycleRFSYNC = 10kΩ9095%
Maximum LX_ Output Current3ARMS
EN1, EN2
EN_ Logic-Low0.7V
EN_ Logic-High1.7V
TA = +25°C-1+1EN_ Input CurrentVEN_ = 0 or 3.6V,
VVDD = 3.6VTA = +85°C0.01μA
SS1, SS2
SS_ Charging CurrentVSS_ = 300mV5811μA
REFIN, SS2
Discharge ResistanceIn shutdown or a fault condition335Ω
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
(Independent Channels)+165°C
Thermal-Shutdown Hysteresis20°C
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VVDD = VVDL = 3.3V, VFB_ = 0.5V, VSS_ = VREFIN= 600mV, PGND_ = GND, RFSYNC= 10kΩ, L = 0.47μH, CBST_= 0.1μF,
CSS_= 0.022μF, PWRGD_ not connected; TA= -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2)
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VVDD = VVDL = 3.3V, VFB_ = 0.5V, VSS_ = VREFIN= 600mV, PGND_ = GND, RFSYNC= 10kΩ, L = 0.47μH, CBST_= 0.1μF,
CSS_= 0.022μF, PWRGD_ not connected; TA= -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETERCONDITIONSMINTYPMAXUNITS
FSYNC
FSYNC Capture Range2502500kHz
FSYNC Input Threshold1.31.51.7V
FSYNC Output Voltage0.9751.01.025V
Phase Shift from LX1 to LX2180D eg r ees
PWRGD1, PWRGD2
PWRGD1 Threshold VoltageVFB1 rising with respect to VREFIN,
and VREFIN > 540mV typ889092%
PWRGD2 Threshold VoltageVFB2 rising with respect to VSS2,
and VSS2 > 540mV typ889092%
PWRGD_ Hysteresis2.6%
PWRGD_ Falling Edge Deglitch354555μs
PWRGD_ Output-Low VoltageIPWRGD_ = 4mA0.030.15V
TA = +25°C1PWRGD_ Leakage CurrentVPWRGD_ = 3.6V,
VFB_ = 0.9VTA = +85°C0.01μA
Note 2:All devices 100% production tested at +25°C. Limits over temperature are guaranteed by design.
Note 3: VVDDmust equal VVDLand be equal to or greater than VIN_.
EFFICIENCY
vs. LOAD CURRENT WITH 3.3V INPUT
MAX8833 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010,000
VOUT_ = 2.5VVOUT_ = 1.2V
VOUT_ = 1.8V
EFFICIENCY
vs. LOAD CURRENT WITH 2.5V INPUT
MAX8833 toc02
LOAD CURRENT (mA)
EFFICIENCY (%)
10010,000
VOUT_ = 1.2V
VOUT_ = 1.8V
SWITCHING FREQUENCY vs. RFSYNC
MAX8833 toc03
RFSYNC (kΩ)
SWITCHING FREQUENCY (kHz)
Typical Operating Characteristics
(VIN1= VIN2= 3.3V. MAX8833, circuit of Figure 6, TA= +25°C, unless otherwise noted.)
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
SWITCHING FREQUENCY
vs. TEMPERATURE
MAX8833 toc04
AMBIENT TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
FEEDBACK VOLTAGE
vs. TEMPERATURE
MAX8833 toc05
AMBIENT TEMPERATURE (°C)
FEEDBACK VOLTAGE (mV)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX8833 toc06
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (nA)
IIN1 + IIN2 + IVDL + IVDD
LOAD TRANSIENT
MAX8833 toc07
20μs/div
IOUT_
VOUT_
1A/div
100mV/div
1.8V OUTPUT
3.0A
1.5A1.5A
SWITCHING WAVEFORMS
MAX8833 toc08
400ns/div
IL2
IL1
VLX2
VLX12V/div
2V/div
2A/div
2A/div
SOFT-START AND SHUTDOWN
MAX8833 toc09
400μs/div
IIN_
VOUT2
VPWRGD_
VEN25V/div
2V/div
1V/div
1A/div
Typical Operating Characteristics (continued)
(VIN1= VIN2= 3.3V. MAX8833, circuit of Figure 6, TA= +25°C, unless otherwise noted.)
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
Typical Operating Characteristics (continued)
(VIN1= VIN2= 3.3V. MAX8833, circuit of Figure6, TA= +25°C, unless otherwise noted.)
OUTPUT TRACKING (EN1 = EN2)
MAX8833 toc13
1ms/div
DDR TRACKING 1.8V, 0.9V
VOUT1
VOUT2
VPWRGD1
VPWRGD2
1V/div
1V/div
2V/div
2V/div
EXTERNAL SYNCHRONIZATION
MAX8833 toc14
400ns/div
VLX1
VLX22V/div
2V/div
2V/div
PULSE GENERATOR SIGNAL. A 10kI RESISTOR
IS CONNECTED BETWEEN THE PULSE
GENERATOR AND FSYNC
OUTPUT PEAK CURRENT LIMIT
vs. OUTPUT VOLTAGE
MAX8833 toc10
OUTPUT VOLTAGE (V)
OUTPUT PEAK CURRENT LIMIT (A)
SHORT CIRCUIT AND RECOVERY
MAX8833 toc11
1ms/div
IL1
VOUT1500mV/div
2A/div
OUTPUT SEQUENCING (EN2 = PWRGD1)
MAX8833 toc12
1ms/div
VOUT1
VOUT2
VPWRGD1
VPWRGD2
1V/div
1V/div
2V/div
2V/div
STARTING INTO PREBIASED OUTPUT
MAX8833 toc15
40μs/div
VOUT1
VEN1
VPWRGD12V/div
500mV/div
2V/div
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
Pin Description
PINNAMEFUNCTIONPWRGD1
Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when VREFIN ≥ 0.54V and
VFB1 ≥ 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VDD or IN1 is below UVLO, the
thermal shutdown is activated, or when VFB1 < 0.9 x VREFIN.REFIN
External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1
to use the internal reference. REFIN is discharged to GND through 335Ω when EN1 is low or regulator 1 is
shut down due to a fault condition.
3VDDSupply Voltage. Connect a 10Ω resistor from VDD to VDL and connect a 0.1μF capacitor from VDD to GND.GNDAnalog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes
together at a single point near the IC.N.C.No ConnectionVDLSupply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage
less than 3.6V. Connect a 1μF capacitor from VDL to the power ground plane.FSYNC
Frequency Set and Synchronization. Connect a 4.75kΩ to 20.5kΩ resistor from FSYNC to GND to set
switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching.
RFSYNC = (T - 0.05μs) x (10kΩ/0.95μs), where T is the oscillator period.PWRGD2
Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when VSS2 ≥ 0.54V and VFB2
≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VDD or IN2 is below UVLO, the thermal
shutdown is activated, or when VFB2 < 0.9 x VSS2.SS2S oft- S tar t for Reg ul ator 2. C onnect a cap aci tor fr om S S 2 to GN D to set the soft- star t ti m e. S ee the S etti ng the S oft- tar t Ti m e secti on. S S 2 i s i nter nal l y p ul l ed l ow w i th 335Ω w hen E N 2 i s l ow or r eg ul ator 2 i s i n a faul t cond i ti on.FB2Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of VIN2. FB2 is high impedance when the IC is shut down.COMP2
Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external
compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally
pulled to GND when the output is shut down.EN2Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on
operation, connect EN2 to VDD.
13, 14IN2Power-Supply Input for Regulator 2. The voltage range is 2.35V to 3.6V. Connect two 10μF and one 0.1μF
ceramic capacitors from IN2 to PGND2.
15, 16, 17PGND2Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
18, 19LX2Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high
impedance when the IC is shut down.BST2
Bootstrap Connection for Regulator 2. Connect a 0.1μF capacitor from BST2 to LX2. BST2 is the supply for
the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX2 to BST2 and from VDL to BST2.BST1
Bootstrap Connection for Regulator 1. Connect a 0.1μF capacitor from BST1 to LX1. BST1 is the supply for
the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX1 to BST1 and from VDL to BST1.
22, 23LX1Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high
impedance when the IC is shut down.
24, 25, 26PGND1Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
Pin Description (continued)
PINNAMEFUNCTION
27, 28IN1Power-Supply Input for Regulator 1. The voltage range is 2.35V to 3.6V. Connect two 10μF and one 0.1μF
ceramic capacitors from IN1 to PGND1.EN1Enable Input for Regulator 1. Drive EN1 high to enable regulator 1, or low for shutdown. For always-on
operation, connect EN1 to VDD.COMP1
Compensation for Regulator 1. COMP1 is the output of the internal voltage-error amplifier. Connect external
compensation network from COMP1 to FB1. See the Compensation Design section. COMP1 is internally
pulled to GND when the output is shut down.FB1Feedback Input for Regulator 1. Connect FB1 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of VIN1. FB1 is high impedance when the IC is shut down.SS1
Soft-Start for Regulator 1. Connect a capacitor from SS1 to GND to set the startup time. See the Setting the
Soft-Start Time section. When E1 is disabled (pulled low), or regulator 1 is in shutdown mode due to a fault
condition, SS1 is internally pulled low with 335Ω resistor.EPExposed Pad. Connect the exposed pad to the power ground plane.
Detailed Description
PWM Controller
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the control
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. It also contains the break-before-
make logic and the timing for charging the bootstrap
capacitors. The error signal from the voltage-error ampli-
fier is compared with the ramp signal generated by the
oscillator at the PWM comparator and, thus, the required
PWM signal is produced. The high-side switch is turned
on at the beginning of the oscillator cycle and turns off
when the ramp voltage exceeds the VCOMP_signal or
the current-limit threshold is exceeded. The low-side
switch is then turned on for the remainder of the oscilla-
tor cycle. The two switching regulators operate at the
same switching frequency with 180°phase shift to
reduce the input-capacitor ripple current requirement.
Figure 1 shows the MAX8833 functional diagram.
Current Limit
The MAX8833 provides both peak and valley current limits
to achieve robust short-circuit protection. During the
high-side MOSFET’s on-time, if the drain-source current
reaches the peak current-limit threshold (specified in
the Electrical Characteristics table), the high-side MOS-
FET turns off and the low-side MOSFET turns on, allow-
ing the current to ramp down. At the next clock, the
high-side MOSFETis turned on only if the inductor cur-
cycle is skipped to continue ramping down the inductor
current. When the inductor current stays above the valley
current limit for 12μs and the FB_ is below 0.7 x VREFIN,
the regulator enters hiccup mode. During hiccup mode,
the SS_ capacitor is discharged to zero and the soft-start
sequence begins after a predetermined time period.
Undervoltage Lockout (UVLO)
When the VDDsupply voltage drops below the falling
undervoltage threshold (typically 1.9V), the MAX8833
enters its undervoltage lockout mode (UVLO). UVLO
forces the device to a dormant state until the input voltage
is high enough to allow the device to function reliably. In
UVLO, LX_ nodes of both regulators are in the high-
impedance state. PWRGD1 and PWRGD2 are forced low
in UVLO. When VVDDrises above the rising undervoltage
threshold (typically 2V), the IC powers up normally as
described in the Startup and Sequencingsection.
The UVLO circuitry also monitors the IN1 and IN2 sup-
plies. When the IN_ voltage drops below the falling
undervoltage threshold (typically 1.9V), the correspond-
ing regulator shuts down, and corresponding PWRGD_
goes low. The regulator powers up when VIN_rises
above the rising undervoltage threshold (typically 2V).
Power-Good Output (PWRGD_)
PWRGD1 and PWRGD2 are open-drain outputs that
indicate when the corresponding output is in regulation.
PWRGD1 is high impedance when VREFIN≥0.54V and
VFB1≥0.9 x VREFIN. PWRGD1 is low when VREFIN <
0.54V, EN1 is low, VVDDor VIN1is below VUVLO, the
thermal-overload protection is activated, or when VFB1
< 0.9 x VREFIN.
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
Figure 1. Functional Diagram
VDD
PGND1
LX1
IN1
VDL
BST1
EN1
EN2
SS2
REFIN
FB1
COMP1
SS1
SHUTDOWN
CONTROL
UVLO
CIRCUITRY
CURRENT-LIMIT
COMPARATOR
ILIM
THRESHOLD
ILIM
THRESHOLD
BST CAP
CHARGING
SWITCH
VDDBIAS
GENERATOR
VOLTAGE
REFERENCE
REF
FROM SS2 (0.6V)
SOFT-START 1
ERROR
AMPLIFIER
PWM
COMPARATOR
SOFT-START 2
VDL
FB2
ERROR
AMPLIFIER+
PWM
COMPARATOR
SHDN
COMP LOW
DETECTOR
COMP2
COMP LOW
DETECTOR
IN1IN2
CONTROL
LOGIC
CLOCK
THERMAL
SHUTDOWN1
EN1
LX1
IN1
PGND2
FSYNC
LX2
IN2
BST2
CURRENT-LIMIT
COMPARATOR
BST CAP
CHARGING
SWITCH
CONTROL
LOGIC
CLOCKTHERMAL
SHUTDOWN2
EN2
PWRGD1
LX2
IN2
OSCILLATOR
GND
CLOCK
FB1
0.9 x VREFIN
REFIN
REF
540mV
SHDN+
PWRGD2
FB2
0.9 x VSS2
SS2
540mV
THERMAL
SHUTDOWNTHERMAL
SHUTDOWN2
THERMAL
SHUTDOWN1
MAX8833
The power-good, open-drain output for regulator 2
(PWRGD2) is high impedance when VSS2 ≥0.54V and
VFB2 ≥0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V,
EN2 is low, VVDDor VIN2is below VUVLO, the thermal-over-
load protection is activated, or when VFB2< 0.9 x VSS2.
External Reference Input (REFIN)
The MAX8833 has an external reference input. Connect
an external reference between 0 and VVDD - 1.6V to
REFIN to set the FB1 regulation voltage. To use the inter-
nal 0.6V reference, connect REFIN to SS1. When the IC
is shut down, REFIN is pulled to GND through 335Ω.
Startup and Sequencing
The MAX8833 features separate enable inputs (EN1
and EN2) for the two regulators. Driving EN_ high
enables the corresponding regulator; driving EN_ low
turns the regulator off. Driving both EN1 and EN2 low
puts the IC in low-power shutdown mode, reducing the
supply current typically to 30nA. The MAX8833 regula-
tors power up when the following conditions are met
(see Figure 2):EN_ is logic-high.
•VVDDis above the UVLO threshold.
•VIN_is above the UVLO threshold.The internal reference is powered.The IC is not in thermal overload (TJ < +165°C).
Once these conditions are met, the MAX8833 begins
soft-start. FB2 regulates to the voltage at SS2. During
soft-start, the SS2 capacitor is charged with a constant
8μA current source so that its voltage ramps up for the
soft-start time. See the Setting the Soft-Start Timesec-
tion to select the SS2 capacitor for the desired soft-start
time. FB1 regulates to the voltage at REFIN. Connect
REFIN to SS1 to use the internal reference with soft-
start time set independently by the SS1 capacitor (see
Figure 3a).
MAX8833
Dual, 3A, 2MHz Step-Down Regulator
Figure 2. Startup Control Diagram
UVLO
UVLO
THERM
SHDN
THERM
SHDN
REF
BIAS
GEN
REF
RDYUVLO
VDD
RRUVB
RRUVB
RRUVB
EN1
EN2
REG1 ON
REG2 ONUVLO
UVLO
TLIM
TLIM
IN1
IN2
Figure3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms
EN1
SS2
PWRGD1EN1
OUT1
OUT2
PWRGD2
EN2
SS1
PWRGD2
VDD
REFIN
EN2
EN2
PWRGD1
10kΩ
10kΩEN1

Partno	Mfg	Dc	Qty	Available	Descript
MAX8833ETJ+	MAXIM	N/a	120	avai	Dual, 3A, 2MHz Step-Down Regulator
MAX8833ETJ+ \|MAX8833ETJ	MAXIN	N/a	305	avai	Dual, 3A, 2MHz Step-Down Regulator
MAX8833ETJ+T	N/A	N/a	2500	avai	Dual, 3A, 2MHz Step-Down Regulator