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MAX8809AETL+-MAX8810AETM+T
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM Controllers with Integrated Dual MOSFET Drivers
19-3886; Rev 1; 8/06
General DescriptionThe MAX8809A/MAX8810A synchronous, 2-/3-/4-
phase, step-down, current-mode controllers with inte-
grated dual-phase MOSFET drivers provide flexible
solutions that fully comply with Intel®VRD11/VRD10
and AMD K8 Rev F CPU core supplies. The flexible
design supplies load currents up to 150A for low-volt-
age CPU core power requirements.
A tri-state SEL input is available to configure the VID
logic for either the Intel VRD11/VRD10 or AMD K8 Rev F
applications. An enable input (EN) is available to dis-
able the IC. True-differential remote output-voltage
sensing enables precise regulation at the load by elimi-
nating the effects of trace impedance in the output and
return paths. A high-accuracy DAC combined with pre-
cision current-sense amplifiers and droop control
enable the MAX8809A/MAX8810A to meet the most
stringent tolerance requirements of new-generation
high-current CPUs. These ICs use either integral or volt-
age-positioning feedback control to achieve high out-
put-voltage accuracy.
The COMP input allows for either positive or negative
voltage offsets from the VID code voltage. A power-
good signal (VRREADY) is provided for startup
sequencing and fault annunciation. The SS/OVP pin
enables the programming of the soft-start period, and
provides an indication of an overvoltage condition. A
soft-stop feature prevents negative voltage spikes on
the output at turn-off, eliminating the need for an exter-
nal Schottky clamp diode.
The MAX8809A/MAX8810A incorporate a proprietary
“rapid active average” current-mode control scheme for
fast and accurate transient-response performance, as
well as precise load current sharing. Either the inductor
DCR or a resistive current-sensing element is used for
current sensing. When used with DCR sensing, rapid
active current averaging (RA2) eliminates the tolerance
effects of the inductance and associated current-sens-
ing components, providing superior phase current
matching, accurate current limit, and precise load-line.
The MAX8809A operates as a single-chip, 2-phase
solution with integrated drivers. It also provides a 3rd-
phase PWM output and easily supports 3-phase design
by adding the MAX8552 high-performance driver. The
MAX8810A enables up to 4-phase designs by adding
the MAX8523 high-performance dual driver for a com-
pact 2-chip solution.
FeaturesVRD11/VRD10 and K8 Rev F Compliant±0.35% Initial Output Voltage AccuracyDual Integrated Drivers with Integrated Bootstrap
DiodesUp to 26V Input VoltageAdaptive Shoot-Through ProtectionSoft-Start, Soft-Stop, VRREADY OutputFast Load Transient ResponseIndividual Phase, Fully Temperature-
Compensated Cycle-by-Cycle Average Current
LimitCurrent Foldback at Short CircuitVoltage Positioning or Integral FeedbackDifferential Remote Voltage SensingProgrammable Positive and Negative Offset
Voltages150kHz to 1.2MHz Switching Frequency per PhaseNTC-Based, Temperature-Independent Load LinePrecise Phase Current SharingProgrammable Thermal-Monitoring Output
(VRHOT)6A Peak MOSFET Drivers0.3Ω/0.85ΩLow-Side, 0.8Ω/1.1ΩHigh-Side
Drivers (typ)40-Pin and 48-Pin Thin QFN Packages
ApplicationsDesktop PCs
Servers, Workstations
Desknote and LCD PCs
Voltage-Regulator Modules
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Ordering Information+Denotes lead-free package.
Note: All parts are specified in the -40°C to +85°C extendedtemperature range.
EVALUATION KIT
AVAILABLE
PART PIN-
PACKAGE
PKG
CODEFUNCTION
MAX8809AETL+ 40 Thin QFN
5mm x 5mmT4055-12-/3-phase
MAX8810AETM+ 48 Thin QFN
6mm x 6mmT4866-12-/3-/4-phase
Pin Configurations appear at end of data sheet.Intel is a registered trademark of Intel Corp.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩto GND, RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 118kΩto GND, VCS_+= VCS_-= 1V,
PWM_ = unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
REF, COMP, SS/OVP, OSC, NTC, VRTSET,
RS+, RS-, PWM_ to GND.......................-0.3V to (VCC+ 0.3V)
CS_+, CS_-, VID_, BUF, EN, ILIM, SEL, VRREADY,
VRHOT, VCCto GND............................................-0.3V to +6V
BST_ to PGND_......................................................-0.3V to +35V
LX_ to PGND_............................................................-1V to +28V
BST_ to VL_...............................................................-1V to +30V
DH_ to PGND_.........................................-0.3V to (VBST_ + 0.3V)
DH_, BST_ to LX_.....................................................-0.3V to +7V
VL_to PGND_ ..........................................................-0.3V to +7V
DL_ to PGND_ ..........................................-0.3V to (VVL_+ 0.3V)
PGND_ to GND......................................................-0.3V to +0.3V
CS_+ to CS_-.........................................................-0.3V to +0.3V
DH_, DL_ Current ....................................................±200mARMS
VL_ to BST_ Diode Current...........................................50mARMS
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 5mm x 5mm
(derate 35.7mW/°C above +70°C)..........................2857.1mW
48-Pin Thin QFN 6mm x 6mm
(derate 37mW/°C above +70°C)................................2963mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERCONDITIONSMINTYPMAXUNITSVCC Operating Range4.55.5V
Rising4.04.254.5VCC UVLO Trip LevelFalling3.74.04.3V
VCC Shutdown Supply CurrentVCC < 3.75V0.35mA
VCC Standby Supply CurrentVEN = 0V0.5mA
VCC Operating Supply CurrentVRS+ - VRS- = 1.0V, no switching, VDAC = 1.0V (Note 1)13mA
Thermal ShutdownTemperature rising, hyster esi s = 25° C ( typ ) +160°C
INTERNAL REFERENCE (REF)Output VoltageIREF = -100µA1.9922.0002.008V
Output Regulation (Sourcing)VCC = 4.5V at IREF = -500µA to VCC = 5.5V at
IREF = -100µA-0.05+0.05%
Output Regulation (Sinking)VCC = 4.5V at IREF = +100µA to VCC = 5.5V at
IREF = +500µA-0.2+0.2%
Reference UVLO Trip LevelRising (100mV typ hysteresis)1.84V
BUF REFERENCEBUF Regulation VoltageIBUF = 0A0.991.01.01V
BUF Output RegulationVCC = 4.5V at IBUF = +100µA to VCC = 5.5V at
IBUF = +500µA-0.25+0.25%
SOFT-STARTEN Startup Delay (TD1)From EN rising to VOUT rising1.62.22.8ms
Soft-Start Period Range (TD2)12kΩ < RSS/OVP < 90.9kΩ0.56.5ms
Soft-Start ToleranceRSS/OVP = 56kΩ2.253.003.75ms
Intel Boot-Level Duration (TD3)SEL = GND or SEL = VCC175250350µs
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩto GND, RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 118kΩto GND, VCS_+= VCS_-= 1V,
PWM_ = unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITS
VOLTAGE REGULATIONRS+ Input Bias CurrentVRS+ = 1V0.11µA
RS- Input Bias CurrentVRS- = 0.2V0.11µA
Output Voltage Initial AccuracyVDAC = 1V (Note 1)-0.35+0.35%
TA = +25°C to +85°C-3.5+3.5Droop AccuracyVDAC = 1V (Note 1),
RNTC = 10kΩTA = -5°C to +85°C-5.5+5.5%
gMV Amplifier Transconductance1.942.002.06mS
gMV Gain Bandwidth Product5MHz
Comp Output CurrentVDAC - VRS+ = 200mV (Note 1)385µA
CURRENT LIMITAverage Current-Limit Trip Level
AccuracyVILIM = 1.5V-6+6%
ILIM Input Bias Current0.011µA
ILIM Default Program LevelVILIM > VCC - 0.2V1.1971.3301.463V
ENABLE INPUT (EN)Turn-On Threshold (Rising)VCC = 4.5V to 5.5V, 100mV typ hysteresis0.80.850.9V
LOGIC INPUTS (VID0–VID7)
INTEL (SEL = HIGH OR LOW)Input Low LevelVCC = 4.5V to 5.5V0.4V
Input High LevelVCC = 4.5V to 5.5V0.8V
Input Pulldown Resistance100270kΩ
AMD (SEL = UNCONNECTED)Input Low LevelVCC = 4.5V to 5.5V0.6V
Input High LevelVCC = 4.5V to 5.5V1.4V
Input Pulldown Resistance100270kΩ
LOGIC INPUT (SEL)Internal Bias Resistance50100200kΩ
Internal Bias VoltageVCC = 4.5V to 5.5VVCC / 2V
Input Low LevelVCC = 4.5V to 5.5V0.5V
Input High LevelVCC = 4.5V to 5.5VVCC -
0.5V
VRREADY OUTPUTOutput Low LevelIVRREADY = +4mA0.4V
Output High LeakageVVRREADY = 5.5V1µA
VRREADY Blanking TimeFr om E N r i si ng to V RRE AD Y r isi ng, RS S /OV P = 12kΩ3.05.5ms
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩto GND, RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 118kΩto GND, VCS_+= VCS_-= 1V,
PWM_ = unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITS(VRS+ - VRS-) risingVDAC +
VDAC +
0.200VRREADY Upper Threshold
(Note 1)
(VRS+ - VRS-) fallingVDAC +
VDAC +
(VRS+ - VRS-) fallingVDAC -
VDAC -
0.200VRREADY Lower Threshold
(Note 1)
(VRS+ - VRS-) risingVDAC -
VDAC -
OVERVOLTAGE PROTECTION
Intel (SEL = High or Low)(VRS+ - VRS-) rising (Note 1)VDAC +
VDAC +
VDAC +
0.200V
AMD (SEL = Unconnected)(VRS+ - VRS-) rising1.7501.7751.800V
SS/OVP High LevelISS/OVP = -10mAVCC -
0.450V
OSCILLATOROscillator Frequency Accuracy
(per Phase)Frequency per phase = 300kHz-10+10%
Switching Frequency Range
(per Phase)1501200kHz
CURRENT-SENSE AMPLIFIERSCurrent-Sense Amplifier Gain (GCA)RNTC = 10kΩ, TA = +25°C to +85°C28.830.031.2V/V
CS_+ Input Bias CurrentVCS_+ = VCS_- = 2V0.33.0µA
CS_- Input Bias CurrentVCS_+ = VCS_- = 2V0.65.5µA
CS to PWM_ DelayVCOMP falling20ns
GAIN TEMPERATURE COMPENSATION (NTC)Compensation AccuracyRNTC temperature = 0°C to +125°C
(10k NTC Panasonic ERTJ1VR103)-6+6%
VRHOT TEMPERATURE MONITORINGVRHOT Output Low VoltageIVRHOT = +4mA0.4V
VRHOT Output High Leakage CurrentVVRHOT = 5.5V5µA
VRTSET Temperature Range+60+125°C
VRTSET AccuracyRN TC tem p er atur e = + 60° C to + 125° C , 15° C
hyster esi s ( typ ) ( 10k N TC P anasoni c E RTJ1V R103) -5+5°C
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩto GND, RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 118kΩto GND, VCS_+= VCS_-= 1V,
PWM_ = unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITS
PWM DRIVEROutput Low LevelIPWM_ = +5mA0.10.4V
Output High LevelIPWM_ = -5mA4.54.9V
Source CurrentVPWM_ = VCC - 2V52mA
Sink CurrentVPWM_ = 2V65mA
Rise/Fall Times10ns
PWM Disable Program Threshold4V < VCC < 5.5V3.0VCC -
0.7V
GATE-DRIVER SPECIFICATIONSL_, BS T_ to LX _ Inp ut V ol tag e Rang e4.56.5V
LX Operating Range26V
VL_ UVLO Threshold (VL12,
MAX8809A; VL1, MAX8810A)VVL_ rising, 250mV hysteresis (typ)3.253.553.80V
DH_ = BST_11.6Driver Static Supply Current, IVL_
(per Channel)DH_ = LX_1.11.8mA
Boost Static Supply Current, IBST_
(per Channel)DH_ = BST_0.61mA
Sourcing current, VVL _ = 6.5V1.12.0DH Driver ResistanceSinking current, VVL _ = 6.5V0.81.2Ω
Sourcing current, VVL _ = 6.5V0.851.7DL Driver ResistanceSinking current, VVL _ = 6.5V0.30.6Ω
DH_ Rise Time (trDH)CDH_ = 3000pF14ns
DH_ Fall Time (tfDH)CDH_ = 3000pF9ns
DL_ Rise Time (trDL)CDL_ = 3000pF10ns
DL_ Fall Time (tfDL)CDL_ = 3000pF7ns
DH_ Propagation Delay (tpDHf)CS+ rising to DH falling32ns
Dead Time (tpDLr)LX_ falling to DL_ rising18ns
Dead Time (tDEAD)DL_ falling to DH_ rising35ns
INTERNAL BOOST-DIODE SPECIFICATIONSOn-ResistanceIBST_ = 2mA6Ω
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PARAMETERCONDITIONSMINTYPMAXUNITSVCC Operating Range4.55.5V
Rising4.04.5VCC UVLO Trip LevelFalling3.74.3V
INTERNAL REFERENCE (REF)Output VoltageIREF = -100µA1.992.01V
Output Regulation (Sourcing)VCC = 4.5V at IREF = -500µA to VCC = 5.5V at
IREF = -100µA-0.065+0.065%
Output Regulation (Sinking)VCC = 4.5V at IREF = +100µA to VCC = 5.5V at
IREF = +500µA-0.2+0.2%
BUF REFERENCEBUF Regulation VoltageIBUF = 0A0.991.01V
BUF Output RegulationVCC = 4.5V at IBUF = +100µA to VCC = 5.5V at
IREF = +500µA-0.4+0.4%
SOFT-STARTEN Startup Delay (TD1)From EN rising to VOUT rising1.62.8ms
Soft-Start Period Range (TD2)12kΩ < RSS/OVP < 90.9kΩ0.56.5ms
Soft-Start ToleranceRSS/OVP = 56kΩ2.253.75ms
Intel Boot Level Duration (TD3)SEL = GND or SEL = VCC175350µs
VOLTAGE REGULATIONRS+ Input Bias CurrentVRS+ = 1.0V1µA
RS- Input Bias CurrentVRS- = 0.2V1µA
Output-Voltage Initial AccuracyVDAC_ = 1V (Note 1)-0.35+0.35%
gMV Amplifier Transconductance1.912.06mS
CURRENT LIMITAverage Current-Limit Trip-Level
AccuracyVILIM = 1.5V-11+11%
ILIM Input Bias Current1µA
ILIM Default Program LevelVILIM > VCC - 0.2V1.1971.463V
ENABLE INPUT (EN)Turn-On Threshold (Rising)VCC = 4.5V to 5.5V, 100mV typ hysteresis0.80.9V
LOGIC INPUTS (VID0–VID7)
INTEL (SEL = HIGH OR LOW)Input Low LevelVCC = 4.5V to 5.5V0.4V
Input High LevelVCC = 4.5V to 5.5V0.8V
Input Pulldown Resistance100270kΩ
ELECTRICAL CHARACTERISTICS(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩ= RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 50kΩto GND, VCS_+= VCS_-= 1V, PWM_ =
unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= -40°C to
+85°C.) (Note 2)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PARAMETERCONDITIONSMINTYPMAXUNITS
AMD (SEL = UNCONNECTED)Input Low LevelVCC = 4.5V to 5.5V0.6V
Input High LevelVCC = 4.5V to 5.5V1.4V
Input Pulldown Resistance100270kΩ
LOGIC INPUT (SEL)Internal Bias Resistance50200kΩ
Input Low LevelVCC = 4.5V to 5.5V0.5V
Input High LevelVCC = 4.5V to 5.5VVCC -
0.5V
VRREADY OUTPUTOutput Low LevelIVRREADY = +4mA0.4V
Output High LeakageVVRREADY = 5.5V1µA
VRREADY Blanking TimeFr om E N r i si ng to V RRE AD Y r i si ng , RS S / OV P = 12kΩ3.05.5ms
(VRS+ - VRS-) risingV D AC +
0.150D AC +
0.200VRREADY Upper Threshold
(Note 1)
(VRS+ - VRS-) fallingV D AC +
0.075D AC +
(VRS+ - VRS-) fallingVDAC -
VDAC -
0.200VRREADY Lower Threshold
(Note 1)
(VRS+ - VRS-) risingVDAC -
VDAC -
OVERVOLTAGE PROTECTION
Intel (SEL = High or Low)(VRS+ - VRS-) rising (Note 1)V D AC +
0.150D AC +
0.200V
AMD (SEL = Unconnected)(VRS+ - VRS-) rising1.751.80V
SS/OVP High LevelISS/OVP = 10mAVCC -
0.450V
OSCILLATOROscillator Frequency Accuracy
(per Phase)Frequency per phase = 300kHz-20+20%
Switching Frequency Range
(per Phase)1501200kHz
ELECTRICAL CHARACTERISTICS (continued)(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩ= RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 50kΩto GND, VCS_+= VCS_-= 1V, PWM_ =
unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= -40°C to
+85°C.) (Note 2)
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PARAMETERCONDITIONSMINTYPMAXUNITS
CURRENT-SENSE AMPLIFIERSCurrent-Sense Amplifier Gain (GCA)RNTC = 10kΩ2733V/V
CS_+ Input Bias CurrentVCS_+ = VCS_- = 2V4.5µA
CS_- Input Bias CurrentVCS_+ = VCS_- = 2V7µA
GAIN TEMPERATURE COMPENSATION (NTC)Tem p er atur e C om p ensati on Accur acyRNTC temperature = 0°C to +125°C
(10k NTC Panasonic ERTJ1VR103)-7.5+7.5%
VRHOT TEMPERATURE MONITORINGVRHOT Output Low Voltage4mA sink current0.4V
VRHOT Output High Leakage CurrentVVRHOT = 5.5V5µA
VRTSET Temperature Range+60+125°C
VRTSET AccuracyRNTC temperature = +60°C to +125°C (10k NTC
Panasonic ERTJ1VR103)-5+5°C
PWM DRIVEROutput Low LevelIPWM_ = +5mA0.4V
Output High LevelIPWM_ = -5mA4.5V
PWM Disable Program Threshold4V < VCC < 5.5V3V
GATE-DRIVER SPECIFICATIONSVL_, BST_ to LX_ Input Voltage Range4.56.5V
LX_ Operating Range26V
VL_ UVLO Threshold (MAX8809A,
VL12; MAX8810A, VL1)VVL_ rising, 250mV hysteresis (typ)3.253.80V
DH_ = BST_1.6Driver Static Supply Current,
IVL_ (per Channel)DH_ = LX_1.8mA
Boost Static Supply Current,
IBST_ (per Channel)DH_ = BST_1mA
Sourcing current, VVL _ = 6.5V2.0DH_ Driver ResistanceSinking current, VVL _ = 6.5V1.2Ω
Sourcing current, VVL _ = 6.5V1.7DL_ Driver ResistanceSinking current, VVL _ = 6.5V0.6Ω
ELECTRICAL CHARACTERISTICS (continued)(VVL_= VBST_= 6.5V, VCC= VEN= 5V, VILIM= 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP= VRS+= 1.0V, RVRREADY=
5kΩpullup to 5V, RSS/OVP= 12kΩ= RNTC= 10kΩto GND, fSW= 300kHz, RVRTSET= 50kΩto GND, VCS_+= VCS_-= 1V, PWM_ =
unconnected, RVRHOT= 249Ωpullup to 1.05V, VGND= VPGND_= VLX_ = VRS-= 0V, DL_ = DH_ = unconnected, TA
= -40°C to
+85°C.) (Note 2)
Note 1:VDACrefers to the internal voltage set by the VID code.
Note 2:Specifications to -40°C are guaranteed by design and characterization.
Typical Operating Characteristics(Circuit of Figure 14, VIN= 12V, VOUT= 1.35V, IOUT_MAX= 115A, RO= 1mΩ, fSW= 200kHz, VCC= 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
EFFICIENCY vs. LOAD CURRENT
ROSC = 130kΩLOAD CURRENT (A)
EFFICIENCY (%)
MAX8809A toc01
VIN = 12V
VIN = 20V
VIN = 7V
OUTPUT VOLTAGE vs. LOAD CURRENTLOAD CURRENT (A)
OUTPUT VOLTAGE (V)
MAX8809A toc0220406080100120
OUTPUT VOLTAGE
vs. INDUCTOR TEMPERATURE
MAX8809A toc03
INDUCTOR TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
ILOAD = 50A
ILOAD = 0A
OUTPUT LOAD TRANSIENTMAX8809A toc04
IOUT
VOUT50mV/div
60A/div
20μs/div
ACTIVE CURRENT SHARING
vs. LOAD CURRENTLOAD CURRENT (A)
(mV)
MAX8809A toc0550100
MEASURED ACROSS
C19, C20, C26, C27
AVERAGE DCR IS 0.86mΩ (+25°C)
DYNAMIC VID RESPONSEMAX8809A toc06VRREADY
IOUT
VOUT
VRREADY
500mV/div
60A/div
1V/div
200μs/div
SOFT-START WAVEFORMS (INTEL)MAX8809A toc07EN
VOUT
IIN
VRREADY
500mA/div
1V/div
1V/div
1V/div
1ms/div
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Typical Operating Characteristics (continued)(Circuit of Figure 14, VIN= 12V, VOUT= 1.35V, IOUT_MAX= 115A, RO= 1mΩ, fSW= 200kHz, VCC= 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
SOFT-START WAVEFORMS (AMD)MAX8809A toc08
IIN
VOUT
VEN
VRREADY
500mA/div
1V/div
1V/div
1V/div
1ms/div
SHUTDOWN WAVEFORMS AT NO LOADMAX8809A toc09
VOUT
IIN
VRREADY
500mA/div
1V/div
1V/div
1V/div
400μs/div
SHUTDOWN WAVEFORMS AT FULL LOADMAX8809A toc10
VOUT
IIN
VRREADY
500mV/div
2V/div
1V/div
5A/div
500μs/div
SHORT-CIRCUIT AND
RECOVERY WAVEFORMSMAX8809A toc11
VRREADY
IOUT
IIN
VOUT500mV/div
50A/div
5A/div
2V/div
40μs/div
CURRENT THRESHOLD
vs. INDUCTOR CASE TEMPERATUREINDUCTOR TEMPERATURE (°C)
RMS CURRENT LIMIT (A)
MAX8809A toc1280607010203040500
ILIM = 155A
ILIM = 100A
REFERENCE VOLTAGE
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX8809A toc13
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Typical Operating Characteristics (continued)(Circuit of Figure 14, VIN= 12V, VOUT= 1.35V, IOUT_MAX= 115A, RO= 1mΩ, fSW= 200kHz, VCC= 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
BUF VOLTAGE
vs. AMBIENT TEMPERATUREAMBIENT TEMPERATURE (°C)
BUF VOLTAGE (V)
MAX8809A toc14
PER-PHASE FREQUENCY vs. ROSC
ROSC (kΩ)
PER-PHASE FREQUENCY (kHz)
MAX8809A toc15100200
2/4 PHASE
3 PHASE
CLOCK FREQUENCY
vs. TEMPERATURETEMPERATURE (°C)
FREQUENCY (kHz)
MAX8809A toc16
OUTPUT VOLTAGE OFFSET
vs. ROS
MAX8809A toc17
ROS (kΩ)
OUTPUT VOLTAGE (mV)403060
SOFT-START DURATION
vs. RSS/OVPRSS/OVP (kΩ)
SOFT-START DURATION (ms)
MAX8809A toc1820406080100
VRHOT SETPOINT
vs. RVRTSETRVRTSET (kΩ)
VRHOT SETPOINT (
MAX8809A toc1950100150200250300
OUTPUT OVERVOLTAGE
PROTECTION WAVEFORM
MAX8809A toc20
VOUT
SS/OVP
VRREADY
500mV/div
1V/div
5V/div
2μs/div
VL_ POWER DISSIPATION
vs. PER-PHASE SWITCHING FREQUENCYfS (kHz)
VL_ POWER DISSIPATION (mW)
MAX8809A toc212004006008001000
CDL_ = CDH_ = 3300pF
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
Typical Operating Characteristics (continued)(Circuit of Figure 14, VIN= 12V, VOUT= 1.35V, IOUT_MAX= 115A, RO= 1mΩ, fSW= 200kHz, VCC= 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
VL_ POWER DISSIPATION
vs. LOAD CAPACITANCEDH_/DL_ LOAD CAPACITANCE (pF)
VL_ POWER DISSIPATION (mW)
MAX8809A toc22
DL_ RISE/FALL TIME
vs. LOAD CAPACITANCE
LOAD CAPACITANCE (pF)
RISE/FALL TIME (ns)
MAX8809A toc23
DL_ RISE
DL_ FALL
DH_ RISE/FALL TIME
vs. LOAD CAPACITANCELOAD CAPACITANCE (pF)
RISE/FALL TIME (ns)
MAX8809A toc242000400060008000
DH_ RISE
DH_ FALL
DH_/DL_ RISE/FALL TIME
vs. AMBIENT TEMPERATUREAMBIENT TEMPERATURE (°C)
RISE/FALL TIME (ns)
MAX8809A toc25
DL_ RISEDH_ RISE
DH_ FALLDL_ FALL
CDH_ = CDL_ = 3300pF
VL_ SUPPLY CURRENT
vs. PER-PHASE SWITCHING FREQENCYfS (kHz)
VL_ SUPPLY CURRENT (mA)
MAX8809A toc262004006008001000
CDH_ = CDL_ = 3300pF
SWITCHING WAVEFORMSMAX8809A t0c27DL_
DH_
LX_
10V/div
10V/div
20V/div
200ns/div
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
BST_ AND VL_ WAVEFORMS
VIN = 8VMAX8809A toc28VL_
LX_
BST_
500mV/div
(AC-COUPLED)
200mV/div
(AC-COUPLED)
5V/div
500ns/div
ypical Operating Characteristics (continued)(Circuit of Figure 14, VIN= 12V, VOUT= 1.35V, IOUT_MAX= 115A, RO= 1mΩ, fSW= 200kHz, VCC= 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
DH_ FALLING PROPAGATION DELAY
vs. TEMPERATUREAMBIENT TEMPERATURE (°C)
PROPAGATION DELAY (ns)
MAX8809A toc29
Pin Description
PIN
MAX8809AMAX8810ANAMEFUNCTION
148VRREADYp en- D r ai n, P ow er - O kay Ind i cator . V RRE AD Y i s an op en- d r ai n outp ut that g oes hi g hm p ed ance w hen the outp ut i s i n r eg ul ati on. V RRE AD Y p ul l s l ow w hen the outp ut i s out ofeg ul ati on, the IC i s i n shutd ow n, or V C C i s b el ow the U V LO thr eshol d .1ILIM
Current-Limit Set Input. Connect to the center tap of an external resistor-divider from REF
to GND to set the cycle-by-cycle average current-limit threshold. Connect ILIM to VCC to
select the default current-limit threshold.2REF
Inter nal Refer ence O utp ut. RE F r eg ul ates to 2V . Byp ass RE F to G N D w i th a 0.1µF to 1µF
cer am i c cap aci tor . D o not use a cap aci tor g r eater than 1µF. RE F sour ces up to 500µA for
exter nal l oad s. RE F i s enab l ed w hen V C C i s ab ove U V LO r eg ar d l ess of the state of E N .3COMP
Error-Amplifier Output. Connect COMP to the compensation network to implement either
voltage positioning or integral feedback-control. Connect a resistor from COMP to GND
to set the offset voltage. See the Loop-Compensation Design section for details on
determining the compensation network.5GNDAnalog Ground. Connect GND to the analog ground plane.VCCIC Supply Input. Connect VCC to a 4.5V to 5.5V power supply. Bypass VCC to GND with
a 1µF or larger ceramic capacitor.8RS-
Output-Voltage Remote-Sense Negative Input. Connect RS- to the VSS_SEN remote-
sense point at the load when using the remote sense. Otherwise, connect RS- to GND at
the load.9RS+
Output-Voltage Remote-Sense Positive Input. Connect RS+ to the VCC_SEN remote-
sense point at the load when using remote sense. Otherwise, connect RS+ to the output
at the load.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
MAX8809AMAX8810ANAMEFUNCTION11OSC
Internal Clock Oscillator Frequency Set Input. Connect a resistor from OSC to GND to set
the internal oscillator frequency. See the Setting the Switching Frequency section for
determining the resistor value.12SS/OVPoft- S tar t P r og r am Inp ut and Over vol tag e- P r otecti on Faul t Fl ag . C onnect a r esi stor fr om S /OV P to GN D to set the soft- star t p er i od . S S /O V P p ul l s to V C C d ur i ng an O V P event to
si g nal the faul t cond i ti on. S ee the S oft- S tar t secti on for d eter m i ni ng the r esi stor val ue.13VRTSET
Temperature Comparator Program Input. Connect a resistor from VRTSET to GND to set
the VRHOT temperature threshold. Connect VRTSET to VCC to disable the VRHOT
monitoring feature. See the Temperature Monitoring (VRTSET, VRHOT) section for
resistor selection.14NTC
Temperature-Sensing Input. Connect a 10kΩ NTC thermistor between NTC and GND for
load-line independent temperature compensation. Connect NTC to VCC to disable the
temperature compensation and VRHOT monitoring features. See the Temperature
Monitoring (VRTSET, VRHOT) section for more details on selection of the NTC device.—CS3-Phase 3 Current-Sense Negative Input. Connect to the load side of the output current-
sensing element.17CS3+
Phase 3 Current-Sense Positive Input. Connect CS3+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.18CS2+
Phase 2 Current-Sense Positive Input. Connect CS2+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.19CS12-Phases 1 and 2 Current-Sense Common Negative Input. Connect to the load side of the
output current-sensing elements.20CS1+
Phase 1 Current-Sense Positive Input. Connect CS1+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.21EN
Enable Input. Drive EN high to enable the IC. Drive EN low to place the IC in shutdown
mode. If VCC is greater than the UVLO threshold, EN is internally pulled to VCC with a
100kΩ resistor. If VCC is less than the UVLO threshold, EN is internally pulled to GND
with a 2kΩ resistor.23PWM3PWM Signal Output for phase 3. PWM3 is low during shutdown, UVLO, and OVP faults.
Connect PWM3 to VCC to enable 2-phase operation.24VRHOT
Temperature Fault Flag. VRHOT is an active-high, open-drain output that goes high
impedance when the temperature sensed by the thermistor at NTC exceeds the
temperature threshold programmed at VRTSET.25DH1Phase 1 High-Side MOSFET Gate-Drive Output. Connect to the gate of the high-side
MOSFET for phase 1. DH1 is pulled low during shutdown, UVLO, and OVP faults.26LX1Phase 1 Inductor Sense Point. Connect LX1 to the switched side of the inductor for
phase 1.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
MAX8809AMAX8810ANAMEFUNCTION27BST1hase 1 H i g h- S i d e M O S FE T Gate- D r i ve S up p l y. C onnect a 0.22µF or l ar g er cer am i c
cap aci tor fr om BS T1 to LX 1 to sup p l y g ate d r i ve for the hi g h- si d e M O S FE T. S ee the Boostap aci tor S el ecti on secti on for d etai l s on cal cul ati ng the BS T1 cap aci tor val ue.28DL1hase 1 Low - S i d e M OS FE T Gate- D r i ve Outp ut. C onnect to the g ate of the l ow - si d e M O S FE T
for p hase 1. D L1 i s p ul l ed l ow d ur i ng und er vol tag e l ockout and p ul l ed hi g h d ur i ng an OV P
faul t. D L1 i s hi g h i n shutd ow n i f V C C i s g r eater than the U V LO thr eshol d .29PGND1
Power Ground for the Phase 1 Driver. Connect PGND1 to the source of the phase 1
low-side MOSFET. PGND1 must be connected to PGND2 and GND externally. See the
PC Board Layout Guidelines section for more details.—VL12
Phase 1 and 2 Low-Side MOSFET Gate-Drive Supply. Connect VL12 to a 4.5V to 6.5V
supply. Bypass VL12 with a 2.2µF or larger ceramic capacitor to the power ground
plane.32PGND2
Power Ground for the Phase 2 Driver. Connect PGND2 to the source of the phase 2
low-side MOSFET. PGND2 must be connected to PGND1 and GND externally. See the
PC Board Layout Guidelines section for more details.33DL2hase 2 Low - S i d e M OS FE T Gate- D r i ve Outp ut. C onnect to the g ate of the l ow - si d e M OS FE T
for p hase 2. D L2 i s p ul l ed l ow d ur i ng und er vol tag e l ockout and p ul l ed hi g h d ur i ng an OV P
faul t. D L2 i s hi g h i n shutd ow n i f V C C i s g r eater than the U V LO thr eshol d .34BST2hase 2 H i g h- S i d e M O S FE T Gate- D r i ve S up p l y. C onnect a 0.22µF or l ar g er cer am i c
cap aci tor fr om BS T2 to LX 2 to sup p l y g ate d r i ve for the hi g h- si d e M O S FE T. S ee the Boostap aci tor S el ecti on secti on for d etai l s on cal cul ati ng the BS T2 cap aci tor val ue.35LX2Phase 2 Inductor Sense Point. Connect LX2 to the switched side of the inductor for
phase 2.36DH2Phase 2 High-Side MOSFET Gate-Drive Output. Connect to the gate of the high-side
MOSFET for Phase 2. DH2 is pulled low during shutdown, UVLO, and OVP faults.38SEL
VID Table Selection Input. Connect SEL to GND to select the VRD10 VID code
(Table 5). Connect SEL to VCC to select the VRD11 8-bit VID code (Table 6). Leave SEL
unconnected to select the K8 Rev F VID code (Table 4).
33–4039–46VID7–VID0
Voltage Identification Code Inputs. Use VID_ to set the output voltage. SEL selects the
VRD10, VRD11, or K8 Rev F VID logic codes. Connect VID_ to the system VTT with a
680Ω resistor for logic-high for Intel VR solutions. Connect VID_ to the system VDDQ
with a 1kΩ resistor for logic-high for AMD VR solutions.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
MAX8809AMAX8810ANAMEFUNCTION4BUF
1V Reference Output. Bypass BUF to GND with a 1µF or larger ceramic capacitor.
Connect a resistor from COMP to BUF to set the load-line. See the Loop-Compensation
Design section for more details.7, 10, 37, 47N.C.No Internal Connection15CS4+
Phase 4 Current-Sense Positive Input. Connect CS4+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.16CS34-Phases 3 and 4 Current-Sense Common Negative Input. Connect to the load side of
the output current-sensing elements.22PWM4
PWM Signal Output for Phase 4. PWM4 is low during shutdown, UVLO, and OVP faults.
Connect PWM4 to VCC to enable 3-phase operation. Connect PWM3 and PWM4 to VCC
to enable 2-phase operation.30VL1
Phase 1 Low-Side MOSFET Gate-Drive Supply. Connect VL1 to a 4.5V to 6.5V supply.
VL1 must be connected to VL2 externally. Bypass the VL1/VL2 connection with a 2.2µF
or larger ceramic capacitor to the power ground plane.31VL2
Phase 2 Low-Side MOSFET Gate-Drive Supply. Connect VL2 to a 4.5V to 6.5V supply.
VL2 must be connected to VL1 externally. Bypass the VL1/VL2 connection with a 2.2µF
or larger ceramic capacitor to the power ground plane.EPExposed Paddle. Connect to the analog GND plane for enhanced thermal power
dissipation.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET DriversVL1
VCC
MAX8809A
MAX8810A
REF
gMB
TEMPERATURE
COMPENSATION
TEMPERATURE
COMPENSATION
NTC
THERMISTOR
LINEARIZATION
CIRCUIT
MAX8810A ONLY
OVP
COMPARATOR
S/R
S/R
S/RPWM3
BST1
DH1
LX1
DL1
PGND1
VL1
(MAX8810A)
VL12
(MAX8809A)
(MAX8809A)
BST2
DH2
LX2
DL2
PGND2
VL2
(MAX8810A)
PWM1
PWM2
VDAC
DHOUT
SENSE
DLOUT
SENSE
DHOUT
SENSE
DLOUT
SENSE
PWM4
(MAX8810A)S/R
2-/3-/4-
PHASE
CONTROL
OSC
POWER-GOOD
CIRCUITRY
SOFT-START
SOFT-STOP
VID
DECODE
LOGIC
DRIVER
CONTROL
LOGIC
REFERENCE
OVP
THRESHOLD
UVLO
BIAS
CLAMP
VRHOTNTCVRTSET
REF / 2
RSDA
CURRENT
FOLDBACK
CS1+
CS2+
CS3-
(MAX8809A)
CS3+
CS34-
(MAX8810A)
CS4+
(MAX8810A)
BUF
(MAX8810A)
COMP
SS/OVP
REF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
SEL
RS+
RS-
ILIM
VRREADY
CS12-
OSCILLATOROPERATION
MODE DETECT
gMV
Figure 1. Block Diagram
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET DriverstrDL
tpDLrtfDL
tDEAD
trDHtfDH
Figure 2. Driver Timing Diagram
Detailed DescriptionThe MAX8809A/MAX8810A synchronous, 2-/3-/4-
phase, step-down, current-mode controllers with inte-
grated dual-phase MOSFET drivers provide flexible
solutions that fully comply with Intel VRD11/VRD10 and
AMD K8 Rev F CPU core supplies. The flexible design
supplies load currents of up to 150A for low-voltage
CPU core power supplies.
The MAX8809A is suitable for 2- or 3-phase core sup-
ply applications. With an integrated dual-MOSFET dri-
ver, the MAX8809A offers a single-chip IC solution for
dual-phase core supplies. Together with the MAX8552,
a high-performance single-phase MOSFET driver, the
MAX8809A also supports 3-phase core supplies.
Similarly, the MAX8810A features a single IC solution
for dual-phase core supplies. It also features two-IC
solutions for 3- or 4-phase core supplies by adding a
single MOSFET driver (MAX8552) or a dual-MOSFET
driver (MAX8523).
Both the MAX8809A and MAX8810A fully comply with
Intel VRD11, Extended VRD10, and the AMD K8 Rev F
VID codes. The SEL input allows the user to select the
architecture specifications.
Clock Frequency (OSC)An external resistor, ROSC, from OSC to GND sets the
internal clock frequency of the MAX8809A/MAX8810A.
A 1% resistor is recommended to maintain good fre-
quency accuracy. The internal clock frequency sets the
per-phase switching frequency. The selection of switch-
ing frequency per phase is influenced by factors such
as the switching speed of the MOSFETs, the inductor’s
core material, different types of input and output capac-
itors, and the available board space. Once the per-
phase switching frequency is selected, the internal
clock frequency is determined using the procedure in
the Setting the Switching Frequencysection.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Voltage Reference (REF)A precision 2V reference is provided by the MAX8809A/
MAX8810A at the REF output. REF is capable of sinking
and sourcing up to 500µA for external loads. Connect a
0.1µF to 1µF ceramic capacitor from REF to GND.
Internal REFOK circuitry monitors the reference voltage.
The reference voltage must be above the REFOK thresh-
old of 1.84V to activate the controller. The controller is
disabled if the reference voltage falls below 1.74V.
Output Current Sensing (CS_+, CS_-)The output current of each phase is sensed differentially.
A low-offset-voltage, differential-current amplifier
(30V/V) at each phase allows low-resistance current-
sense resistors to be used to minimize power dissipa-
tion. Sensing the current at the output of each phase
offers advantages including less noise sensitivity, more
accurate current sharing between phases, and the flex-
ibility of using either a current-sense resistor or the DC
resistance of the output inductor.
Using the DC resistance, RDC, of the output inductor
(Figure 3) allows higher efficiency. In this configuration,
the initial tolerance and temperature coefficient of RDC
must be accounted for in the output-voltage droop-error
budget. The temperature coefficient can be compensat-
ed; see the Load-Line Independent Inductor DC
Resistance Temperature Compensation section for more
details. An RC-filtering network is needed to extract the
current information from the output inductor. The time
constant of the RC network is calculated as follows:
where L is the inductance of the output inductor. For
20A or higher current-per-phase applications, the DC
resistance of commercially available inductors is
approximately 1mΩ. To minimize current-sense error
due to the bias current at the current-sense inputs,
choose R1 less than 2kΩ. Determine the value for C1 as:
Select a 1% resistor for R1. For mainstream PCs 20%
tolerance is recommended for C1, and for performance
PCs 10% tolerance should be considered. If using an
inductor with RDCgreater than 1mΩ, a resistor (R2)
may be necessary to divide down the voltage across
CS_+ and CS_-. The maximum average signal present
at the input of the current-sense amplifier should not
exceed 85mV.
When a current-sense resistor is used for more accu-
rate current sharing and load-line, a similar RC-filtering
circuit is recommended to cancel the equivalent series
inductance of the current-sense resistor, as shown in
Figure 4. Again, select R2 less than 2kΩ, and C2 is
determined by the following equation:
where ESL is the equivalent series inductance of the
current-sense resistor and RSis the value of the cur-
rent-sense resistor. For example, a 1mΩ, 2025 pack-
age sense resistor has an ESL of 1.6nH. If using an RS
greater than 1mΩ, a resistor (R2) may be necessary to
divide down the voltage across CS_+ and CS_-. The
maximum average signal present at the input of the
current-sense amplifier should not exceed 85mV.
Output Current Limit and Short-Circuit
Protection (ILIM)The MAX8809A/MAX8810A feature a precise average
output current limit on a cycle-by-cycle basis using
Maxim’s proprietary RA2technology. The current-limit
scheme is insensitive to input-voltage variation, the
inductor tolerance, and the tolerance of the current-
sense capacitor, permitting the use of low-cost compo-
nents to reduce total BOM cost. Furthermore, the
current limit is fully temperature compensated resultingESLS2 =×()LDC1 =×()L
RDC11 ×=
RDCIOUT
OPTIONAL
VRDC = RDC x IOUT
RDC IS THE INDUCTOR DC RESISTANCE
CS_+CS_-
Figure 3.Inductor RDCCurrent SenseIOUTVS = RS x IOUT
ESL IS THE PARASITIC INDUCTANCE OF THE CURRENT-SENSE RESISTOR
ESLL
CS_+CS_-
OPTIONAL
Figure 4.Resistor Current Sense
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Driversin a constant output current limit over the entire opera-
tional temperature range. This eliminates the need to
oversize MOSFETs and inductors to compensate for
thermal effects. Connecting ILIM to VCCprograms the
default current-limit threshold. To select a different cur-
rent-limit threshold, connect a resistor-divider from REF
to GND with ILIM connected to the center tap. The volt-
age at ILIM is proportional to the current-limit threshold.
See the Setting the Current-Limitsection for more details.
The current-limit circuitry terminates the DH_ on-time
immediately when the current-sense voltage (VCS_+-
VCS_-) exceeds the current-limit threshold, allowing the
output inductor current to ramp down. At the next
switching cycle, the PWM pulse is skipped if the output
inductor current is still above the current-limit threshold.
Otherwise, the new cycle initiates as normal.
The MAX8809A/MAX8810A offer foldback-current pro-
tection under soft-start and overload conditions. This
feature allows the VRM to safely operate under short-
circuit conditions and to automatically recover once the
short-circuit condition is removed. If the output voltage
falls below the VRREADY threshold during an overcur-
rent event, the foldback current-limit circuitry sets the
current-limit threshold to half the user-selected value.
Output Differential Sensing (RS+, RS-)The MAX8809A/MAX8810A feature differential output-
voltage sensing to achieve the highest possible output
accuracy. This allows the controllers to sense the actu-
al voltage at the load, so the controller can compensate
for losses in the power output and ground lines. Traces
from the load point back to RS+ and RS- should be
routed close to each other and as far away as possible
from noise sources (such as inductors and high di/dt
traces). Use a ground plane to shield the remote-sense
traces from noise sources. To filter out common-mode
noise, RC filtering is recommended for these inputs as
shown in Figure 5. For VRD applications, a 100Ωresis-
tor with a 1nF capacitor should be used. For VRM
applications, additional 50Ωresistors should be con-
nected from these inputs to the local outputs of the
converter before the VRM connector. This avoids
excessive voltage at the CPU in case the remote-sense
connections get disconnected.
Programming the Output-Voltage DroopBoth the MAX8809A and MAX8810A employ peak-cur-
rent-mode control with finite gain to actively set the out-
put-voltage droop. Figure 6 shows the simplified control
block diagram. The relationship between the output
inductor current in an N-phase DC-DC converter and
the output voltage of the voltage-error amplifier is:
where GCA (30V/V typ) is the gain of the differential cur-
rent amplifier and N is the number of phases. IOUT is the
total output current. Therefore, when the output current
increases, VCincreases. On the other hand, VCis relat-
ed to the output voltage of the converter by the following
equation:
where gMVis the transconductance of the voltage-error
amplifier (2mS typ) and VDACis the VID-generated voltage.VgRVVCMVCOMPDACOUT =××−()IRGCOUTSENSECA =××
MAX8809A/
MAX8810A
RS+
50Ω
50Ω
100Ω
100Ω
1nF
1nF
RS-
TO REMOTE SENSE
LOCATION
TO POSITIVE OUTPUT
OF VRM
TO POWER GROUND
OF VRM
Figure 5. Recommended Filtering for Output-Voltage Remote
Sensing
PWM
COMPARATOR
VOLTAGE-
ERROR AMPLIFIERRCOMPgMVVi
VDAC
VOUT
IL_PEAK
GCA
RSENSE
Figure 6. Simplified Peak Current-Mode Control IC with Active
Output-Voltage Positioning
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET DriversThe DC gain of the voltage-error amplifier is equal to
gMVx RCOMP. From the previous equations it is clear
that the output-voltage droop can be accurately pro-
grammed if the DC gain of the voltage-error amplifier is
set to be a finite value. As the output current increases,increases and, consequently, VOUTdecreases.
Define the output-droop resistance, RDROOP, as:
then RDROOP can be expressed as:
Since GCAand gMVare constants, RDROOPis solely
determined by RCOMPwhen RSENSEand N are chosen.
Peak current-mode control with finite gain is the sim-
plest way to achieve the output-voltage droop without
introducing a separate current loop, which is the case
for voltage-mode control. Therefore, the response time
of the output-voltage droop is the same as the voltage-
feedback loop, resulting in fast output-voltage-droop
transient response and less output capacitance than
solutions using voltage-mode control.
Other features offered by peak-current-mode control
are excellent line regulation and inherent current shar-
ing between phases. Standard peak-current-mode con-
trol does have one disadvantage in that current
matching between phases is impacted by the inductor
mismatch (tolerance) between phases. Because only
the current peak is controlled, any mismatch in the
inductor value between two phases creates an inductor
ripple current mismatch, which, in turn, creates a DC
current mismatch between those two phases.
Tolerance mismatch between the current-sense capac-
itors used in DCR current sensing creates the exact
same DC current mismatch as an inductor mismatch.
Maxim’s proprietary RA2technology addresses this
issue by averaging out the inductor ripple current indi-
vidually at each phase, as shown in Figure 7. The rapid
active average circuitry learns the peak-to-peak ripple
current of each phase in 5 to 10 switching cycles and
then biases the peak current signal down by half of the
peak-to-peak ripple current, consequently eliminating
the impact of both output inductance and DCR current-
sense capacitance variations. Since the rapid active
average circuitry is not part of the current-loop path, it
does not slow down the transient response.
Programming the Output Offset VoltageAccording to the Intel VRD specifications, the output
voltage at no load cannot exceed the voltage specified
by the VID code, including the initial set tolerance, rip-
ple voltage, and other errors. Therefore, the actual out-
put voltage should be biased lower to compensate for
these errors. For the MAX8809A, the output-voltage off-
set is created through a resistor-divider that is connect-
ed between REF and GND, with the center tap
connected to COMP as shown in Figure 8. This resistor-
divider also sets the output load-line. The MAX8810A
contains a BUF output that makes the output-voltage
offset setting independent of the output load-line. To
program the output-voltage offset, connect a resistor
between COMP and GND. A resistor between BUF and
COMP sets the output load-line. See the Loop
Compensation Design section for details on setting the
output-voltage offset.RGRDROOPSENSECACOMP =×VVDROOPDACOUT
OUT =−()
1/S
PWM
COMPARATOR
VOLTAGE-
ERROR AMPLIFIERRCOMP
VDAC
VOUT
gMA
GCA
RSENSE x (IOUT / N)RSENSE x (IOUT / N)
RA2 ALGORITHMgMB
gMV
Figure 7. Implementation of the Rapid Active Averaging (RA2)
Algorithm
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Load-Line Independent Inductor DC
Resistance Temperature Compensation Changes in inductor resistance due to temperature
cause a change in the output-droop characteristic. This
is compensated by changing the gain of the current-
sense amplifier as a function of temperature. In doing
so, the voltage at COMP is independent of temperature,
resulting in a temperature-independent load-line setting.
Additionally, the output short-circuit protection is also
temperature independent because current limit is imple-
mented by clamping the voltage at COMP. This technol-
ogy uses an NTC thermistor solely for temperature
compensation, freeing it from being one of the compo-
nents that determines the output load-line. Therefore,
only one NTC thermistor is needed to enable any output
load-line. The same NTC thermistor is used for tempera-
ture sense for the VRHOT output. The MAX8809A/
MAX8810A temperature-compensation scheme is opti-
mized for use with a Panasonic ERTJ1VR103 10kΩNTC
thermistor. Other thermistors may be used. Contact your
local Maxim representative for more details.
Loop CompensationDuring a load transient, the output voltage instantly
changes due to the ESR of the output capacitors by an
amount equal to their ESR times the change in load cur-
rent (ΔVOUT= RESRx ΔILOAD). The output voltage then
deviates further based on the speed at which the loop
compensates for the load transient. The voltage-posi-
tioning method allows better utilization of the output reg-
ulation window, resulting in less required output
capacitors. The RA2architecture adjusts the output cur-
rent based on the instantaneous output voltage, result-
ing in fast voltage positioning. The voltage-error
amplifier consists of a high-bandwidth, high-accuracy
transconductance amplifier (gMVin Figure 7). The nega-
tive input of the transconductance amplifier is connected
to the output of the remote-voltage differential amplifier,
and the positive input is connected to the output of an
internal DAC controlled by the VID inputs. The DC gain
of the transconductance amplifier is set to a finite value
to achieve fast output-voltage positioning by connecting
an RC circuit (RCOMPand CCOMP) from COMP to GND.
See the Loop-Compensation Design section for details
on selecting the required components.
VR Ready Output (VRREADY)VRREADY is an open-drain output that turns high
impedance when the output voltage reaches regula-
tion. VRREADY goes low if VOUTis less than (VDAC-
225mV) or greater than (VDAC + 175mV), signaling an
out-of-regulation fault. VRREADY is held low in shut-
down, if VCCis less than the UVLO threshold, or during
soft-start. For logic-level output voltages, connect an
external pullup resistor between VRREADY and the
logic power supply. A 100kΩresistor works well in most
applications.
Dynamic VID ChangeThe MAX8809A/MAX8810A provide the ability for the
CPU to dynamically change the VID inputs while the
controller is operating (on-the-fly or OTF). The output
voltage changes in 6.25mV steps (Intel) or
12.5mV/25mV steps (AMD) when a VID change is
detected.
The controller provides a 400ns logic-skew window to
prevent false code changes. The controller accepts
both step-by-step changes of VID inputs or all-at-once
VID input changes. For all-at-once VID input changes,
the output-voltage slew rate is the same, 1 LSB per
step and 2µs duration. VRREADY is blanked during
dynamic VID changes.
Multiphase Operation SelectionThe MAX8809A operates in either a 2- or 3-phase config-
uration. Connect PWM3 to VCCfor 2-phase operation.
The MAX8810A operates in 2-, 3- or 4-phase configura-
tion. Connect PWM4 to VCCfor 3-phase operation.
Connect PWM4 and PWM3 to VCCfor 2-phase operation.
All active PWM outputs are held low during shutdown.
UVLO and Output EnableWhen the IC supply voltage (VCC) is less than the
UVLO threshold (4.25V typ), all active PWM outputs are
internally pulled low and most internal circuitry is shut
down to reduce the quiescent current. When EN is
released and VCC> UVLO, the internal 100kΩresistor
pulls EN to VCCand soft-start is initiated (after a typical
2.2ms delay).
ROS
RLL
REF
COMP
ROS
RLL
BUF
COMP
MAX8810AMAX8809A
Figure 8. Programming the Output Offset Voltage
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET DriversWhen the driver supply voltage (VVL_) is less than its
UVLO threshold (3.55V typ), DH_ and DL_ are held low.
If VVL_ is above the UVLO threshold and while EN is low,
DL_is driven high and DH_ is held low. This prevents
the output of the converter from rising before a valid EN
high signal is present.
Soft-StartThe MAX8809A/MAX8810A soft-start with 6.25mV
steps, regardless of processor architecture. Connect a
resistor between SS/OVP and GND to program the soft-
start time. When the device is enabled, SS/OVP is dri-
ven to 2V and the current drawn by the set resistor is
measured. This current sets the internal delay time
between the DAC voltage steps. Select a resistor
between 12kΩand 90.9kΩfor a corresponding soft-
start time of 500µs to 6.5ms. For Intel designs, the
resistor value is calculated as:
where tSSis the desired soft-start time (in ms) to the
1.1V VBOOTlevel. Figure 9 shows the Intel startup
sequence, and Table 1 shows the values of the time
delays.
For AMD applications, the controllers soft-start up to the
voltage set by the VID inputs. The soft-start time is set
by the following equation:
where VDACis the output voltage set by the VID inputs.
Figure 10 shows the AMD startup sequence, and Table 2
shows the values of the time delays.
Soft-StopWhen EN goes low, the output of the converter ramps
down to 0V in 6.25mV DAC steps in the time set by the
SS/OVP input. Once the output reaches 0V, DL is held
high and DH is held low to maintain the 0V output. ThistVSSOVPss
DAC/() . .Ω=−×001830532RktOVPss/() .Ω=−001830532
VID
INPUT
READ
(SS TIME)
NO. OF STEPS x 2μs
TD5
TD4TD3TD2
TD1
SOFT-START RATE
SET BY RSS/OVPSOFT-STOP
RATE SET BY RSS/OVP
VBOOT
6.25mV/STEP6.25mV/STEPOUT
VRREADY
VID CODE
CHANGE
STEP TO
VID CODE
6.25mV/2μs
NORMAL
OPERATION
6.25mV/2μs
Figure 9. Intel VRD11/VRD10 Startup Sequence
Table 1. Intel Startup Sequence
Specifications
PARAMETERMINMAXTD11ms5ms
TD250µs5ms
TD350µs3ms
TD4—2.5ms
TD550µs3ms
approach prevents large negative voltages on the out-
put during shutdown and therefore eliminates the need
for a Schottky clamp diode on the output.
Output Overvoltage Protection (OVP)When the output voltage exceeds the regulation voltage
by 200mV (Intel) or exceeds 1.8V (AMD), all active PWM
outputs are pulled low and the controller is latched off.
SS/OVP is internally pulled to VCCto signal an overvolt-
age fault. All DH_ outputs are held low and all DL_ out-
puts are held high to discharge the output. The latch
condition can only be cleared by cycling the input volt-
age (VCC).
Integrated Dual-MOSFET DriverThe MAX8809A/MAX8810A contain a dual-phase gate
driver capable of driving 3000pF capacitive loads with
only 32ns propagation delay and 11ns typical rise and fall
times, allowing operation up to 1.2MHz per phase.
Adaptive dead time controls low-side MOSFET turn-on
and high-side MOSFET turn-on. This maximizes converter
efficiency, while allowing operation with a variety of
MOSFETs. A UVLO circuit ensures proper power-on
sequencing.
Adaptive Shoot-Through ProtectionAdaptive shoot-through protection is incorporated for
the switching transition after the high-side MOSFET is
turned off and before the low-side MOSFET is turned
on. The low-side driver is turned on only when the LX_
voltage falls below 2.5V typical. In addition, a fixed
35ns delay time between the low-side MOSFET turn-off
and high-side MOSFET turn-on adds further protection
from “shoot-through.” The 35ns time begins after DL_
has fallen through 1.5V typical.
MOSFET Driver UVLOWhen VVL12(MAX8809A) or VVL1(MAX8810A) is below
the UVLO threshold (3.55 typ), DH_ and DL_ are held
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET DriversSS TIME
TD2TD3TD12msTD41.1ms
SOFT-START RATE
SET BY RSS/OVPABOVE 0.775V
25mV/4μs
SOFT-STOP
RATE SET BY RSS/OVP
VID CODE
LEVEL
6.25mV/STEP
6.25mV/STEP
BELOW 0.775V
12.5mV/2μs
OUT
VRREADY
VID INPUT
CHANGE
Figure 10. K8 Rev F Startup Sequencing and Timing
Table 2. AMD Startup Sequence
Specifications
PARAMETERM IN IM U M T IM Eµ s ) A XIM U M T IM Em s ) TD11—
TD2*5006.5
TD3—20
TD4—500
*User programmable.
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Driverslow. Once VVL_is above the UVLO threshold and EN is
low, DL_ is kept high and DH_ is kept low. This pre-
vents the output from rising before a valid EN signal
is given.
Boost Circuit for High-Side MOSFET DriverThe gate-drive voltage for the high-side MOSFET dri-
vers is generated by a flying-capacitor boost circuit.
The capacitor between BST_ and LX_ is charged from
the VL_ supply through an internal switch while the low-
side MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage on the capacitor is
stacked above LX_ to provide the necessary turn-on
voltage for the high-side MOSFET(s). No external boost
diode is needed. See the Boost Capacitor Selection
section for details on selecting the correct capacitor.
Thermal ProtectionThe MAX8809A/MAX8810A feature a thermal-fault-pro-
tection circuit. When the junction temperature rises
above +160°C typical, an internal thermal sensor acti-
vates the shutdown circuit to hold all MOSFET drivers
and active PWM outputs low to disable switching. The
thermal sensor reactivates the controller after the junc-
tion temperature cools by 25°C typical.
Temperature Monitoring (VRTSET, VRHOT)The MAX8809A/MAX8810A contain temperature-moni-
toring circuitry that allows the user to program a tem-
perature trip point between +60°C and +125°C, and
monitor an active-high, open-drain VRHOT output.
Connect a resistor from VRTSET to GND to set the tem-
perature-monitoring threshold. The resistor is calculat-
ed as follows:
where KTis a temperature scale factor specifically for
the Panasonic ERTJ1VR103 NTC thermistor. Table 3
provides values of KTand the closest standard 1%
RVRTSETvalues needed to program the VRHOT thresh-
old over a +60°C to +125°C range. RVRTSETmust be
greater than 20kΩ. Contact your local Maxim represen-
tative for information on using other thermistors.
Architecture Selection and Timing
AMD K8 Rev FThe AMD K8 Rev F processor uses a 6-bit VID code
that specifies a 0.375V to 1.55V output voltage range
(see Table 4). Leave SEL unconnected to select the
AMD K8 Rev F architecture. The startup sequencing
and timing specifications are shown in Figure 10. Note
that the VID input defines the AMD processor boot
level, and there is no internal default. The boot level is
not latched; therefore, if the codes change during soft-
start, the boot level also changes.
Extended Intel VRD10The Intel VRD10 processor uses a 7-bit VID code that
specifies a 0.83125V to 1.6V output voltage range (see
Table 5). Connect SEL to GND to select the VRD10
architecture. The startup sequencing and timing speci-
fications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
Intel VRD11The Intel VRD11 processor uses an 8-bit VID code that
specifies a 0.3125V to 1.6V output voltage range (see
Table 6). Connect SEL to VCCto select the VRD11
architecture. The startup sequencing and timing speci-
fications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.KinkVRTSETT. =800Ω
Table 3. Temperature Scale Factor
TEMPERATURE (°C)KTRVRTSET (kΩ)+604.497294
+655.453243
+706.580200
+757.903169
+809.447140
+8511.244118
+9013.325100
+9515.72584.5
+10018.48471.5
+10521.64361.9
+11025.24752.3
+11529.34545.3
+12033.98839.2
+12539.23134
