MAX8794ETB+-MAX8794ETB+T Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX8794ETB+-MAX8794ETB+T
Low-Voltage DDR Linear Regulator
General Description
The MAX8794 DDR linear regulator sources and sinks up
to 3A peak (typ) using internal n-channel MOSFETs. This
linear regulator delivers an accurate 0.5V to 1.5V output
from a low-voltage power input (VIN= 1.1V to 3.6V). The
MAX8794 uses a separate 3.3V bias supply to power the
control circuitry and drive the internal n-channel MOSFETs.
The MAX8794 provides current and thermal limits to pre-
vent damage to the linear regulator. Additionally, the
MAX8794 generates a power-good (PGOOD) signal to
indicate that the output is in regulation. During startup,
PGOOD remains low until the output is in regulation for 2ms
(typ). The internal soft-start limits the input surge current.
The MAX8794powers the active-DDR termination bus
that requires a tracking input reference. The MAX8794
can also be used in low-power chipsets and graphics
processor cores that require dynamically adjustable
output voltages. The MAX8794is available in a 10-pin,
3mm x 3mm, TDFN package.
Applications
Notebook/Desktop Computers
DDR Memory Termination
Active Termination Buses
Graphics Processor Core Supplies
Chipset/RAM Supplies as Low as 0.5V
FeaturesInternal Power MOSFETs with Current Limit (3A typ)Fast Load-Transient ResponseExternal Reference Input with Reference
Output Buffer1.1V to 3.6V Power Input±15mV (max) Load-Regulation ErrorThermal-Fault ProtectionShutdown InputPower-Good Window Comparator with 2ms (typ)
DelaySmall, Low-Profile, 10-Pin, 3mm x 3mm TDFN
PackageCeramic or Polymer Output Capacitors
MAX8794
Low-Voltage DDR Linear Regulator
Ordering Information
OUTIN
OUTS
AGND
PGND
VOUT = VTT
VIN
(1.1V TO 3.6V)
VBIAS
(2.7V TO 3.6V)
VDDQ
(2.5V OR 1.8V)VREFOUT = VTTR
REFOUT
MAX8794
VCC
PGOOD
SHDN
REFIN
Typical Operating Circuit
19-0584; Rev 2; 3/10
PARTTEMP RANGEPIN-
PACKAGE
TOP
MARK
MAX8794ETB+-40°C to +85°C10 TDFN-EP*
(3mm x 3mm)ASW
MAX8794ETB/V+-40°C to +85°C10 TDFN-EP*
(3mm x 3mm)ASW
SHDN
OUTSPGOOD
OUT
PGNDAGND
REFIN
VCC
TDFN
3mm x 3mm
TOP VIEWEP*
*EXPOSED PAD.+
REFOUT
MAX8794
Pin Configuration
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
MAX8794
Low-Voltage DDR Linear Regulator
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN= 1.8V, VCC= 3.3V, VREFIN= VOUTS= 1.25V, SHDN= VCC, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to PGND............................................................-0.3V to +4.3V
OUT to PGND..............................................-0.3V to (VIN+ 0.3V)
OUTS to AGND............................................-0.3V to (VIN+ 0.3V)
VCCto AGND.........................................................-0.3V to +4.3V
REFIN, REFOUT, SHDN, PGOOD to AGND...-0.3V to (VCC+ 0.3V)
PGND to AGND.....................................................-0.3V to +0.3V
REFOUT Short Circuit to AGND.................................Continuous
OUT Continuous RMS Current
100s................................................................................±1.6A
1s....................................................................................±2.5A
Continuous Power Dissipation (TA= +70°C)
10-Pin 3mm x 3mm TDFN
(derated 24.4mW/°C above +70°C)...........................1951mW
Operating Temperature Range
MAX8794ETB...................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VINPower input1.13.6Input Voltage RangeVCCBias supply2.73.6V
Quiescent Supply Current (VCC)ICCLoad = 0, VREFIN > 0.45V0.71.3mA
SHDN = AGND, VREFIN > 0.45V350600Shutdown Supply Current (VCC)ICC(SHDN)SHDN = AGND, REFIN = AGND50100µA
Quiescent Supply Current (VIN)IINLoad = 00.410mA
Shutdown Supply Current (VIN)IIN(SHDN)SHDN = AGND0.110µA
TA = +25°C-40+4Feedback-Voltage ErrorVOUTSREFIN to OUTS,
IOUT = ±200mATA = -40°C to +85°C-6+6mV
Load-Regulation Error-1A ≤ IOUT ≤ +1A-15+15mV
Line-Regulation Error1.4V ≤ VIN ≤ 3.3V, IOUT = ±100mA1mV
OUTS Input Bias CurrentIOUTS-1+1µA
OUTPUT
Output Adjust Range0.51.5V
High-side MOSFET (source) (IOUT = 0.1A)0.100.169OUT On-ResistanceLow-side MOSFET (sink) (IOUT = -0.1A)0.100.20Ω
Output Current Slew RateCOUT = 100µF, IOUT = 0.1A to 2A3A/µs
OUT Power-Supply Rejection
RatioPSRR10Hz < f < 10kHz, IOUT = 200mA,
COUT = 100µF80dB
OUT to OUTS ResistanceROUTS12kΩ
Discharge MOSFET On-
ResistanceRDISCHARGESHDN = AGND8Ω
MAX8794
Low-Voltage DDR Linear Regulator
Note 1:Limits are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed through cor-
relation using statistical-quality-control (SQC) methods.
ELECTRICAL CHARACTERISTICS (continued)
(VIN= 1.8V, VCC= 3.3V, VREFIN= VOUTS= 1.25V, SHDN= VCC, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
REFERENCE
REFIN Voltage RangeVREFIN0.51.5V
REFIN Input Bias CurrentIREFIN-1+1µA
REFIN Undervoltage-Lockout
VoltageRising edge, hysteresis = 75mV0.350.45V
REFOUT VoltageVREFOUTVCC = 3.3V, IREFOUT = 0VREFIN
- 0.01VREFINVREFIN
+ 0.01V
REFOUT Load RegulationΔVREFOUTIREFOUT = ±5mA-20+20mV
FAULT DETECTION
Thermal-Shutdown ThresholdTSHDNRising edge, hysteresis = 15°C+165°C
VCC Undervoltage-Lockout
ThresholdVUVLORising edge, hysteresis = 100mV2.452.552.65V
IN Undervoltage-Lockout
ThresholdRising edge, hysteresis = 55mV0.91.1V
Current-Limit ThresholdILIMIT1.834.2A
Soft-Start Current-Limit TimetSS200µs
INPUTS AND OUTPUTS
PGOOD Lower Trip ThresholdWith respect to feedback threshold,
hysteresis = 12mV-200-150-100mV
PGOOD Upper Trip ThresholdWith respect to feedback threshold,
hysteresis = 12mV100150200 mV
PGOOD Propagation DelaytPGOODOUTS forced 25mV beyond PGOOD trip
threshold51035µs
PGOOD Startup DelayStartup rising edge, OUTS within ±100mV of
the feedback threshold23.5ms
PGOOD Output Low VoltageISINK = 4mA0.3V
PGOOD Leakage CurrentIPGOODOUTS = REFIN (PGOOD high impedance),
PGOOD = VCC + 0.3V1µA
Logic high2.0SHDN Logic Input ThresholdLogic low0.8V
SHDN Logic Input CurrentSHDN = VCC or AGND-1+1µA
MAX8794
Low-Voltage DDR Linear Regulator
OUTPUT LOAD REGULATION
MAX8794 toc01
IOUT (A)
OUT
(V)
VREFIN = 0.9V
VIN = 1.5V
VIN = 1.25V
OUTPUT LOAD REGULATION
MAX8794 toc02
IOUT (A)
OUT
(V)
VREFIN = 1.25V
VIN = 1.8V
VIN = 1.5V
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
MAX8794 toc03
INPUT VOLTAGE (V)
MAXIMUM OUTPUT CURRENT (A)
DROPOUT VOLTAGE LIMITED
THERMALLY LIMITED
VOUT = 1.25VVOUT = 0.9V
BIAS CURRENT (ICC)
vs. INPUT VOLTAGE (VIN)
MAX8794 toc05
VIN (V)
(mA)
VOUT = 1.25V
DROPOUT
INPUT UVLO
BIAS CURRENT (ICC)
vs. LOAD CURRENT (IOUT)
MAX8794 toc06
IOUT (A)
(mA)0-1
VIN = 1.5V
VOUT = 1.25V
VOUT = 0.90V
ENTERING
DROPOUT
POWER GROUND CURRENT (IPGND)
vs. SOURCE LOAD CURRENT (IOUT)
MAX8794 toc07
IOUT (A)
IPGND
(mA)
VOUT = 1.25V
VOUT = 0.90V
VIN = 1.5V
ENTERING
DROPOUT
INPUT CURRENT (IIN)
vs. SINK LOAD CURRENT (IOUT)
MAX8794 toc08
IOUT (A)
(mA)
VIN = 1.5V
VOUT = 0.90V
VOUT = 1.25V
DROPOUT VOLTAGE
vs. OUTPUT CURRENT
MAX8794 toc09
OUTPUT CURRENT (A)
DROPOUT VOLTAGE (V)
VOUT = 1.25V
VOUT = 0.9V
Typical Operating Characteristics
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
INPUT CURRENT (IIN)
vs. INPUT VOLTAGE (VIN)
MAX8794 toc04
VIN (V)
IIN
VOUT = 1.25V
VOUT = 0.90V
MAX8794
SHUTDOWN WAVEFORM
MAX8794 toc12
100μs/div
VOUT
PGOOD
SHDNRLOAD = 100Ω
SOURCE LOAD TRANSIENT
MAX8794 toc13
20.0μs/div
1mV/div
VOUT
AC-COUPLED
IOUT
Low-Voltage DDR Linear Regulator
SOURCE/SINK LOAD TRANSIENT
MAX8794 toc14
4.00μs/div
+1.5A
5mV/div
-1.5A
VOUT
AC-COUPLED
IOUT
LINE TRANSIENT
MAX8794 toc15
40μs/div
3.3V
0.9V
1.5V
VIN (1V/div)
VOUT (10mV/div)
AC-COUPLED
IOUT = 100mA
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
REFOUT VOLTAGE ERROR
vs. REFOUT LOAD CURRENT
MAX8794 toc10
REFOUT LOAD CURRENT (mA)
REFOUT VOLTAGE ERROR (mV)
STARTUP WAVEFORM
MAX8794 toc11
500μs/div
1.25V
PGOOD
VOUT
SHDN
MAX8794
Low-Voltage DDR Linear Regulator
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX8794 toc16
20.0μs/div
2.5V
0.9V
0.9V
1.8V
1.2V
1.2V
VREFOUT
VDDQ
VOUT
VIN = 1.5V
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX8794 toc17
20.0μs/div
2.5V
0.9V
0.9V
1.8V
1.2V
1.2V
VREFOUT
VDDQ
VOUT
VIN = 1.8V
SINK CURRENT-LIMIT
DISTRIBUTION
MAX8794 toc18
SINK CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 200+25°C
+85°C
SOURCE CURRENT-LIMIT
DISTRIBUTION
MAX8794 toc19
SOURCE CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 200+25°C
+85°C
MAX8794
Low-Voltage DDR Linear Regulator
PINNAMEFUNCTIONREFOUTBuffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
2VCCAnalog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or
greater ceramic capacitor.AGNDAnalog Ground. Connect the backside pad to AGND.REFINExternal Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN).PGOOD
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.OUTS
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ
resistor.SHDNShutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the
linear regulator. The reference buffer remains active in shutdown.PGNDPower Ground. Internally connected to the output sink MOSFET.OUTOutput of the Linear RegulatorINPower Input. Internally connected to the output source MOSFET.
—EPExposed Pad. Connected to a large AGND ground plane with multiple vias to maximize thermal
performance.
Pin Description

Partno	Mfg	Dc	Qty	Available	Descript
MAX8794ETB+	MAXIM	N/a	60000	avai	Low-Voltage DDR Linear Regulator
MAX8794ETB+T	MAXIM	N/a	3986	avai	Low-Voltage DDR Linear Regulator