MAX8550AETI+ ,Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic CardsApplications6 16POK2 OUTDDR I and DDR II Memory Power Supplies7 15 FBDesktop Computers STBYNotebook ..
MAX8550ETI ,Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic Cardsapplications,Ordering Informationdoes not offer the pulse-skip feature.The VTT and VTTR outputs tra ..
MAX8550ETI ,Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic Cardsfeatures make the ♦ 1.7ms Digital Soft-Start and IndependentShutdownMAX8550/MAX8551 ideally suited ..
MAX8550ETI ,Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic CardsELECTRICAL CHARACTERISTICS(V = +15V, V = AV = V = V = V = V = 5V, V = V = V = 2.5V, UVP/OVP = STBY ..
MAX8550ETI+ ,Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic CardsApplicationsPOK2 6 16 OUTDDR I and DDR II Memory Power SuppliesSTBY 7 15 FBDesktop ComputersNoteboo ..
MAX8550ETI+T ,Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic CardsApplicationsPOK2 6 16 OUTDDR I and DDR II Memory Power SuppliesSTBY 7 15 FBDesktop ComputersNoteboo ..
MB8264A-10 , MOS 65536-BIT DYNAMIC RANDOM ACCESS MEMORY
MB8264A-10 , MOS 65536-BIT DYNAMIC RANDOM ACCESS MEMORY
MB8264A-10 , MOS 65536-BIT DYNAMIC RANDOM ACCESS MEMORY
MB82D01171A-80LLPBN , 16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory
MB82D01171A-80LLPBN , 16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory
MB82D01171A-90LLPBT , 16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory
MAX8550AETI+
Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards
General DescriptionThe MAX8550A integrates a synchronous-buck PWM
controller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT, and a 10mA reference
output buffer to generate VTTR. The buck controller drives
two external n-channel MOSFETs to generate output volt-
ages down to 0.7V from a 2V to 28V input with output cur-
rents up to 15A. The LDO can sink or source up to 1.5A
continuous and 3A peak current. Both the LDO output
and the 10mA reference buffer output can be made to
track the REFIN voltage. These features make the
MAX8550A ideally suited for DDR memory applications in
desktops, notebooks, and graphic cards.
The PWM controller in the MAX8550A utilizes Maxim’s
proprietary Quick-PWM™ architecture with programma-
ble switching frequencies of up to 600kHz. This control
scheme handles wide input/output voltage ratios with
ease and provides 100ns response to load transients
while maintaining high efficiency and a relatively con-
stant switching frequency. The MAX8550A offers fully
programmable UVP/OVP and skip-mode options ideal in
portable applications. Skip mode allows for improved
efficiency at lighter loads.
The VTT and VTTR outputs track to within 1% of VREFIN/ 2.
The high bandwidth of this LDO regulator allows excel-
lent transient response without the need for bulk capac-
itors, thus reducing cost and size.
The buck controller and LDO regulators are provided with
independent current limits. Adjustable lossless foldback
current limit for the buck regulator is achieved by monitor-
ing the drain-to-source voltage drop of the low-side
MOSFET. Additionally, overvoltage and undervoltage pro-
tection mechanisms are built in. Once the overcurrent
condition is removed, the regulator is allowed to enter
soft-start again. This helps minimize power dissipation
during a short-circuit condition. The MAX8550A allows
flexible sequencing and standby power management
using the SHDNand STBYinputs, which support all
DDRs’ operating states.
The MAX8550A is available in a small 5mm ×5mm, 28-
pin thin QFN package.
ApplicationsDDR I and DDR II Memory Power Supplies
Desktop Computers
Notebooks and Desknotes
Graphic Cards
Game Consoles
RAID
Networking
Features
Buck ControllerQuick-PWM with 100ns Load-Step ResponseUp to 95% Efficiency2V to 28V Input Voltage Range1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable OutputUp to 600kHz Selectable Switching FrequencyProgrammable Current Limit with Foldback
Capability1.7ms Digital Soft-Start Independent Shutdown and Standby ControlsOvervoltage/Undervoltage-Protection OptionPower-Good Window Comparator
LDO SectionFully Integrated VTT and VTTR CapabilityVTT Has ±3A Sourcing/Sinking CapabilityVTT and VTTR Outputs Track VREFIN/ 2All-Ceramic Output-Capacitor Designs1.0V to 2.8V Input Voltage RangePower-Good Window Comparator
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
PARTTEMP RANGEPIN-PACKAGEMAX8550AETI-40°C to +85°C28 TQFN 5mm × 5mm
Ordering Information8121314282524232226
MAX8550A
5mm x 5mm Thin QFNTOP VIEW
OVP/UVP
TON
REF
ILIM
POK1
POK2
TPOAV
GND
PGND1
BST
VIN
OUT
REFIN
VTTIVTT
PGND2
VTTRVTTS
SHDN
SKIP
STBY
Pin Configuration19-3313; Rev 0; 5/04
Typical Operating Circuit appears at end of data sheet.
EVALUATION KIT
AVAILABLEQuick-PWM is a trademark of Maxim Integrated Products, Inc.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
MAIN PWM CONTROLLERVIN228Input Voltage RangeVDD, AVDD4.55.5V
Output Adjust RangeVOUT0.75.5V
FB = OUT0.6930.70.707
FB = GND2.472.52.53Output Voltage Accuracy
(Note 2)
FB = VDD1.781.81.82
Soft-Start Ramp TimetSSRising edge of SHDN to full current limit1.7ms
TON = GND (600kHz)170194219
TON = REF (450kHz)213243273
TON = OPEN (300kHz)316352389On-TimetON
VIN = 15V,
VOUT = 1.5V
(Note 3)
TON = AVDD (200kHz)461516571
Minimum Off-TimetOFF_MIN(Note 3)200300450ns
VIN Quiescent Supply CurrentIIN2540µA
VIN Shutdown Supply CurrentSHDN = GND15µA
All on (PWM, VTT, and VTTR on)2.55AVDD Quiescent Supply CurrentIAVDDSTBY = GND (only VTTR and PWM on)12mA
AVDD + VDD Shutdown Supply
CurrentSHDN = GND210µA
Rising edge of VIN4.054.254.40VAVDD Undervoltage-Lockout
ThresholdHysteresis50mV
VDD Quiescent Supply CurrentIVDDSet VFB = 0.8V15µA
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VIN= +15V, VDD= AVDD= VSHDN= STBY= VBST= VILIM= 5V, VOUT= VREFIN= VVTTI= 2.5V, UVP/OVP = TP0 = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS= VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VINto GND.............................................................-0.3V to +30V
VDD, AVDD, VTTI to GND.........................................-0.3V to +6V
SHDN, REFIN to GND..............................................-0.3V to +6V
SS, POK1, POK2, SKIP, ILIM, FB to GND................-0.3V to +6V
STBY, TON, REF, UVP/OVP to GND........-0.3V to (AVDD+ 0.3V)
OUT, VTTR to GND..................................-0.3V to (AVDD+ 0.3V)
DL to PGND1..............................................-0.3V to (VDD+ 0.3V)
DH to LX....................................................-0.3V to (VBST+ 0.3V)
LX to BST..................................................................-6V to +0.3V
LX to GND.................................................................-2V to +30V
VTT to GND...............................................-0.3V to (VVTTI+ 0.3V)
VTTS to GND............................................-0.3V to (AVDD+ 0.3V)
PGND1, PGND2, TP0 to GND...............................-0.3V to +0.3V
REF Short Circuit to GND...........................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin 5mm x 5mm TQFN (derate 35.7mW/°C
above +70°C).................................................................2.86W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10s).................................+300°C
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
REFERENCEReference VoltageVREFAVDD = 4.5V to 5.5V; IREF = 01.9822.02V
Reference Load RegulationIREF = 0 to 50µA0.01V
VREF rising1.93VREF Undervoltage LockoutHysteresis300mV
FAULT DETECTIONOVP Trip Threshold
(Referred to Nominal VOUT)UVP/OVP = AVDD (Note 4)112116120%
UVP Trip Threshold
(Referred to Nominal VOUT)657075%
Lower level, falling edge, 1% hysteresis879093POK1 Trip Threshold
(Referred to Nominal VOUT)Upper level, rising edge, 1% hysteresis107110113%
Lower level, falling edge, 1% hysteresis87.59092.5POK2 Trip Threshold
(Referred to Nominal VVTTS
and VVTTR)Upper level, rising edge, 1% hysteresis107.5110112.5
POK2 Disable Threshold
(Measured at REFIN)VREFIN rising (hysteresis = 75mV typ)0.70.9V
UVP Blanking TimeFrom rising edge of SHDN102040ms
OVP, UVP, POK_ Propagation
Delay10µs
POK_ Output Low VoltageISINK = 4mA0.3V
POK_ Leakage CurrentVPOK_ = 5.5V, VFB = 0.8V, VVTTS = 1.3V1µA
ILIM Adjustment RangeVILIM0.252.00V
ILIM Input Leakage Current0.1µA
Current-Limit Threshold (Fixed)
PGND1 to LX455055mV
Current-Limit Threshold
(Adjustable) PGND1 to LXVILIM = 2V170200235mV
Current-Limit Threshold (Fixed,
Negative Direction) PGND1 to LXSKIP = AVDD-75-60-45mV
Current-Limit Threshold
(Adjustable, Negative Direction)
PGND1 to LX
SKIP = AVDD, VILIM = 2V-250mV
Zero-Crossing Detection
Threshold PGND1 to LX3mV
Thermal-Shutdown Threshold+160°C
Thermal-Shutdown Hysteresis15°C
ELECTRICAL CHARACTERISTICS (continued)(VIN= +15V, VDD= AVDD= VSHDN= STBY= VBST= VILIM= 5V, VOUT= VREFIN= VVTTI= 2.5V, UVP/OVP = TP0 = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS= VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at TA= +25°C.) (Note 1)
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
MOSFET DRIVERSDH Gate-Driver On-ResistanceVBST - VLX = 5V14Ω
DL Gate-Driver On-Resistance in
High State14Ω
DL Gate-Driver On-Resistance in
Low State0.53Ω
DH falling to DL rising 30Dead Time (Additional to
Adaptive Delay)DL falling to DH rising 30ns
INPUTS AND OUTPUTSRising edge1.201.72.20VLogic Input Threshold
(SHDN, STBY, SKIP)Hysteresis225mV
Logic Input Current
(SHDN, STBY, SKIP)-1+1µA
Low (2.5V output)0.05Dual-Mode™ Input Logic
Levels (FB)High (1.8V output)2.1V
Input Bias Current (FB)-0.1+0.1µA
HighAVDD -
Floating3.153.85
REF1.652.35
Four-Level Input Logic Levels
(TON, OVP/UVP)
Low0.5
Logic Input Current
(TON, OVP/UVP)-3+3µA
FB = GND90175350
FB = AVDD70135270OUT Input Resistance
FB adjustable mode4008001600
OUT Discharge-Mode
On-Resistance1025Ω
DL Turn-On Level During
Discharge Mode
(Measured at OUT)
0.010.10.20V
ELECTRICAL CHARACTERISTICS (continued)(VIN= +15V, VDD= AVDD= VSHDN= STBY= VBST= VILIM= 5V, VOUT= VREFIN= VVTTI= 2.5V, UVP/OVP = TP0 = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS= VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at TA= +25°C.) (Note 1)
Dual Mode is a trademark of Maxim Integrated Products, Inc.
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Note 1:Specifications to -40°C are guaranteed by design, not production tested.
Note 2:When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-compara-
tor threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the
trip level by approximately 1.5% due to slope compensation.
Note 3:On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST= 5V,
and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LINEAR REGULATORS (VTTR AND VTT)VTTI Input Voltage RangeVVTTI1
2.8V
VTTI Supply CurrentIVTTIIVTT = IVTTR = 0<0.11mA
VTTI Shutdown CurrentSHDN = GND10µA
REFIN Input ImpedanceVREFIN = 2.5V122030kΩ
REFIN RangeVREFIN1 2.8V
VTT, VTTR UVLO Threshold
(Measured at OUT)0.010.10.20V
Soft-Start Charge CurrentISSVSS = 04µA
VTT Internal MOSFET High-Side
On-Resistance
IVTT = -100mA, VVTTI = 1.5V,
AVDD = 4.5V0.3Ω
VTT Internal MOSFET Low-Side
On-ResistanceIVTT = 100mA, AVDD = 4.5V0.3Ω
VTT Output Accuracy
(Referred to VREFIN / 2)VREFIN = 1.5V or 2.5V, IVTT = 1mA-1+1%
VREFIN = 2.5V, IVTT = 0 to ±1.5A1VTT Load RegulationVREFIN = 1.5V, IVTT = 0 to ±1A1%
VTT Current LimitVTT = 0 or VTTI±3±5±6.5A
VTTS Input CurrentIVTTSVVTTS = 1.5V, VTT open 0.1 1µA
VTTR Output Error
(Referred to VREFIN / 2)VREFIN = 1.5V or 2.5V, IVTTR = 0-1+1%
VTTR Current LimitVVTTR = 0 or VVTTI±18±32±50mA
ELECTRICAL CHARACTERISTICS (continued)(VIN= +15V, VDD= AVDD= VSHDN= STBY= VBST= VILIM= 5V, VOUT= VREFIN= VVTTI= 2.5V, UVP/OVP = TP0 = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS= VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at TA= +25°C.) (Note 1)
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Typical Operating Characteristics(VVIN= 12V, VOUT= 2.5V, TON = GND, SKIP= AVDD, circuit of Figure8, TA= +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(TON = GND)MAX8550A toc01
ILOAD (A)
EFFICIENCY (%)10.1
fSW = 600kHz
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
SKIP = GND
SKIP = AVDD
EFFICIENCY vs. LOAD CURRENT
(TON = OPEN)MAX8550A toc02
ILOAD (A)
EFFICIENCY (%)10.1
fSW = 300kHz
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
SKIP = GND
SKIP = AVDD
SWITCHING FREQUENCY vs. LOAD CURRENT
(TON = GND)MAX8550A toc03
ILOAD (A)
FREQUENCY (kHz)10892345671
SKIP = GND
SKIP = AVDD
SWITCHING FREQUENCY vs. INPUT VOLTAGE
(TON = GND)MAX8550A toc04
VIN (V)
FREQUENCY (kHz)242022810121416186
ILOAD = 12A
ILOAD = 0A
SWITCHING FREQUENCY vs. TEMPERATURE
(TON = GND)MAX8550A oc05
TEMPERATURE (°C)
FREQUENCY (kHz)655035205-10-25
ILOAD = 12A
OUTPUT VOLTAGE
vs. LOAD CURRENTMAX8550A toc06
ILOAD (A)
OUT
(V)106842
VIN = 15V,
TON = GND
SKIP = GND
SKIP = AVDD
VTT VOLTAGE
vs. VTT CURRENTMAX8550A toc07
IVTT (A)
VTT
(V)1-2-10
VTTR VOLTAGE
vs. VTTR CURRENT
MAX8550A toc08
IVTTR (mA)
VTTR
(V)5-10-50
LINE REGULATION
(VOUT vs. VIN)
MAX8550A toc09
VIN (V)
OUT242022810121416186
ILOAD = 0A
ILOAD = 12A
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
LOAD TRANSIENT (BUCK)MAX8550A toc10
20μs/div
12A
VOUT
100mV/div
VTT
100mV/div
VTTR
100mV/div
ILOAD
10A/div0.1A
IVTT = 1.5A, IVTTR = 15mA
LOAD TRANSIENT VTT (-1.5A TO +1.5A)MAX8550A toc11
40μs/div
VOUT
50mV/div
VTT
50mV/div
VTTR
50mV/div
IVTT
2A/div0A
ILOAD = 12A, IVTTR = 15mA
LOAD TRANSIENT VTT (-3A TO +3A)MAX8550A toc12
40μs/div
VOUT
50mV/div
VTT
50mV/div
VTTR
50mV/div
IVTT
5A/div0A
ILOAD = 12A, IVTTR = 15mA
POWER-UP WAVEFORMSMAX8550A toc13
200μs/div
OUT
1V/div
VTT
2V/div
VTTR
1V/div
VIN
10V/div0V
VDD = 5V, ILOAD = 12A, IVTT = 1.5A, IVTTR = 15mA
POWER-DOWN WAVEFORMSMAX8550A toc14
200μs/div
OUT
1V/div
VTT
2V/div
VTTR
1V/div
VIN
10V/div0V
VDD = 5V, ILOAD = 12A, IVTT = 1.5A, IVTTR = 15mA
STARTUP AND SHUTDOWN INTO
HEAVY LOAD, DISCHARGE DISABLEDMAX8550A toc15
1ms/div
VOUT
2V/div
VTT
1V/div
SHDN
5V/div
POK1
5V/div
ILOAD = 12A,
IVTT = 1.5A
Typical Operating Characteristics (continued)(VVIN= 12V, VOUT= 2.5V, TON = GND, SKIP= AVDD, circuit of Figure 8, TA= +25°C, unless otherwise noted.)
STARTUP AND SHUTDOWN INTO
LIGHT LOAD, DISCHARGE ENABLEDMAX8550A toc16
2ms/div
VOUT
VTT
VTTR
10V/div
500mV/div
500mV/div
500mV/div
SHDN1.8V
0.9V
0.9V
STANDBY RESPONSE
VTT LOADED AT 10Ω TO GNDMAX8550A toc17a
2ms/div
500mV/div
500mV/div
500mV/div
5V/div
VOUT
VTT
VTTR
STBY
1.8V
0.9V
0.9V
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
STANDBY RESPONSE, VTT AT NO LOADMAX8550A toc17b
2ms/div
500mV/div
500mV/div
500mV/div
5V/div
VOUT
VTT
VTTR
STBY
1.8V
0.9V
0.9V
ypical Operating Characteristics (continued)(VVIN= 12V, VOUT= 2.5V, TON = GND, SKIP= AVDD, circuit of Figure8, TA= +25°C, unless otherwise noted.)
OVERVOLTAGE AND TURN-OFF
OF BUCK OUTPUTMAX8550A toc18
20μs/div
VOUT
2V/div
25A/div
5V/div
20V/div
SHORT CIRCUIT AND
RECOVERY OF VDDQMAX8550A toc19
400μs/div
VOUT
2V/div
ILOAD
10A/div
VIN
10V/div
IIN
2A/div0A
UVP DISABLED, FOLDBACK CURRENT LIMIT
SHORT CIRCUIT AND
RECOVERY OF VDDQMAX8550A toc20
400μs/div
VOUT
2V/div
ILOAD
10A/div
VIN
10V/div
IIN
2A/div
UVP ENABLED
SHORT CIRCUIT OF VTTMAX8550A toc21
400μs/div
VTT
1V/div
IVTT
5A/div0A
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Pin Description
PINNAMEFUNCTION1TON
On-Time Selection-Control Input. This four-level logic input sets the nominal DH on-time. Connect to
GND, REF, AVDD, or leave TON unconnected to select the following nominal switching frequencies:
TON = AVDD (200kHz)
TON = OPEN (300kHz)
TON = REF (450kHz)
TON = GND (600kHz)OVP/
UVP
Overvoltage/Undervoltage-Protection Control Input. This four-level logic input enables or disables the
overvoltage and/or undervoltage protection. The overvoltage limit is 116% of the nominal output
voltage. The undervoltage limit is 70% of the nominal output voltage. Discharge mode is enabled when
OVP is also enabled. Connect the OVP/UVP pin to the following pins for the desired function:
OVP/UVP = AVDD (Enable OVP and discharge mode, enable UVP.)
OVP/UVP = OPEN (Enable OVP and discharge mode, disable UVP.)
OVP/UVP = REF (Disable OVP and discharge mode, enable UVP.)
OVP/UVP = GND (Disable OVP and discharge mode, disable UVP.)REF
+2.0V Reference Voltage Output. Bypass to GND with a 0.1µF (min) capacitor. REF can supply 50µA
for external loads. Can be used for setting voltage for ILIM. REF turns off when SHDN is low and
OUT < 0.1V.ILIM
Valley Current-Limit Threshold Adjustment for Buck Regulator. The current-limit threshold across PGND
and LX is 0.1 times the voltage at ILIM. Connect ILIM to a resistive divider, typically from REF to GND,
to set the current-limit threshold between 25mV and 200mV. This corresponds to a 0.25V to 2V range at
ILIM. Connect ILIM to AVDD to select the 50mV default current-limit threshold. See the Setting the
Current Limit section.POK1
Buck Power-Good Open-Drain Output. POK1 is low when the buck output voltage is more than 10%
above or below the normal regulation point or during soft-start. POK1 is high impedance when the
output is in regulation and the soft-start circuit has terminated. POK1 is low in shutdown.POK2
LDO Power-Good Open-Drain Output. In normal mode, POK2 is low when either VTTR or VTTS is more
than 10% above or below the normal regulation point, which is typically REFIN / 2. In standby mode,
POK2 responds only to the VTTR input. POK2 is low in shutdown, and when VREFIN is less than 0.8V.STBYStandby. Connect to GND for low-quiescent mode where the VTT output is open circuit. POK2 takes
input from only VTTR in this mode. PWM output can be on or off, depending on the state of SHDN.
8SS
Soft-Start Control for VTT. Connect a capacitor (C9 in the Typical Applications Circuit) from SS to
ground (see the Soft-Start Capacitor Selection section). Leave SS open to disable soft-start.
SS discharges to ground when VTT is off. See the POR, UVLO, and Soft-Start section.VTTS
Sensing Pin for Termination Supply Output. Normally connected to VTT pin to allow accurate regulation
to half the REFIN voltage. Connected to a resistive divider from VTT to GND to regulate VTT to higher
than half the REFIN voltage.VTTRTermination Reference Voltage. VTTR tracks VREFIN / 2.
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Pin Description (continued)
PINNAMEFUNCTIONPGND2Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad.VTTTermination Power-Supply Output. Connect VTT to VTTS to regulate to VREFIN / 2.VTTIPower-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator
for DDR application.REFINExternal Reference Input. This is used to regulate the VTT and VTTR outputs to VREFIN / 2.FB
Feedback Input for Buck Output. Connect to AVDD for a +1.8V fixed output or to GND for a +2.5V fixed
output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output
voltage. FB regulates to +0.7V.OUT
Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor.
OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the
Typical Applications Circuit). OUT also serves as the buck output’s feedback input in fixed-output
modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an
internal 10Ω resistor connected between OUT and GND. OUT also acts as the input to the VTT and
VTTR UVLO detector.VINInput-Voltage Sense Connection. Connect to input power source. VIN is used only to set the PWM’s on-
time one-shot timer. IN voltage range is from 2V to 28V.DHHigh-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.LXExternal Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current
limit and the return supply of the DH driver.BSTBoost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the
Typical Applications Circuit (Figure 8). See the Boost-Supply Diode and Capacitor Selection section.DLSynchronous-Rectifier Gate-Driver Output. Swings from PGND to VDD.VDDSupply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to
PGND1 with a 1µF (min) ceramic capacitor.PGND1Power Ground for Buck Controller. Connect PGND1 externally to the underside of the exposed pad.GNDAnalog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad.SKIPPulse-Skipping Control Input. Connect to AVDD for low-noise, forced-PWM mode. Connect to GND to
enable pulse-skipping operation.AVDDAnalog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage
with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor.SHDNShutdown Control Input. Use to control buck output. A rising edge on SHDN clears the overvoltage-
and undervoltage-protection fault latches (see Tables 2 and 3). Connect to AVDD for normal operation.TP0This is a test pin. Must connect to GND externally.
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic CardsMAX8550A
ON-TIME
COMPUTE
tON
ONE-SHOT
1.0V
1.16 x INTREF
OVP/UVP
LATCH
QUAD LEVEL
DECODE
20ms
TIMER
0.7 x INTREF
INTREF
DECODE
DISCHARGE
LOGICN
REFERENCE
INTREF
VOUT = 1.8V
VOUT = 2.5V
INTREF + 10%INTREF - 10%
POWER-DOWN
0.1VOUT
10kΩ10kΩ
REFIN / 2REFIN / 2 - 10%REFIN / 2 + 10%
REFIN / 2 - 10%REFIN / 2 + 10%
BST
VDD
PGND
ILIM
VDD - 1V
OUT
AVDD
GND
REF
REFIN
VTT
VDD
VDD
PGND2
VTTR
POK2
POK1
OVP/UVP
TON
tOFF
TRIG
ONE-SHOT
TRIG
ZERO CROSSING
VTTS
VTTI
CURRENT
LIMITS
VTT ILIM
TP0SHUTDOWN
DECODER
BUCK ON/OFF
VTT ON/OFFVTTR ON/OFF
BIAS ON/OFF
SHDN
STBY
SKIP
VTTI
PGND2
OUT
Figure1. Functional Diagram
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Detailed DescriptionThe MAX8550A combines a synchronous-buck PWM con-
troller, an LDO linear regulator, and a 10mA reference out-
put buffer. The buck controller drives two external
n-channel MOSFETs to deliver load currents up to 12A
and generate voltages down to 0.7V from a +2V to +28V
input. The LDO linear regulator can sink and source up to
1.5A continuous and 3A peak current with relatively fast
response. These features make the MAX8550/MAX8551
ideally suited for DDR memory applications.
The MAX8550A buck regulator is equipped with a fixed
switching frequency of up to 600kHz using Maxim’s
proprietary constant on-time Quick-PWM architecture.
This control scheme handles wide input/output voltage
ratios with ease, and provides 100ns “instant-on”
response to load transients, while maintaining high effi-
ciency with relatively constant switching frequency.
The buck controller, LDO, and a reference output
buffer are provided with independent current limits.
Lossless foldback current limit in the buck regulator is
achieved by monitoring the drain-to-source voltage
drop of the low-side FET. The ILIM input is used to
adjust this current limit. Overvoltage protection, if
selected, is achieved by latching the low-side synchro-
nous FET on and the high-side FET off when the output
voltage is over 116% of its set output. It also features
an optional undervoltage protection by latching the
MOSFET drivers to the OFF state during an overcurrent
condition, when the output voltage is lower than 70% of
the regulated output. This helps minimize power dissi-
pation during a short-circuit condition.
The current limit in the LDO and buffered reference out-
put buffer is ±5A and ±32mA, respectively, and neither
have the over- or undervoltage protection. When the
current limit in either output is reached, the output no
longer regulates the voltage, but regulates the current
to the value of the current limit.
+5V Bias Supply (VDDand AVDD)The MAX8550A requires an external +5V bias supply in
addition to the input voltage (VIN). Keeping the bias sup-
ply external to the IC improves the efficiency and elimi-
nates the cost associated with the +5V linear regulator
that would otherwise be needed to supply the PWM cir-
cuit and the gate drivers. If stand-alone capability is
needed, then the +5V supply can be generated with an
external linear regulator such as the MAX1615. VDD,
AVDD, and IN can be connected together if the input
source is a fixed +4.5V to +5.5V supply.
VDDis the supply input for the buck regulator’s MOSFET
drivers, and AVDDsupplies the power for the rest of
the IC. The current from the AVDDand VDDpower
supply must supply the current for the IC and the gate
drive for the MOSFETs. This maximum current can be
estimated as:
where IVDD+ IAVDDare the quiescent supply currents
into VDDand AVDD, QG1and QG2are the total gate
charges of MOSFETs Q1 and Q2 (at VGS= 5V) in the
Typical Applications Circuit, and fSWis the switching
frequency.
Free-Running Constant-On-Time PWMThe Quick-PWM control architecture is a pseudo-fixed-
frequency, constant on-time, current-mode regulator
with voltage feed-forward (Figure1). This architecture
relies on the output filter capacitor’s ESR to act as a
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined
solely by a one-shot whose pulse width is inversely pro-
portional to input voltage and directly proportional to
the output voltage. Another one-shot sets a minimum
off-time of 300ns (typ). The on-time one-shot is trig-
gered if the error comparator is low, the low-side switch
current is below the valley current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to input and output voltages. The high-side
switch on-time is inversely proportional to the input volt-
age (VIN) and is proportional to the output voltage:
where K (the switching period) is set by the TON input
connection (Table1) and RDS(ON)Q2is the on-resis-
tance of the synchronous rectifier (Q2) in the Typical
Applications Circuit(Figure8). This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. The benefits of a
constant switching frequency are twofold:The frequency can be selected to avoid noise-sensi-
tive regions such as the 455kHz IF band.The inductor ripple-current operating point remains
relatively constant, resulting in an easy design
methodology and predictable output voltage ripple.VIRON
OUTLOADDSONQ ()=×+×()2IfQQBIASVDDAVDDSWGG =++×+()12
The on-time one-shot has good accuracy at the operat-
ing points specified in the Electrical Characteristics
table(approximately ±12.5% at 600kHz and 450kHz,
and ±10% at 200kHz and 300kHz). On-times at operat-
ing points far removed from the conditions specified in
the Electrical Characteristicstablecan vary over a
wider range. For example, the 600kHz setting typically
runs approximately 10% slower with inputs much
greater than 5V due to the very short on-times required.
The constant on-time translates only roughly to a con-
stant switching frequency. The on-times guaranteed in
the Electrical Characteristicstableare influenced by
resistive losses and by switching delays in the high-
side MOSFET. Resistive losses, which include the
inductor, both MOSFETs, the output capacitor’s ESR,
and any PC board copper losses in the output and
ground, tend to raise the switching frequency as the
load increases. The dead-time effect increases the
effective on-time, reducing the switching frequency as
one or both dead times are added to the effective on-
time. The dead time occurs only in PWM mode (SKIP=
VDD) and during dynamic output-voltage transitions
when the inductor current reverses at light or negative
load currents. With reversed inductor current, the induc-
tor’s EMF causes LX to go high earlier than normal,
extending the on-time by a period equal to the DH-rising
dead time. For loads above the critical conduction point,
where the dead-time effect is no longer a factor, the
actual switching frequency is:
where VDROP1is the sum of the parasitic voltage drops
in the inductor discharge path, including the synchro-
nous rectifier, the inductor, and any PC board resis-
tances; VDROP2is the sum of the resistances in the
charging path, including the high-side switch (Q1 in the
Typical Applications Circuit), the inductor, and any PC
board resistances, and tON is the one-shot on-time (see
the On-Time One-Shot (TON)section.
Automatic Pulse-Skipping Mode
(SKIP= GND)In skip mode (SKIP= GND), an inherent automatic
switchover to PFM takes place at light loads (Figure2).
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The zero-crossing comparator
differentially senses the inductor current across the
synchronous-rectifier MOSFET (Q2 in the Typical
Applications Circuit, Figure8). Once VPGND- VLX
drops below 5% of the current-limit threshold (2.5mV
for the default 50mV current-limit threshold), the com-
parator forces DL low (Figure1). This mechanism caus-
es the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation (also known as the critical
conduction point). The load-current level at which
PFM/PWM crossover occurs, ILOAD(SKIP), is equal to
half the peak-to-peak ripple current, which is a function
of the inductor value (Figure2). This threshold is rela-
tively constant, with only a minor dependence on the
input voltage (VIN):
where K is the on-time scale factor (see Table1). For
example, in the Typical Applications Circuitof Figure8
(K = 1.7µs, VOUT= 2.5V, VIN= 12V, and L = 1µH), the
pulse-skipping switchover occurs at:
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used. The switch-
ing waveforms can appear noisy and asynchronous
when light loading causes pulse-skipping operation,
but this is a normal operating condition that results in
high light-load efficiency. Trade-offs in PFM noise vs.
light-load efficiency are made by varying the inductor
value. Generally, low inductor values produce a broad-
er efficiency vs. load curve, while higher values result in
higher full-load efficiency (assuming that the coil resis-172168. . .VsA×⎜⎞⎟⎛⎜⎞⎟=μ .5VVKLOADSKIPOUTINOUT() =×⎛⎜⎞⎟⎛⎜⎞⎟2VVVSWOUTDROPINDROP =+()
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Table1. Approximate K-Factor Errors
TON SETTING
TYPICAL
FACTOR
(µs)
K-FACTOR
ERROR
(%)
MINIMUM VIN AT
VOUT = 2.5V
(h = 1.5; SEE THE
DROPOUT
PERFORMANCE
SECTION)(TON = AVDD)5.0±103.15
(TON = OPEN)3.3±103.47
(TON = REF)2.2±12.54.13
(TON = GND)1.7±12.55.61
MAX8550Atance remains fixed) and less output voltage ripple.
Penalties for using higher inductor values include larger
physical size and degraded load-transient response,
especially at low input-voltage levels.
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continu-
ous conduction, the MAX8550A regulates the valley of
the output ripple, so the actual DC output voltage is
higher than the trip level by 50% of the output ripple
voltage. In discontinuous conduction (SKIP= GND and
ILOAD< ILOAD(SKIP)), the output voltage has a DC regu-
lation level higher than the error-comparator threshold
by approximately 1.5% due to slope compensation.
Forced-PWM Mode (SKIP= AVDD)The low-noise forced-PWM mode (SKIP= AVDD) dis-
ables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gate-
drive waveform to constantly be the complement of the
high-side gate-drive waveform, so the inductor current
reverses at light loads while DH maintains a duty factor
of VOUT/ VIN. Forced-PWM mode keeps the switching
frequency fairly constant. However, forced-PWM opera-
tion comes at a cost where the no-load VDDbias cur-
rent remains between 2mA and 20mA due to the
external MOSFET’s gate charge and switching frequen-
cy. Forced-PWM mode is most useful for reducing
audio frequency noise, improving load-transient
response, and providing sink-current capability for
dynamic output-voltage adjustment.
Current-Limit Buck Regulator (ILIM)
Valley Current LimitThe current-limit circuit for the buck regulator portion of
the MAX8550A employs a unique “valley” current-sens-
ing algorithm that senses the voltage drop across LX
and PGND1 and uses the on-resistance of the rectifying
MOSFET (Q2 in the Typical Applications Circuit, Figure
8) as the current-sensing element. If the magnitude of
the current-sense signal is above the valley current-limit
threshold, the PWM controller is not allowed to initiate a
new cycle (Figure4). With valley current-limit sensing,
the actual peak current is greater than the valley cur-
rent-limit threshold by an amount equal to the inductor
current ripple. Therefore, the exact current-limit charac-
teristic and maximum load capability are a function of
the current-sense resistance, inductor value, and input
voltage. When combined with the undervoltage-protec-
tion circuit, this current-limit method is effective in
almost every circumstance.
In forced-PWM mode, the MAX8550A also implements a
negative current limit to prevent excessive reverse induc-
tor currents when the buck regulator output is sinking
current. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
tracks the positive current limit when VILIMis adjusted.
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. A 2µA to 20µA divider current is
recommended for accuracy and noise immunity.
The current-limit threshold adjustment range is from
25mV to 200mV. In the adjustable mode, the current-
limit threshold voltage (from PGND1 to LX) is precisely
1/10th the voltage seen at ILIM. The threshold defaults
to 50mV when ILIM is connected to AVDD. The logic
threshold for switchover to the 50mV default value is
approximately AVDD- 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the differ-
ential current-sense signals seen between LX and GND.
POR, UVLO, and Soft-StartInternal power-on reset (POR) occurs when AVDDrises
above approximately 2V, resetting the fault latch and
the soft-start counter, powering up the reference, and
preparing the buck regulator for operation. Until AVDD
reaches 4.25V (typ), AVDDundervoltage-lockout
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic CardsFigure2. Pulse-Skipping/Discontinuous Crossover Point
INDUCTOR CURRENT
ON-TIME0TIME
IPEAK
ILOAD = IPEAK / 2Δt
VIN - VOUT=
(UVLO) circuitry inhibits switching. The controller
inhibits switching by pulling DH low and holding DL low
when OVP and shutdown discharge are disabled
(OVP/UVP = REF or GND) or forcing DL high when OVP
and shutdown discharge are enabled (OVP/UVP =
AVDDor OPEN). See Table3 for a detailed truth table
for OVP/UVP and shutdown settings. When AVDDrises
above 4.25V, the controller activates the buck regulator
and initializes the internal soft-start.
The buck regulator’s internal soft-start allows a gradual
increase of the current-limit level during startup to
reduce the input surge currents. The MAX8550A
divides the soft-start period into five phases. During the
first phase, the controller limits the current limit to only
20% of the full current limit. If the output does not reach
regulation within 425µs, soft-start enters the second
phase, and the current limit is increased by another
20%. This process repeats until the maximum current
limit is reached, after 1.7ms, or when the output reach-
es the nominal regulation voltage, whichever occurs
first. Adding a capacitor in parallel with the external
ILIM resistors creates a continuously adjustable analog
soft-start function for the buck regulator’s output.
Soft-start in the LDO section can be realized by con-
necting a capacitor between the SS pin and ground.
When VTT is turned off or placed in standby mode, or
during thermal shutdown of the LDOs, the SS capacitor
is discharged. When VTT is turned on or when the ther-
mal limit is removed, an internal 4µA (typ) current
charges the SS capacitor. The resulting ramp voltage
on SS linearly increases the current-limit comparator
threshold to the VTT output, until full current limit is
attained when SS reaches approximately 1.6V. This
lowering of the current limit during startup limits the ini-
tial inrush current peaks, particularly when driving
capacitors. Choose the value of the SS cap appropri-
ately to set the soft-start time window. Leave SS floating
to disable the soft-start feature.
MAX8550A
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic CardsFigure4. Valley Current-Limit Threshold
INDUCTOR CURRENT
ILOAD
ILIMITTIME
IPEAK
ILOAD(MAX)
ILIM(VAL) =1 - x ILOADLIR()
Figure3. Adjustable Current-Limit Threshold
ILIM
TO PWM
CONTROLLER
(SEE FIGURE 1)
VDD - 1V
MAX8550A
1.0V
CREF
CILIMRA
REF
