MAX77826EWJ+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX77826EWJ+T ,Power Management ICApplications• 3 x 300mA● GSM, GPRS, EDGE, CDMA WCDMA, and LTE • 6 PMOSLS LDOs (V Range: 0.8V to 3.9 ..
MAX778CSA , Low-Voltage-Input, 3V/3.3V/5V/Adjustable-Output, Step-Up DC-DC Converters
MAX778ESA , Low-Voltage-Input, 3V/3.3V/5V/Adjustable-Output, Step-Up DC-DC Converters
MAX778LCSA ,Low-Voltage Input, 3V/3.3V/5V/ Adjustable Output, Step-Up DC-DC ConvertersFeaturesThe MAX777L/MAX778L/MAX779L are pulse-skipping DC-DC' 1V to 4.5V Input Guarantees Start-Up ..
MAX778LESA ,Low-Voltage Input, 3V/3.3V/5V/ Adjustable Output, Step-Up DC-DC ConvertersMAX777L/MAX778L/MAX779L19-0186; Rev 2; 7/96Low-Voltage Input, 3V/3.3V/5V/Adjustable Output, Step-Up ..
MAX779CSA , Low-Voltage-Input, 3V/3.3V/5V/Adjustable-Output, Step-Up DC-DC Converters
MB6M ,MINIATURE GLASS PASSIVATED SINGLE-PHASE BRIDGE RECTIFIERThermal Characteristics (TA = 25°C unless otherwise noted)Parameter Symbol MB2M MB4M MB6M UnitDevic ..
MB6S ,Bridge RectifiersThermal Characteristics (T = 25°C unless otherwise noted)AParameter Symbol MB2S MB4S MB6S UnitDevic ..
MB7117E , Schottky TTL 2048-Bit Bipolar Programmable Read-Only Memory
MB71A38-25 , PROGRAMMABLE SCHOTTKY 16384-BIT READ ONLY MEMORY
MB8117800A-60 ,2 M X 8 BIT FAST PAGE MODE DYNAMIC RAMapplications where very low power dissipation and high bandwidth are basic requirements of the desi ..

MAX77826EWJ+T
Power Management IC
General Description
The MAX77826 is a subpower management IC for the
latest 3G/4G smartphones and tablets. The MAX77826
contains a high-efficiency BUCK regulator, a BUCK
BOOST regulator and 15 LDOs to power up peripherals.
The MAX77826 also provides power on/off control logic
and an I2C serial interface to program individual regulator
output voltages and on/off control for complete flexibility.
The linear regulators support a remote cap feature and
provide greater than 70dB PSRR and less than 45µVRMS
noise.
The MAX77826 features I2C-compatible, 2-wire serial
interface that comprises a bidirectional serial data line
(SDA) and a serial clock line (SCL). The MAX77826 sup-
ports SCL clock rates up to 3.4MHz.
Applications●GSM, GPRS, EDGE, CDMA WCDMA, and LTE
Smartphones and Tablets
Beneits and Features●Compact Total Solution Size Allows More Peripheral
Devices in Smartphones and Tablets3A High-Eficiency BUCK RegulatorDVS (Dynamic Voltage Scaling) Through HS I2C±1% (typ) Output Voltage DC AccuracyLow Power Mode2A BUCK BOOST Regulator15 Linear Regulators with Remote Cap3 NMOS LDOs (VOUT Range: 0.6V to 2.1875V
with 12.5mV Step)1 x 150mA1 x 450mA1 x 600mA6 PMOSLV LDOs (VOUT Range: 0.8V to 3.975V
with 25mV Step)3 x 150mA3 x 300mA6 PMOSLS LDOs (VOUT Range: 0.8V to 3.975V
with 25mV Step)3 x 150mA3 x 300mA±1.5% Typical Output Voltage DC Accuracy70dB PSRR at 1kHzLow Power Mode with 2µA (typ) for all LDOs●Simple Management of Power-Up/Down Sequence,
Output Voltage Setting, and Fault DetectionHigh-Speed (Up to 3.4MHz) I2C Serial Interface
Ordering Information appears at end of data sheet.
MAX77826Power Management IC
EVALUATION KIT AVAILABLE
SYS, VIO, INL1, INL2, INL3,
INL4, INL5 to GND ...........................................-0.3V to +6.0V
INB to PGNDB......................................................-0.3V to +6.0V
INBB, OUTBB to PGNDBB ..................................-0.3V to +6.0V
PGNDB, PGNDBB to GND ..................................-0.3V to +0.3V
IRQB, CE, SDA, SCL to GND ...................-0.3V to (VIO + 0.3V)
FB_B, ENBB, ENB, ENL12,
REFBYP to GND ................................-0.3V to (VSYS + 0.3V)
FB_BB to PGNDBB ............................-0.3V to (VOUTBB + 0.3V)
LXB to PGNDB ........................................-0.3V to (VINB + 0.3V)
LXBB1 to PGNDBB ...............................-0.3V to (VINBB + 0.3V)
LXBB2 to PGNDBB ............................-0.3V to (VOUTBB + 0.3V)
LDO1, LDO2 to GND .............................-0.3V to (VINL1 + 0.3V)
LDO3 to GND .........................................-0.3V to (VINL2 + 0.3V)
LDO4, LDO5, LDO6, LDO7, LDO8,
LDO9 to GND .....................................-0.3V to (VINL3 + 0.3V)
LDO10, LDO11 to GND ..........................-0.3V to (VINL4 + 0.3V)
LDO12, LDO13, LDO14,
LDO15 to GND ...................................-0.3V to (VINL5 + 0.3V)
LXB Continuous RMS Current (Note 1) ..................................3A
LXBB1/LXBB2 Continuous RMS Current (Note 1) ..............3.3A
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
WLP Junction-to-Ambient Thermal Resistance (θJA) ..........37°C/W
(Note 2)
Note 1: LX_ node has internal clamp diodes to PGND_ and INB_. Applications that give forward bias to these diodes should ensure
that the total power loss does not exceed IC’s package power dissipation limits.
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.)
MAX77826Power Management IC
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Package Thermal Characteristics
General Electrical Characteristics
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Shutdown Supply CurrentISHDN_SYSCE = low2.510µA
Standby CurrentIQ_SYSCE = high and all regulators are off35µA
Shutdown VIO CurrentISHDN_VIOAll regulators are off0µA
No Load Supply Current 1INO_LOAD1BUCK is on in normal mode
(no switching)60µA
No Load Supply Current 2INO_LOAD2BUCK and BUCK BOOST are on in
normal mode (no switching)120µA
No Load Supply Current 3INO_LOAD3All regulators are on in normal
mode (no switching)400700µA
VSYS UNDERVOLTAGE LOCKOUT
VSYS Undervoltage Lockout
Threshold
VUVLO_RVSYS rising2.3752.502.625
VUVLO_FVSYS falling (default)2.05
REFERENCE
REFBYP Output Voltage0.7860.800.814V
REFBYP Supply Rejection2.7V ≤ VSYS ≤ 5.5V0.2mV/V
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.)
MAX77826Power Management IC
General Electrical Characteristics (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
THERMAL SHUTDOWN
Thermal Shutdown ThresholdTSHDNTJ rising, 15°C hysteresis+165°C
Thermal Interrupt at +120°C T120TJ rising, 15°C hysteresis+120°C
Thermal Interrupt at +140°C T140TJ rising, 15°C hysteresis+140°C
LOGIC AND CONTROL INPUTS
Input Low LevelVIL
ENB, ENBB,
ENL12
VSYS ≤ 4.5V
TA = +25°C0.4TA = +25°C0.3 x VIO
Input High LevelVIH
ENB, ENBB,
ENL12
VSYS ≤ 4.5V
TA = 25°C1.2TA = +25°C0.7 x VIO
Logic Input Leakage CurrentILEAKCE
(0V < VIO < 1.8V)
TA = +25°C-1+1µA
TA = +85°C0.1
IRQB Output Low VoltageVOLISINK = 1mA0.4V
IRQB Output High LeakageIOZHVIO = 5.5V
TA = +25°C-1+1
TA = +85°C0.1
INTERNAL PULLDOWN RESISTANCE
ENB, ENBB, ENL12RPDPulldown resistor to GND4008001600kΩ
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
MAX77826Power Management IC2C Electrical Characteristics
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
VIO VoltageVIO1.73.6V
SDA AND SCL I/O STAGES
SCL, SDA Input High VoltageVIH0.7 x VIOV
SCL, SDA Input Low VoltageVIL0.3 x VIOV
SCL, SDA Input HysteresisVHYS0.05 x VIOV
SCL, SDA Input CurrentIIVIO = 3.7V-10+10µA
SDA Output Low VoltageVOLISINK = 20mA0.4V
SCL, SDA Pin CapacitanceCI10pF
Output Fall Time from
VIO to 0.3 x VIOtOF120ns
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST MODE PLUS) (Note 3)
Clock FrequencyfSCL1000kHz
Hold Time (REPEATED) START
ConditiontHD;STA0.26µs
CLK Low PeriodtLOW0.5µs
CLK High PeriodtHIGH0.26µs
Setup Time REPEATED START
ConditiontSU;STA0.26µs
DATA Hold TimetHD:DAT0µs
DATA Setup TimetSU;DAT50ns
Setup Time for STOP ConditiontSU;STO0.26µs
Bus-Free Time Between
STOP and STARTtBUF0.5µs
Capacitive Load for
Each Bus LineCB550pF
Maximum Pulse Width of
Spikes That Must Be
Suppressed by the Input Filterns
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
MAX77826Power Management IC2C Electrical Characteristics (continued)
PARAMETERSYMBOLCONDITIONSCB = 100pFCB = 400pFUNITSMINTYPMAXMINTYPMAX
I2C-COMPATIBLE INTERFACE TIMING (HS MODE)
Clock FrequencyfSCL3.41.7MHz
Set-Up Time REPEATED
START ConditiontSU;STA160160ns
Hold Time (REPEATED)
START ConditiontHD;STA160160ns
CLK Low PeriodtLOW160320ns
CLK High PeriodtHIGH60120ns
DATA Setup timetSU:DAT1010ns
DATA Hold TimetHD:DAT3575ns
SCL Rise Time
(Note 3)tRCLTA = +25°C10402080ns
Rise Time of SCL Signal
After a REPEATED
START Condition and
After an Acknowledge Bit
(Note 3)
trCL1TA = +25°C108020160ns
SCL Fall Time
(Note 3)tfCLTA = +25°C10402080ns
SDA Rise Time
(Note 3)trDATA = +25°C80160ns
SDA Fall Time
(Note 3)tfDATA = +25°C80160ns
Set-Up Time for STOP
ConditiontSU;STO160160ns
Capacitive Load for Each
Bus LineCB100400pF
Maximum Pulse Width
of Spikes That Must Be
Suppressed by the Input
Filter10ns
(VSYS = VINB = +3.7V, VFB_B = VOUT = 1.25V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 4)
MAX77826Power Management IC
BUCK Electrical Characteristics
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage RangeParametric2.65.5V
Shutdown Supply Current
(Note 3)0.1µA
Supply Quiescent Current
(Note 3)
No switching,
No load
Normal mode22
Low power mode8
Output Voltage RangeI2C-programmable 6.25mV step0.51.8V
Output Voltage AccuracyVINB = 2.6V to 4.5V,
VOUT = 1.25V, no load
PWM mode, TA = +25°C-1.0+1.0
Low power mode-3.0+4.0
Line RegulationVINB = 2.6V to 4.5V0.200%/V
Load Regulation (Note 3)VOUT = 1.25V0.125%/A
Transient Load Response,
VDROOP (Note 3)
VOUT = 1.25V, IOUT changes from 0A to 1.5A in 6µs,
COUT_ACTUAL = 22µF, L = 0.47µH-50mV
Soft-Start Slew Rate14mV/µs
Output Voltage Ramp-Up Slew
Rate
RAMP[1:0] = 00b (default)12.5
mV/µs
RAMP[1:0] = 01b25
RAMP[1:0] = 10b50
RAMP[1:0] = 11b100
Maximum Output Current
Normal mode3000
Low power mode10
Peak Current Limit3.304.255.50A
Valley Current Limit3.825A
Negative Current Limit1.000A
N-FET Zero-Crossing
ThresholdSkip mode20mA
Switching Frequency1.822.2MHz
Turn-On Delay TimeEN signal to LX switching with bias ON30µs
HS PMOS RDSONVINB = 3.7V, INB to LX, ILX = 200mA60mΩ
LS NMOS RDSONVINB = 3.7V, LX to PGNDB, ILX = 200mA35mΩ
Output Active Discharge
ResistanceOutput disabled, resistance from FB_B to PGNDB100Ω
LX LeakageVLXB = 5.5V or 0V
TA = +25°C-10.1+1
TA = +85°C1
POWER-OK COMPARATOR
Output POK Trip LevelVOUT POK rising threshold90%
(VINBB = +3.7V, VOUTBB = +3.5V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
BUCK BOOST Electrical Characteristics
PARAMETERCONDITIONSMINTYPMAXUNITS
GENERAL
Operating Input Voltage RangeSupplied from VSYS2.65.5V
Shutdown Supply CurrentVINBB = 5.5V,
VOUTBB = 0V
TA = +25°C0.01
TA = +85°C1
Input Supply CurrentEnabled, no
load
HSKIP mode (no switching)60µA
FPWM mode (switching)9mA
Active Discharge Resistance100Ω
Thermal ShutdownTA rising, 20°C hysteresis+165°C
H-BRIDGE
Maximum Output Current (Note 6)
VINBB = 3.0V, VOUTBB = 3.5V2000
VINBB = 2.6V, VOUTBB = 3.5V1500
Default Output VoltageNo load, BB_VOUT[6:0] = 0x483.5V
Output Voltage AccuracyBB_VOUT[6:0] = 0x48,
no load
PWM mode-1.0+1.0HSKIP mode
TA = +25°C-1.0+4.0
Output Voltage RangeI2C programmable (12.5mV step)2.64.1875V
Line RegulationVINBB = 2.6V to 5.5V0.200%/V
Load Regulation (Note 6)VOUTBB = 3.5V0.125%/A
Transient Load Response, VDROOP
(Note 6)
VINBB = 3.8V, VOUTBB = 3.5V,
IOUT changes from 10mA to 1A in 10µs, COUT_
ACTUAL = 47µF, L = 1µH
-100mV
Output Overvoltage ThresholdWith respect to
VOUTBB
BB_OVP_TH[1:0] = 01b110BB_OVP_TH[1:0] = 10b115
BB_OVP_TH[1:0] = 11b
(default)120
Switching Frequency
2-phase BUCK or BOOST mode1.61.82.0
MHz
3-phase mode0.9
LXBB1, LXBB2 Leakage Current
VLXBB1/2 = 0V or 5.5V,
VOUTBB = 5.5V, VSYS =
VINBB = 5.5V
TA = +25°C0.11
TA = +85°C0.2
LXBB1/2 Current Limit3.54.55.5A
PMOS On-ResistanceILXBB = 100mA, per switch65mΩ
NMOS On-ResistanceILXBB = 100mA, per switch55mΩ
(VINBB = +3.7V, VOUTBB = +3.5V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 5)
Note: LDO12 can also be enabled/disabled by external logic inputs, ENL12.
MAX77826Power Management IC
BUCK BOOST Electrical Characteristics (continued)
PARAMETERCONDITIONSMINTYPMAXUNITS
Minimum Effective Output
Capacitance0µA < IOUT < 2000mA16µF
Turn-On Delay TimeFrom ENBB asserting to LXBB Switching with bias on6µs
Soft-Start TimeVOUTBB = 3.5V, IOUT = 10mA40µs
POWER-OK COMPARATOR
Output POK Trip LevelVOUTBB POK rising threshold80%
Output POK HysteresisVOUT when VPOK switches5%
LDO Electrical Characteristics
LDO NO.TYPEVOUT RANGE (V)STEP SIZE
(mV)IOUT(max, mA)DEFAULT
VOUT (V)DEFAULT ON/OFFINPUT PINCOUT (µF)NMOS0.6–2.187512.56001.0OffINL14.7NMOS0.6–2.187512.51501.0OffINL11NMOS0.6–2.187512.54501.0OffINL24.7PMOSLV0.8–3.975253001.5OffINL34.7PMOSLV0.8–3.975253001.8OffINL34.7PMOSLV0.8–3.975251501.8OffINL32.2PMOSLV0.8–3.975253001.8OffINL34.7PMOSLV0.8–3.975251501.8OffINL32.2PMOSLV0.8–3.975251501.8OffINL32.2PMOSLS0.8–3.975253002.8OffINL42.2PMOSLS0.8–3.975251502.8OffINL42.2PMOSLS0.8–3.975253003.3OffINL52.2PMOSLS0.8–3.975253003.3OffINL52.2PMOSLS0.8–3.975251503.3OffINL52.2PMOSLS0.8–3.975251503.3OffINL52.2
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO1 (600mA NMOS)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage Range
VINLx must be lower than or equal to VSYSVOUTVSYSVSYS2.65.5
(Note 7)1.5
Input Supply Current
Normal mode, no load2Low power mode, no load2
Shutdown< 0.1
System Supply Current
Normal mode, no load30Low power mode, no load4
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.6Maximum VOUT, Lx_VOUT[6:0] = 7’h7F2.1875
Least signiicant step size0.0125
Output Voltage Accuracy
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
VINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA-5+5
Maximum Output Current
(Note 8)
Normal mode600mA
Low power mode5
Load RegulationVSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V)
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line Regulation
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
IOUT = 0.1mA
Normal mode0.05
%/V
Low power mode0.05
Dropout VoltageNormal mode, IOUT = IMAX,
VDO = VINLx - VOUT
VSYS - VOUT = 2.5V60150
VSYS - VOUT = 1.5V100
Output Current LimitVOUT = 90% of
VOUT(TARGET)
Normal mode9001800mA
Low power mode10
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH (Note 9)2.354.7µF
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
PARAMETERCONDITIONSMINTYPMAXUNITS
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = 2.7V,
VINLx = 1.2V,
VOUT = VOUTMIN
µVRMSVSYS = 2.7V,
VINLx = 1.8V,
VOUT = 1.0V
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode, VSYS = 3.7V,
VINLx = 1.8V, VOUT = 1.0V,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 4.7µF±5
COUT = 10µF±3
Output Line Transient
Normal mode, VOUT = 1.0V,
IOUT = 1mA, tRISE = tFALL
= 5µs
VSYS = VINLx = 3.7V to
3.2V to 3.7V5
VSYS = 3.7V, VINLx =
1.8V to 1.5V to 1.8V5
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled.5µs
Output Overshoot during Startup
Overshoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising165
TJ falling150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches5%
LDO1 (600mA NMOS) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 1.0µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO2 (150mA NMOS)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage Range
VINLx must be lower than or equal to VSYSVOUTVSYSVSYS2.65.5
(Note 7)1.5
Input Supply Current
Normal mode, no load2Low power mode, no load2
Shutdown< 0.1
System Supply Current
Normal mode, no load25Low power mode, no load3
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.6Maximum VOUT, Lx_VOUT[6:0] = 7’h7F2.1875
Least signiicant step size0.0125
Output Voltage Accuracy
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
VINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA-5+5
Maximum Output Current
(Note 8)
Normal mode150mA
Low power mode5
Load RegulationVSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V)
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line Regulation
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
IOUT = 0.1mA
Normal mode0.05
%/V
Low power mode0.05
Dropout Voltage
Normal mode,
IOUT = IMAX,
VDO = VINLx - VOUT
VSYS - VOUT = 2.5V60150
VSYS - VOUT = 1.5V100
Output Current LimitVOUT = 90% of VOUT
(TARGET)
Normal mode225450
Low power mode10
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH (Note 9)0.51.0µF
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 1.0µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
PARAMETERCONDITIONSMINTYPMAXUNITS
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = 2.7V,
VINLx = 1.2V,
VOUT = VOUTMIN
µVRMSVSYS = 2.7V,
VINLx = 1.8V,
VOUT = 1.0V
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode, VSYS = 3.7V,
VINLx = 1.8V, VOUT = 1.0V,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 1.0µF±5
COUT = 10µF±3
Output Line Transient
Normal mode, VOUT = 1.0V,
IOUT = 1mA, tRISE = tFALL
= 5µs
VSYS = VINLx = 3.7V to
3.2V to 3.7V5
VSYS = 3.7V, VINLx = 1.8V
to 1.5V to 1.8V5
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled.5µs
Output Overshoot During
Startup Overshoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising165
TJ falling150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches5%
LDO2 (150mA NMOS) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO3 (450mA NMOS)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage Range
VINLx must be lower than or equal to VSYSVOUTVSYSVSYS2.65.5
(Note 7)1.5
Input Supply Current
Normal mode, no load2Low power mode, no load2
Shutdown< 0.1
System Supply Current
Normal mode, no load25Low power mode, no load3
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.6Maximum VOUT, Lx_VOUT[6:0] = 7’h7F2.1875
Least signiicant step size0.0125
Output Voltage Accuracy
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
VINLx = VOUT + 0.3V to VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA-5+5
Maximum Output Current
(Note 8)
Normal mode450mA
Low power mode5
Load RegulationVSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V)
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line Regulation
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
IOUT = 0.1mA
Normal mode0.05
%/V
Low power mode0.05
Dropout VoltageNormal Mode, IOUT = IMAX,
VDO = VINLx - VOUT
VSYS - VOUT = 2.5V60150
VSYS - VOUT = 1.5V100
Output Current LimitVOUT = 90% of VOUT
(TARGET)
Normal mode6751350
Low power mode10
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH
(Note 9)2.354.7µF
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 1.0µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO3 (450mA NMOS) (continued)
PARAMETERCONDITIONSMINTYPMAXUNITS
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = 2.7V,
VINLx = 1.2V,
VOUT = VOUTMIN
µVRMSVSYS = 2.7V,
VINLx = 1.8V,
VOUT = 1.0V
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power-Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode, VSYS = 3.7V,
VINLx = 1.8V, VOUT = 1.2V,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 4.7µF±5
COUT = 10µF±3
Output Line Transient
Normal mode, VOUT
= 1.2V, IOUT = 1mA,
tRISE = tFALL = 5µs
VSYS = VINLx = 3.7V to 3.2V to
3.7V5
VSYS = 3.7V, VINLx = 1.8V to 1.5V
to 1.8V5
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled5µs
Output Overshoot during Startup
Overshoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising165
TJ falling150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches5%
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO4, LDO5 and LDO7 (300mA PMOSLV)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage RangeVINLx must be lower than or equal to VSYS1.7VSYSV
Input Supply Current
Normal mode, no load15Low power mode, no load1.5
Shutdown< 0.1
System Supply Current
Normal mode, no load3Low power mode, no load0.3
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.8Maximum VOUT, Lx_VOUT[6:0] = 7’h7F3.975
Least signiicant step size0.025
Output Voltage AccuracyVINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA-5+5
Maximum Output Current
(Note 8)
Normal mode300
Low power mode5
Load RegulationVINLx = VOUT + 0.3V
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line RegulationVINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Normal mode0.05
%/V
Low power mode0.05
Dropout Voltage
Normal mode,
VSYS = 3.7V,
IOUT = IMAX,
VDO = VINLx - VOUT
VINLx = 3.7V60150
VINLx = 1.7V100
Output Current LimitVOUT = 90% of
VOUT(TARGET)
Normal mode6001120Low power mode40
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH
(Note 9)2.354.7µF
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
PARAMETERCONDITIONSMINTYPMAXUNIT
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN25
µVRMS
VSYS = VINLx = 2.7V,
VOUT = 1.0V30
VSYS = VINLx = 2.7V,
VOUT = 2.0V40
VSYS = VINLx = 3.7V,
VOUT = 3.0V60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default,
IOUT = 1mA to ½ x IMAX
to 1mA,
tRISE = tFALL = 1µs
COUT = 4.7µF±5
COUT = 10µF±3
Output Line Transient
Normal mode,
VOUT = 1.2V,
IOUT = 1mA,
tRISE = tFALL = 5µs
VSYS = VINLx = 3.7V to 3.2V
to 3.7V5
VSYS = 3.7V,
VINLx = 2.0V to 1.7V to 2.0V5
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled5µs
Output Over-shoot during
Startup Over-shoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising+165TJ falling+150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches3%
LDO4, LDO5 and LDO7 (300mA PMOSLV) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO6, LDO8, and LDO9 (150mA PMOSLV)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage RangeVINLx must be lower than or equal to VSYS1.7VSYSV
Input Supply Current
Normal mode, no load15Low power mode, no load1.5
Shutdown< 0.1
System Supply Current
Normal mode, no load3Low power mode, no load0.3
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.8Maximum VOUT, Lx_VOUT[6:0] = 7’h7F3.975
Least signiicant step size0.025
Output Voltage AccuracyVINLx = VOUT + 0.3V
to VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA,-5+5
Maximum Output Current
(Note 8)
Normal mode150
Low power mode5
Load RegulationVINLx = VOUT + 0.3V
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line RegulationVINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Normal mode0.05
%/V
Low power mode0.05
Dropout Voltage
Normal mode, VSYS = 3.7V,
IOUT = IMAX,
VDO = VINLx - VOUT
VINLx = 3.7V60150
VINLx = 1.7V100
Output Current LimitVOUT = 90% of
VOUT(TARGET)
Normal mode300560
Low power mode40
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH
(Note 9)1.12.2µF
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO6, LDO8, and LDO9 (150mA PMOSLV) (continued)
PARAMETERCONDITIONSMINTYPMAXUNITS
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN25
µVRMS
VSYS = VINLx = 2.7V,
VOUT = 1.0V30
VSYS = VINLx = 2.7V,
VOUT = 2.0V40
VSYS = VINLx = 3.7V,
VOUT = 3.0V60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 2.2µF±5
COUT = 10µF±3
Output Line Transient
Normal mode, VOUT = 1.2V,
IOUT = 1mA,
tRISE = tFALL = 5µs
VSYS = VINLx = 3.7V to
3.2V to 3.7V5
VSYS = 3.7V, VINLx =
2.0V to 1.7V to 2.0V5
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled5µs
Output Overshoot During
Startup Overshoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising+165
TJ falling+150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches3%
(VSYS = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO11, LDO14 and LDO15 (150mA PMOSLS)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage Range
VINLx2.65.5VSYS2.65.5
Input Supply Current
Normal mode, no load15Low power mode, no load4
Shutdown< 0.1
System Supply Current
Normal mode, no load3.25Low power mode, no load0.85
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.8Maximum VOUT, Lx_VOUT[6:0] = 7’h7F3.975
Least signiicant step size0.025
Output Voltage AccuracyVINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA-5+5
Maximum Output Current
(Note 8)
Normal mode150
Low power mode5
Load RegulationVINLx = VOUT + 0.3V
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line RegulationVINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Normal mode0.05
%/VLow power mode0.05
Dropout VoltageNormal mode, VSYS = VINLx = 3.7V,
IOUT = IMAX, VDO = VINLx - VOUT100200mV
Output Current LimitVOUT = 90% of
VOUT(TARGET)
Normal mode300560
Low power mode40
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH (Note 9)0.62.2µF
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO11, LDO14 and LDO15 (150mA PMOSLS) (continued)
PARAMETERCONDITIONSMINTYPMAXUNITS
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN25
µVRMS
VSYS = VINLx = 2.7V,
VOUT = 1.0V30
VSYS = VINLx = 2.7V,
VOUT = 2.0V40
VSYS = VINLx = 3.7V,
VOUT = 3.0V60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default, IOUT =
1mA to ½ x IMAX to 1mA,
tRISE = tFALL = 1µs
COUT = 2.2µF±5
COUT = 10µF±3
Output Line TransientNormal mode, VINLx = 3.7V to 3.2V to 3.7V,
VOUT = default, IOUT = 1mA, tRISE = tFALL = 5µs5mV
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled5µs
Output Overshoot During
Startup Overshoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising165TJ falling150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches3%
(VSYS = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
MAX77826Power Management IC
LDO10, LDO12 and LDO13 (300mA PMOSLS)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Voltage Range
VINLx2.65.5VSYS2.65.5
Input Supply Current
Normal mode, no load15Low power mode, no load4
Shutdown< 0.1
System Supply Current
Normal mode, no load3.25Low power mode, no load0.85
Shutdown< 0.1
Output Voltage Programming
Minimum VOUT, Lx_VOUT[6:0] = 7’h000.8Maximum VOUT, Lx_VOUT[6:0] = 7’h7F3.975
Least signiicant step size0.025
Output Voltage AccuracyVINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX-2+2
Low power mode
IOUT = 0.1mA to 5mA-5+5
Maximum Output Current
(Note 8)
Normal mode300
Low power mode5
Load RegulationVINLx = VOUT + 0.3V
Normal mode
IOUT = 0.1mA to IMAX0.5
Low power mode
IOUT = 0.1mA to 5mA0.5
Line RegulationVINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Normal mode0.05
%/V
Low power mode0.05
Dropout VoltageNormal mode, VSYS = VINLx = 3.7V,
IOUT = IMAX, VDO = VINLx - VOUT100200mV
Output Current LimitVOUT = 90% of
VOUT(TARGET)
Normal mode6001120
Low power mode40
Output Capacitance for StabilityDCR < 200mΩ, ESL < 20nH (Note 9)0.62.2µF
(VSYS = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
Note 3: Guaranteed by design. Not production tested.
Note 4: 100% production tested at TA = +25°C, limits over the operating range are guaranteed by design.Note 5: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through
correlation using statistical quality control methods.Note 6: The maximum output current spec is not directly tested. Instead, it is guaranteed by LX NMOS current limit test.Note 7: For NMOS LDOs, VSYS must be at least 1.5V above VOUT (VSYS ≥ VOUT + 1.5V).Note 8: The maximum output current is guaranteed by the output voltage accuracy tests.Note 9: For stability, guaranteed by design and not production tested.
Note 10: There is an n-channel MOSFET in series with the output active discharge resistance. This NMOS requires VSYS > 1.2V to
MAX77826Power Management IC
LDO10, LDO12 and LDO13 (300mA PMOSLS) (continued)
PARAMETERCONDITIONSMINTYPMAXUNITS
Output Noise
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN25
µVRMS
VSYS = VINLx = 2.7V,
VOUT = 1.0V30
VSYS = VINLx = 2.7V,
VOUT = 2.0V40
VSYS = VINLx = 3.7V,
VOUT = 3.0V60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX60
Power Supply RejectionNormal mode, f = 1kHz, IOUT = 30mA70dB
Output Load Transient (ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default, IOUT =
1mA to ½ x IMAX to 1mA,
tRISE = tFALL = 1µs
COUT = 2.2µF±5
COUT = 10µF±3
Output Line TransientNormal mode, VINLx = 3.7V to 3.2V to 3.7V, VOUT =
default, IOUT = 1mA, tRISE = tFALL = 5µs5mV
Output Startup Ramp Rate10% to 90%30mV/µs
Turn-On Delay TimeFrom Lx_EN = 1 (or ENL12 = high) to output rising,
REFBYP enabled > 300µs prior to LDO being enabled5µs
Output Overshoot During
Startup Overshoot50mV
Output Active Discharge
Resistance(Note 10)100Ω
Thermal Shutdown
TJ rising+165
TJ falling+150
POWER-OK COMPARATOR
Output POK Trip LevelRising edge, VOUT when VPOK switches87.5%
Output POK HysteresisVOUT when VPOK switches3%
MAX77826Power Management IC
Pin Conigurations
Pin Description
SCLSDA
SYS
IRQB
LDO12
VIO
LDO7LDO6
INL3
LDO5
LDO3
ENBB
LDO10
LDO14
INL4
LDO11
LDO13
INL5
LDO9
PGNDBPGNDB
LDO4
FB_BLXBLXB
ENB
INL1LDO8
LDO1
LDO15
INBINB
INL2
LDO2
INBBOUTBBLXBB1PGNDBB
INBBLXBB1PGNDBB
LXBB2
ENL12
REFBYP
OUTBBLXBB2
FB_BB234567
GND
MAX77826
PINNAMEFUNCTIONCE
Active-High Chip Enable Input. When CE = high (standby), the I2C interface is enabled
and regulators are ready to be turned on. When CE = low (shutdown), all regulators
are turned off and all Type-O registers are reset to their POR default values.ENBActive-High BUCK External Enable Input. An 800kΩ internal pull-down resistance to the GND. If this pin is not used, leave it loating.ENBBActive-High BUCK BOOST External Enable Input. An 800kΩ internal pulldown
resistance to the GND. If this pin is not used, leave it unconnected.ENL12Active-High LDO12 External Enable Input. An 800kΩ internal pulldown resistance to
the GND. If this pin is not used, leave it unconnected.FB_BBUCK Output Voltage FeedbackFB_BBBUCK BOOST Output Voltage FeedbackGNDGround
A1, A2INBBUCK Input. Bypass to PGNDB with a 10µF capacitor.
F7, G7INBBBUCK BOOST Input
MAX77826Power Management IC
Pin Description (continued)
PINNAMEFUNCTIONINL1Input for LDO1 and 2. Bypass to GND with a 4.7µF capacitor.INL2Input for LDO3. Bypass to GND with a 1µF capacitor.INL3Input for LDO4, 5, 6, 7, 8, and 9. Bypass to GND with a 4.7µF capacitor.INL4Input for LDO10 and 11. Bypass to GND with a 4.7µF capacitor.INL5Input for LDO12, 13, 14, and 15. Bypass to GND with a 4.7µF capacitor.IRQBInterrupt Output. A 100kΩ external pullup resistor to VIO is required.
B1, B2LXBBUCK Switching Node
F6, G6LXBB1BUCK BOOST Switching Node 1
F4, G4LXBB2BUCK BOOST Switching Node 2LDO1LDO1 (600mA NMOS) Output. Bypass to GND with a 4.7µF capacitor.LDO2LDO2 (150mA NMOS) Output. Bypass to GND with a 1µF capacitor.LDO3LDO3 (450mA NMOS) Output. Bypass to GND with a 4.7µF capacitor.LDO4LDO4 (300mA PMOSLV) Output. Bypass to GND with a 4.7µF capacitor.LDO5LDO5 (300mA PMOSLV) Output. Bypass to GND with a 4.7µF capacitor.LDO6LDO6 (150mA PMOSLV) Output. Bypass to GND with a 2.2µF capacitor.LDO7LDO7 (300mA PMOSLV) Output. Bypass to GND with a 4.7µF capacitor.LDO8LDO8 (150mA PMOSLV) Output. Bypass to GND with a 2.2µF capacitor.LDO9LDO9 (150mA PMOSLV) Output. Bypass to GND with a 2.2µF capacitor.LDO10LDO10 (300mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.LDO11LDO11 (150mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.LDO12LDO12 (300mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.LDO13LDO13 (300mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.LDO14LDO14 (150mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.LDO15LDO15 (150mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
F3, G3OUTBBBUCK BOOST Output
C1, C2PGNDBBUCK Power GND
F5, G5PGNDBBBUCK BOOST Power GNDREFBYPLDO Reference Bypass Node. Connect a 0.1µF Cap to GND.SCLI2C Clock Input. High Impedance in Off State.A 1.5kΩ~2.2kΩ of pullup resistor to VIO is required.SDAI2C Data I/O. High Impedance in Off State. A 1.5kΩ–2.2kΩ of pullup resistor to VIO is
required.SYSSystem (Battery) Voltage Input. Bypass to GND with a 1µF capacitor.VIOIO Supply Voltage Input. Bypass to GND with a 0.1µF capacitor.
MAX77826Power Management IC
Block Diagram
SYS
BUCK
FB_B
LXB
PGNDB
INB
ENBB
ON/OFF CONTROL
AND2C INTERFACE
BUCK-BOOST
LXBB1
PGNDBB
INBB
SBIAS, REF, UVLO,
TSHDN
800kΩ
VIOVIO
IRQB
SCL
SDA
INL1
LDO1
(N600)
LDO2
(N150)
LDO1
LDO2
ENL12
800kΩ
MAX77826
LXBB2
INL2
LDO3
(N450)
LDO3
INL3
LDO4
(P300LV)
LDO4
LDO5
(P300LV)
LDO6
(P150LV)
LDO5
LDO6
LDO7
(P300LV)
LDO7
LDO8
(P150LV)
LDO9
(P150LV)
LDO8
LDO9
INL4
LDO11
(P150LS)
LDO11
LDO10
(P300LS)
LDO10
INL5
LDO13
(P300LS)
LDO13
LDO14
(P150LS)
LDO15
(P150LS)
LDO14
LDO15
FB_BB
LDO12
(P300LS)
LDO12
800kΩ
ENB
REFBYP
GND
OUTBB
Detailed Description
Top System Management
System Faults
The MAX77826 monitors the system for the following
faults: global thermal, local thermal shutdown, and under-
voltage lockout.
Global Thermal Fault
The MAX77826 has a centralized thermal protection
circuit which monitors temperature on the die. If the die
temperature exceeds +165°C (TSHDN), a thermal shut-
down event initiates, and the MAX77826 enters its global
shutdown state.
In addition to the +165°C threshold, there are two addi-
tional comparators that trip at +120°C and +140°C.
Interrupts are generated in the event the die temperature
reaches +120°C or +140°C.
There is a 15°C thermal hysteresis. After the thermal shut-
down, if the die temperature reduces by 15°C, the thermal
shutdown bus deasserts.
Local Thermal Shutdown
If any of the BUCK BOOST or LDOs reach the thermal
shutdown threshold, the MAX77826 shuts down the cor-
responding block locally. If the temperature goes below a
threshold, that block goes back to normal operation.
Undervoltage Lockout
When VSYS falls below VUVLO_F (typ 2.05V), the
MAX77826 enters its undervoltage lockout (UVLO) mode.
UVLO forces the MAX77826 to a dormant state until the
source voltage is high enough to allow the MAX77826
to be securely functional. I2C does not function and the
Type-O register contents are reset to their default values
in UVLO mode. UVLO rising threshold is set to 2.5V by
an OTP option.
Chip Enable (CE)
A logic-high on CE pin puts the MAX77826 into standby
mode (enabled). In standby mode, all user registers are
accessible through I2C so that the host processor can
overwrite the default output voltages of regulators and
each regulator can be enabled by either I2C or the GPIO
input if applicable.
When the CE pin goes high, the MAX77826 turns on the
top-level bias circuitry, and it takes typically 85µs to settle.
As soon as the top-level bias is ready, BUCK BOOST is
ready to be turned on. However, BUCK and LDOs require
additional 85µs (typ) for REFBYP to settle. Total, it takes
170µs (85µs + 85µs) for REFBYP to settle from CE =
high. In the worst-case scenario, it can take up to 230µs.
Once REFBYP is ready, all the regulators are allowed
to be tuned on through I2C or the ENx pins. In case the
regulars are enabled before the bias circuitry is ready, the
regulators require longer time to startup.
When CE pin is pulled low, the MAX77826 goes into
shutdown mode (disabled) and turns off all the regulators
regardless of ENx pins. This event also resets all Type-O
registers to their POR default values.
Immediate Shutdown Events
The following events initiate immediate shutdown: ther-
mal protection (TJ > +165°C), VSYS < VSYS UVLO
falling threshold (VUVLO_F), VIO < VIO OK threshold
(VTH_VIO_OK)
The events in this category are associated with potentially
hazardous system states. Powering down the host pro-
cessor and resetting all Type-O registers help mitigate any
issues that can occur due to these potentially hazardous
conditions. Note that the MAX77826 cannot be enabled
until the junction temperature drops below +150°C in case
thermal protection caused the immediate shutdown.
Operating Mode (OPMD)
Each regulator (BUCK, BUCK BOOST, and LDO) has
independent register bits to control its operating mode.
These bits determines on/off operation during initial
startup, output enable control, and sleep mode operation
based on the enable control logic of each regulator. The
POR default values of output enable bits (x_EN) are 0
(output off).
MAX77826Power Management IC
Enable Control Logic1
BUCK, BUCK BOOST, and LDO12 have independent
I2C enable bits and dedicated GPIO enable pins (ENB,
ENBB, and ENL12). As shown in Table 1, regulators can
be turned on/off by ENx or I2C control bits.
Enable Control Logic 2
LDO1–LDO11 and LDO13–LDO15 have independent I2C
enable bits. As shown in Table 2, regulators can be turned
on/off by the I2C control bits.
Reset Conditions
System Reset
When VSYS voltage drops below its POR threshold (≈1.55V), all Type-S1 registers are reset to their POR
default values.
Off Reset
Off reset occurs by any power-off events. This condition
resets all Type-O registers to their POR default values.
Interrupt and Mask
IRQB pin is used to indicate to the host processor that
the status on the MAX77826 has changed. IRQB signal is
asserted whenever one or more interrupts are triggered.
The host processor reads the interrupt source register
(ADDR 0x00) and the interrupt registers as indicated by
the interrupt source register in order to see the cause of
interrupt event.
Each interrupt register can be read at a time. IRQB pin
goes high (cleared) as soon as the read sequence finish-
es. If an interrupt is captured during the read sequence,
IRQB pin is held low. Note that the interrupt source regis-
ter is cleared when the corresponding interrupt registers
are read by the host processor.
Each interrupt can be masked (disabled) by setting the
corresponding interrupt mask register bit. In case an inter-
rupt mask bit is set (masked), the corresponding interrupt
bit is not supposed to be set even when the interrupt con-
dition is met. As a result, the IRQB pin stays high for this
event. If the mask bit is cleared for an active interrupt, the
corresponding interrupt bit is set to pull the IRQB pin low.
Figure 1. Enable Control Logic 1
*The BUCK BOOST regulator does not have a low power
mode.
Table 1. Enable Control Logic 1 Truth Table
Table 2. Enable Control Logic 2 Truth Table
MAX77826Power Management IC
BUCK,
BUCK BOOST,
LDO12
LOGIC 1
LOGIC 1: OPERATING
MODE CONTROL
B_EN (I2C)
B_LPM (I2C)
ENx
LPM
BB_EN (I2C)
L12_EN (I2C)
L12_LPM (I2C)
LDO1– LDO11,
LDO13–LDO15
LOGIC 2
LOGIC 2: OPERATING
MODE CONTROL
Lx_EN (I2C)
Lx_LPM (I2C)LPMENx
B_EN
BB_ENL12_EN
B_LPML12_LPMOPERATING MODE
LowxxxDevice off
HighLow0xOutput off
HighHighx1Output on (low
power mode*)
HighHighx0Output on
Highx11Output on (low
power mode*)
Highx10Output onLx_ENLx_LPMOPERATING MODE
LowxxDevice off
High0xOutput off
High11Output on
(low power mode)
BUCK Regulator
The MAX77826 includes a 3A current-mode BUCK regu-
lator. In normal operation, BUCK consumes only 22µA
quiescent current. In low power mode, the quiescent
current is decreased to 8µA with reduced load capability.
The summary of features is:●3A of maximum output current rating●2.6V to 5.5V input voltage range●Output voltage range from 0.50V to 1.80V in 6.25mV
steps●±1% (typ) output voltage DC accuracy●2MHz (typ) switching frequency●Automatic SKIP/PWM or forced PWM modes●> 90% peak efficiency●Programmable slew rate for increasing output voltage
settings
Operating Mode Control
The operating mode bit resides in the top level that con-
trols the enable/disable state of BUCK through the B_EN
register and also controls the operating mode (low power
or normal mode) through the B_LPM register.
SKIP/Forced PWM Operation
In normal operating mode, BUCK automatically transitions
from SKIP mode to fixed frequency operation as load cur-
rent increases. For operating modes where lowest output
ripple is required, forced PWM switching behavior can be
enabled by writing 1 to B_FPWM bit.
Low Power Mode Operation
In low power mode, the quiescent current is reduced from
22µA to 8µA. The output current is limited to 10mA. It
is not recommended to adjust the output voltage in low
power mode. The regulator does not automatically enter/
exit low power mode. The host processor needs to control
low power mode operation in times of known low power
states through the I2C serial interface.
Startup and Soft-Start
When starting up BUCK regulator, the bias circuitry must
be enabled and provided with adequate time to settle. The
bias circuitry is guaranteed to settle within 250µs, at which
time, the BUCK regulators’ power-up sequences can
commence. Note that attempting to implement a power-
up sequence before BIASOK signal is generated results
in all enabled regulators starting up at the same time.
The BUCK regulator supports starting into a prebiased
output. For example, if the output capacitor has an ini-
tial voltage of 0.4V when the regulator is enabled, the
regulator gradually increases the capacitor voltage to the
required target voltage such as 1.0V. This is unlike other
regulators without the start into prebias feature in which
they can force the output capacitor voltage to 0V before
the soft-start ramp begins.
The BUCK regulator has a soft-start rate of 14mV/µs. The
controlled soft-start rate and BUCK regulator current limit
(ILIMP) limit the input inrush current to the output capaci-
tor (IINRUSH). IINRUSH = min (ILIMP and COUT x dv/dt).
Note that the input current of BUCK regulator is lower
than the inrush current to the output capacitor by the ratio
of output to input voltage.
Output Voltage Setting
The output voltage is programmable from 0.50V to 1.80V
in 6.25mV steps to allow fine adjustment to the processor
supply voltage under light load conditions to minimize
power loss within the processor. The default output volt-
age is set by an OTP option at the factory. The default out-
put voltage can be overwritten by changing the contents
in B_VOUT[7:0] register prior to enabling the regulator.
The output voltage can also be adjusted during normal
operation.
Changing Output Voltage While Operating
In a typical smartphone or tablet application, there are
several power domains in which the operating frequency
of the processor increases or decreases (DVFS). When
the operating frequency needs to be changed, it is
expected that BUCK regulator responds to a command to
change the output voltages to new target values quickly.
The high peak current limit, coupled with low inductance
and small output capacitance, allows the BUCK regulator
to respond to a positive step change in output voltage and
settle to the new target value quickly. The BUCK regulator
provides programmable ramp-up slew rates to accommo-
date different requirements.
For a negative step change in output voltage, the settling
time is not critical. In forced PWM mode (either B_FPWM
bit or B_FSRAD bit is enabled), the negative inductor
current through NMOS discharges energy from the out-
put capacitor to help the output voltage decrease to the
new target value faster. In skip mode, negative inductor
current is not allowed so that the output voltage settling
time is dependent on the load current and the output
capacitance.
MAX77826Power Management IC
Output Voltage Slew Rate Control
The BUCK regulator supports programmable slew rate
control feature when increasing and decreasing the output
voltage. The ramp-up slew rate can be set to 12.5mV/µs,
25mV/µs, 50mV/µs or 100mV/µs independently through
the B_RAMP[1:0] bits, while the ramp-down slew rate is
fixed to 6.25mV/µs.
Output Active Discharge Resistance
BUCK provides an internal 100Ω resistor for output active
discharge function. If the active discharge function is
enabled (B_AD = 1), the internal resistor discharges the
energy stored in the output capacitor to GND whenever
the regulator is disabled.
Either the regulator remains enabled or the active dis-
charge function is disabled (B_AD = 0), the internal resis-
tor is disconnected from the output. If the active discharge
function is disabled, the output voltage decays at a rate
that is determined by the output capacitance and the load
current when the regulator is turned off.
Inductor Selection
BUCK is optimized for a 0.47µH inductor. The lower the
inductor DCR, the higher BUCK efficiency is. Users need
to trade off inductor size with DCR value and choose a
suitable inductor for BUCK.
Input Capacitor Selection
The input capacitor, CIN, reduces the current peaks
drawn from the battery or input power source and reduces
switching noise in the IC. The impedance of CIN at the
switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R dielectrics are highly rec-
ommended due to their small size, low ESR, and small
temperature coefficients. For most applications, a 10µF
capacitor is sufficient.
Output Capacitor Selection
The output capacitor, COUT, is required to keep the out-
put voltage ripple small and to ensure regulation loop
stability. COUT must have low impedance at the switching
frequency. Ceramic capacitors with X5R or X7R dielectric
are highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the unique
feedback network, the output capacitance can be very
low. The recommended minimum output capacitance for
BUCK is 22µF.
BUCK BOOST Regulator
The MAX77826 BUCK BOOST regulator utilizes a four-
switch H-bridge configuration to realize BUCK, BUCK
BOOST, and BOOST operating modes. In this way, this
topology maintains output voltage regulation when the
input voltage is greater than, equal to, or less than the
output voltage. The MAX77826 BUCK BOOST is ideal
in Li-ion battery powered applications, providing 2.6V
to 4.1875V output voltage and up to 2A output current
across the input voltage range. High switching frequency
and a unique control algorithm allow the smallest solution
size, low output noise, and highest efficiency across a
wide input voltage and output current range.
The MAX77826 BUCK BOOST regulator typically gener-
ates a 3.50V output voltage. The input current limit is set
to 3.5A (typ) to guarantee delivery of 2A at 3.50V from
3.0V input. Internal soft-start limits the inrush current at
startup.
Table 3. Suggested Inductors for BUCK
MAX77826Power Management IC
MANUFACTURERSERIESNOMINAL INDUCTANCE
(µH)
DC RESISTANCE (typ, mΩ)
CURRENT RATING (A) -30% (∆L/L)
CURRENT RATING (A) ∆T = +40°C RISE
DIMENSIONSL x W x H
(mm)
SemcoCIGT201610G
MR47MNE0.47354.02.92.0 x 1.6 x 1.0
TokoDFE201610-H
-R47N0.47373.53.52.0 x 1.6 x 1.0
H-Bridge Controller
The H-bridge architecture operates at 3MHz fixed fre-
quency with a pulse width modulated (PWM), current
mode control scheme. This topology is in a cascade of
a BOOST regulator and a BUCK regulator using a single
inductor and output capacitor. BUCK, BUCK BOOST,
and BOOST stages are 100% synchronous for highest
efficiency in portable applications.
There are three phases implemented with the H-bridge
switch topology, as shown in Figure 4:
Φ1 switch period (Phase 1: P1 = on, N2 = on) stores
energy in the inductor, ramping up the inductor current at
a rate proportional to the input voltage divided by induct-
ance; VINBB/L.
Φ2 switch period (Phase 2: P1 = on, N3 = on) ramps the
inductor current up or down, depending on the differen-
tial voltage across the inductor, divided by inductance;
±(VINBB - VOUTBB)/L.
Φ3 switch period (Phase 3: N1 = on, N3 = on) ramps
down the inductor current at a rate proportional to the
Figure 3. BUCK BOOST Block Diagram
Figure 4. BUCK BOOST Switching Intervals
MAX77826Power Management IC
OSCSHUT-
DOWN
VOUTBB
PGNDBB
LXBB2LXBB1
BUFFER
SNSBB
P1 CSP2 CS
VINBB
DRIVERDRIVER
CONTROL LOGIC
REF
LXBB
1µH
2x 22µF
10µF
REGISTER
CONTROL
Ф1
Ф2
VINBBLXBB1
CHARGE LDISCHARGE L
CHARGE/
DISCHARGE L
VOUTBB
LXBB2
2-Phase BUCK topology is utilized when VINBB > VOUTBB.
A switching cycle is completed in one clock periods. Switch period Φ2 is followed by switch period Φ3, result-
ing in an inductor current waveform similar to Figure 5.
3-Phase BUCK topology is utilized when VINBB > VOUTBB
and 2-Phase BUCK cannot support VO. Switch period is: Φ1  Φ2  Φ3. Switch period Φ1 is fixed. This results in
an inductor current waveform similar to Figure 6.
2-Phase BOOST topology is utilized when VINBB <
VOUTBB. A switching cycle is completed in one clock periods. Switch period Φ1 is followed by switch period Φ2, resulting in an inductor current waveform similar to
Figure 7.
3-Phase BOOST topology is utilized when VINBB <
VOUTBB and 2-Phase BOOST cannot support VO. Switch period is: Φ1  Φ2  Φ3. Switch period Φ3 is fixed. This
results in an inductor current waveform similar to Figure 8.
Inductor Selection
BUCK BOOST is optimized for a 1µH inductor. The lower
the inductor DCR, the higher BUCK BOOST efficiency is.
Users need to trade off inductor size with DCR value and
choose a suitable inductor for BUCK BOOST.
The input capacitor, CIN, reduces the current peaks
drawn from the battery or input power source and reduces
switching noise in the IC. The impedance of CIN at the
switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R dielectrics are highly rec-
ommended due to their small size, low ESR, and small
temperature coefficients. For most applications, a 10µF
capacitor is sufficient.
Output Capacitor Selection
The output capacitor, COUT, is required to keep the out-
put voltage ripple small and to ensure regulation loop
stability. COUT must have low impedance at the switching
frequency. Ceramic capacitors with X5R or X7R dielectric
are highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the unique
feedback network, the output capacitance can be very
low. The recommended minimum output capacitance for
BUCK BOOST is 47µF.
Figure 5. 2-Phase BUCK Switching Current WaveformsFigure 7. 2-Phase BOOST Mode Switching Current Waveform
Figure 6. 3-Phase BUCK Switching Current Waveforms When
VINBB > VOUTBB
Figure 8. BOOST Mode Switching Current Waveforms When
VINBB < VOUTBB
Table 4. Suggested Inductors for BUCK BOOST
MAX77826Power Management IC
CLKCLK
tSW1Ф3
CLK
tSW1Ф3
CLKCLK
tSW2Ф3
CLK
tSW2Ф3Ф2Ф1
CLKCLK
tSW2Ф2Ф1
CLK
tSW2
CLKCLK
tSW1Ф1
CLK
tSW1Ф1
MANUFACTURERSERIESNOMINAL INDUCTANCE
(µH)
DC RESISTANCE (typ, mΩ)
CURRENT RATING (A) -30% (∆L/L)
CURRENT RATING (A) ∆T = +40°C RISE
DIMENSIONSL x W x H
(mm)
TDKTFM201610GHM 1.0503.83.02.0 x 1.6 x 1.0
Linear Regulators
The MAX77826 provides 15 low dropout linear reg-
ulators including 3 NMOS LDOs, 6 PMOSLV LDOs,
and 6 PMOSLS LDOs. Each of these regulators draws
27µA/18µA (NMOS/PMOS) of quiescent current in normal
operating mode and < 5µA in low power mode. PMOSLV
LDOs allow input voltages as low as 1.7V for optimized
system efficiency.
All regulators can be operated in low power mode that
supports up to 5mA of maximum load current.
The summary of features is:●3 NMOS LDOs (VOUT range: 0.6V to 2.1875V with
12.5mV step)1 x 150mA1 x 450mA1 x 600mA●6 PMOSLV LDOs (VOUT range: 0.8V to 3.975V with
25mV step)3 x 150mA3 x 300mA●6 PMOSLS LDOs (VOUT range: 0.8V to 3.975V with
25mV step)3 x 150mA3 x 300mA±1.5% typical Output Voltage DC Accuracy70dB PSRR at 1kHz
LDO Reference
The MAX77826 has a single LDOREF bias rail. LDOREF
is enabled or disabled along with the central bias block
(SBIA) so that LDOREF is ready whenever any LDO turns
on. It has a very low quiescent current of 2µA typical.
Operating Mode Control
The operation mode bits for each LDO reside in the top
level that controls the enable/disable state for each LDO
through the Lx_EN signal and also controls the operation
modes (low power or normal mode) for each LDO through
the Lx_LPM signal.
Low Power Mode
In low power mode, the quiescent current of each LDO
is reduced from 27µA/18µA (NMOS/PMOS) to less than
5µA. The output current of each LDO is limited to 5mA if
operating in low power mode. Each LDO can be individu-
ally enabled to operate in low power mode.
Soft-Start and Dynamic Voltage Change
When a regulator is enabled, the output voltage ramps to
the final voltage at the slew rate of 30mV/µs. The 30mV/
µs ramp rate results in around 30mA inrush current with
a 1.0µF output capacitor under no load condition. For a
1.8V LDO ramping from 0V, the output voltage regulation
is achieved within 60µs. The soft-start ramp rate is also
the rate of change at the output when switching dynami-
cally between two output voltages without disabling. The
soft-start circuitry of LDOs supports starting into a prebi-
ased output.
Output Active Discharge
Each LDO provides an internal 100Ω resistor for output
active discharge function. If the active discharge function
is enabled (Lx_AD = 1), the internal resistor discharges
the energy stored in the output capacitor to GND when-
ever the regulator is disabled.
Either the regulator remains enabled or the active dis-
charge function is disabled (Lx_AD = 0), the internal resis-
tor is disconnected from the output. If the active discharge
function is disabled, the output voltage decays at a rate
that is determined by the output capacitance and the load
current when the regulator is turned off.
Thermal Considerations
In most applications, the MAX77826 does not dissipate
much heat because of its high efficiency. However, in
applications where the MAX77826 runs with heavy loads
at high ambient temperature, the junction temperature
can exceed the maximum operating temperature. In case
the junction temperature reaches approximately +165°C,
the thermal overload protection triggers. The maximum
power dissipation of the MAX77826 depends on the ther-
mal resistance of the IC package and PCB. The power
dissipated in the device is:
PD = POUT x (1/η - 1)
where η is the efficiency of the regulator and POUT is the
output power delivered to the load.
The maximum allowed power dissipation is:
PMAX = (TJMAX - TA)/θJA
TJMAX - TA is the temperature difference between the
maximum rated junction temperature and the ambient temperature, θJA is the thermal resistance between the
junction and the ambient.
MAX77826Power Management IC
Serial Interface
The I2C-compatible, 2-wire serial interface is used for
regulator on/off control, setting output voltages, and other
functions. See the Register Map for details.
The I2C serial bus consists of a bidirectional serial-data
line (SDA) and a serial clock (SCL). I2C is an open-drain bus. SDA and SCL require pullup resistors (500Ω or greater). Optional 24Ω resistors in series with SDA and
SCL help to protect the device inputs from high voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
System Coniguration
I2C bus is a multimaster bus. The maximum number of
devices that can attach to the bus is only limited by bus
capacitance.
The figure above shows an example of a typical I2C sys-
tem. A device on I2C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates SCL clock signals to control the
data transfer is a master. Any device that is addressed by
the master is considered a slave. When the MAX77826
I2C-compatible interface is operating in normal mode, it is
a slave on I2C bus, and it can be both a transmitter and
a receiver.
Bit Transfer
One data bit transfers for each SCL clock cycle. The data
on SDA must remain stable during the high portion of SCL
clock pulse. Changes in SDA while SCL is high are control
signals (START and STOP conditions).
START and STOP Conditions
When the I2C serial interface is inactive, SDA and SCL
idle high. A master device initiates communication by
issuing a START condition. A START condition is a high-
to-low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high.
A START condition from the master signals the beginning
of a transmission to the MAX77826. The master termi-
nates transmission by issuing a NOT ACKNOWLEDGE
followed by a STOP condition.
A STOP condition frees the bus. To issue a series of com-
mands to the slave, the master can issue REPEATED
START (Sr) commands instead of a STOP command to
maintain control of the bus. In general, a REPEATED
START command is functionally equivalent to a regular
START command.
When a STOP condition or incorrect address is detected,
the MAX77826 internally disconnects SCL from the I2C
serial interface until the next START condition, minimizing
digital noise and feedthrough.
Figure 9. Functional Logic Diagram for Communications Controller
Figure 10. I2C Bit TransferFigure 11. START and STOP Conditions
MAX77826Power Management IC
MASTER
TRANSIMTTER/
RECEIVER
SDA
SCL
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSIMTTER/
RECEIVER
MASTER
TRANSIMTTER/
RECEIVER
SDA
SCL
CHANGE
OF DATA
ALLOWED
DATA LINE STABLE
DATA VALIDPSr
SCL
SDA
tHD;STA
tSU;STAtSU;STO
tHD;STA
Acknowledge
Both the I2C bus master and MAX77826 (slave) generate
acknowledge bits when receiving data. The acknowledge
bit is the last bit of each 9-bit data packet. To generate an
ACKNOWLEDGE (A), the receiving device must pull SDA
low before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period of
the clock pulse. To generate a NOT-ACKNOWLEDGE (nA),
the receiving device allows SDA to be pulled high before
the rising edge of the acknowledge-related clock pulse and
leaves it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
Slave Address
The I2C slave address of the MAX77826 is shown in
Table 5.
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. The I2C specifica-
tion allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77826 does not use any form of clock
stretching to hold down the clock line.
General Call Address
The MAX77826 does not implement I2C specification
general call address. If the MAX77826 sees the gen-
eral call address (00000000b), it does not issue an
ACKNOWLEDGE (A).
Communication Speed
The MAX77826 provides an I2C 3.0-compatible (3.4MHz)
serial interface.●I2C revision 3-compatible serial communications
channel0Hz to 100kHz (standard mode)0Hz to 400kHz (fast mode)0Hz to 1MHz (fast mode plus)0Hz to 3.4MHz (high-speed mode)Does not utilize I2C clock stretching
Operating in standard mode, fast mode and fast mode
plus do not require any special protocols. The main con-
sideration when changing the bus speed through this
range is the combination of the bus capacitance and pul-
lup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds the
pullup resistance must be decreased to maintain a rea-
sonable time constant. Refer to the Pullup Resistor Sizing
section of I2C revision 3.0 specification for detailed guid-
ance on the pullup resistor selection. In general for bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about a 1.5kΩ pullup resis-tors, and a 1MHz bus needs 680Ω pullup resistors. Note
that the pullup resistor dissipates power when the open-
drain bus is low. The lower the value of the pullup resistor,
the higher the power dissipation is (V2/R).
Operating in high-speed mode requires some special
considerations. For the full list of considerations, refer to
the I2C 3.0 specification. The major considerations with
respect to the MAX77826 are:●The I2C bus master uses current source pullups to
shorten the signal rise times.●The I2C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
higher bus speed.●The communication protocols need to utilize the high-
speed master code.
Table 5. Power Management Slave Address
MAX77826Power Management IC
SLAVE ADDRESS (7 bit)
SLAVE ADDRESS (Write)
SLAVE ADDRESS (Read)
110 00000xC0 (1100 0000)0xC1 (1100 0001)
SCL
SDA23119
ACKNOWLEDGE56700R/WA0
At power-up and after each STOP condition, the MAX77826
inputs filters are set for standard mode, fast mode, or fast
mode plus (i.e., 0Hz to 1MHz). To switch the input filters
for high-speed mode, use the high-speed master code
protocols that are described in Communication Protocols
section.
Communication Protocols
The MAX77826 supports both writing and reading from
its registers. Table TBD shows the I2C communication
protocols for each functional block. The power block uses
the same communications protocols.
Writing to a Single Register
Figure 13 shows the protocol for the I2C master device to
write one byte of data to the MAX77826. This protocol is
the same as the SMBus specification’s write byte proto-
col. The write byte protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data
8) The slave acknowledges or does not acknowledges
the data byte. The next rising edge on SDA loads
the data byte into its target register and the data
becomes active.
9) The master sends a STOP condition (P) or a RE-
PEATED START condition (Sr). Issuing a P ensures that the bus input ilters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves the bus input ilters in their current state.
Writing to Sequential Registers
Figure 14 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte proto-
col, except the master continues to write after it receives
the first byte of data. When the master is done writing,
it issues a STOP or REPEATED START. The writing to
sequential registers protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
MAX77826Power Management IC
NUMBER OF
BITS
R/W
SLAVE ADDRESS8
REGISTER POINTERA8
DATAA OR nA
P OR Sr*
SLAVE TO MASTERMASTER TO SLAVE
LEGEND9
ACKNOWLEDGEAB1
THE DATA IS LOADED INTO
THE TARGET REGISTER AND
BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
SCL
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE. Sr LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA LOW.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte. The next
rising edge on SDA loads the data byte into its target
register, and the data becomes active.
8) Steps 6 and 7 are repeated as many times as the
master requires.
9) During the last acknowledge related clock pulse, the
master can issue an ACKNOWLEDGE (A) or a NOT
ACKNOWLEDGE (nA).
10) The master sends a STOP condition (P) or a RE-
PEATED START condition (Sr). Issuing a P ensures that the bus input ilters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves the bus input ilters in their current state.
MAX77826Power Management IC
NUMBER OF
BITS
R/NW
SLAVE ADDRESS8
REGISTER POINTER XA8
DATA XA
NUMBER OF
BITS8
DATA X+1A8
DATA X+2A
NUMBER OF
BITS8
DATA N-1A8
DATA N
SLAVE TO MASTERMASTER TO SLAVE
LEGEND9
ACKNOWLEDGEAB1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
SDA
SCL
DETAIL: Α9
ACKNOWLEDGEAB1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
SDA
SCL
DETAIL: ΒΑΒ
A OR NA
P OR SR*
*P FORCES THE BUS
FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE. Sr
LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
REGISTER POINTER =
X + 1REGISTER POINTER = X +
REGISTER POINTER =
X + (N - 2)
REGISTER POINTER =
X + (N - 1)
Writing Multiple Bytes using Register-Data Pairs
Figure 15 shows the protocol for I2C master device to
write multiple bytes to the MAX77826 using register-data
pairs. This protocol allows I2C master device to address
the slave only once and then send data to multiple reg-
isters in a random order. Registers can be written con-
tinuously until the master issues a STOP condition. The
multiple byte register-data pair protocol is as follows:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte. The next
rising edge on SDA loads the data byte into its target
register and the data becomes active.
8) Steps 4 to 7 are repeated as many times as the
master requires.
9) The master sends a STOP condition. During the ris-
ing edge of the stop related SDA edge, the data byte
that was previously written is loaded into the target
register and becomes active.
Figure 15. Writing to Multiple Registers with Multiple Byte Register-Data Pairs Protocol
MAX77826Power Management IC
NUMBER OF BITS
R/nW
SLAVE ADDRESS8
REGISTER POINTER XA8
DATA XA
NUMBER OF BITS8
REGISTER POINTER nA8
DATA nA
NUMBER OF BITS8
REGISTER POINTER ZA8
DATA ZA
SLAVE TO MASTERMASTER TO SLAVE
LEGEND9
ACKNOWLEDGEAB1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
SDA
SCL
DETAIL: α9
ACKNOWLEDGEAB1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
SDA
SCL
DETAIL: β

Partno	Mfg	Dc	Qty	Available	Descript
MAX77826EWJ+T	MAXIM	N/a	8000	avai	Power Management IC