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MAX769EEI+
2 or 3 Cell, Step-Up/Down, Two-Way Pager System IC
________________General DescriptionThe MAX769 is a complete buck/boost power supply
and monitoring system for two-way pagers or other low-
power digital communications devices. Few external
components are required. Included on-chip are:An 80mA output, synchronous-rectified, buck/boost
DC-DC converter with a digitally controlled +1.8V to
+4.9V output. The DC-DC converter is unique, since
it provides a regulated output for battery inputs that
are both less than and greater than the output volt-
age, without using transformers.Three low-noise linear-regulator outputsThree DAC-controlled comparators for software-
driven, 3-channel A/D conversionSPI™-compatible serial interfaceReset and low-battery (LBO) warning outputsCharger for NiCd/NiMH, lithium battery, or storage
capacitor for RF PA power or system backupTwo 1.8Ω(typical), serial-controlled, open-drain
MOSFET switches for beeper or vibrator drive
An evaluation kit for the MAX769 (MAX769EVKIT) is
available to aid in design and prototyping.
____________________________FeaturesRegulated Step-Up/Step-Down Operation80mA Output from 3 Cells85% Efficiency13μA Idle Mode™(coast) Current Selectable Low-Noise PWM or Low-Current PFM
OperationPWM Operating Frequency Synchronized to
Seven Times an External Clock SourceOperates at 270kHz with No External ClockAutomatic Backup-Battery Switchover
________________________ApplicationsTwo-Way Pagers
GPS Receivers
2 or 3-Cell Powered, Hand-Held Equipment
or 3-Cell, Step-Up/Down, o-Way Pager System ICMAX769
INPUT
2 OR 3 AA ALKALINE BATTERIES
1.5V TO 5.5VBATT
LX2
OUT
PGND
REG2IN
OFS
REG2
OUTPUT 2
2.85V ANALOG
LOW-BATTERY
IN/OUT
REJECT
IN/OUT
SERIAL
I/O
1.8W
DRIVERS
A/D
INPUT
OPTIONAL
OUTPUT 1
3V LOGIC
OUTPUT 3
1V RECEIVER
TO RF PA
NiCd
BATTERY OR
STACK
REG1
REG3
NICDAGNDREFFILT
LBI
LBO
RSIN
RSO
SCL
SD1
SD03
DR1
DR2
DR2IN
DRGND
CH0
SYNC
LX1
STORAGE
CAPACITOR
___________________________________________________Typical Operating Circuit19-4771; Rev 1; 10/98
PARTMAX769EEI-40°C to +85°C
TEMP. RANGEPIN-PACKAGE28 QSOP
Ordering InformationIdle Mode is a trademark of Maxim IntegratedProducts. SPI is a trademark of Motorola, Inc.
Pin Configuration appears at end of data sheet.
EVALUATION KIT MANUAL
FOLLOWS DATA SHEET
or 3-Cell, Step-Up/Down, o-Way Pager System ICABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(OUT = 3.0V, BATT = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
BATT, OUT, NICD, LBO, RSO to AGND...................-0.3V to +6V
REG1, REG2, OFS, REF, R2IN to AGND.....-0.3V to (OUT + 0.3V)
SCL, SDO, SDI, CS, SYNC, FILT, DR2IN,
CH0, LBI, RSIN to AGND......................-0.3V to (REG1 + 0.3V)
REG3.......................................................-0.3V to (REG2 + 0.3V)
DR1, DR2 to DRGND...............................-0.3V to (BATT + 0.3V)
PGND, DRGND to AGND......................................-0.3V to +0.3V
LX1 to PGND.............................................-0.3V to (OUT + 0.3V)
LX2 to PGND............................................-0.3V to (BATT + 0.3V)
Continuous Power Dissipation (TA= +70°C)
QSOP (derate 8mW/°C above +70°C)..........................640mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10sec).............................+300°C
IREF= 0 to 20μA, OUT = 1.8V to 4.9VV-1.5%1.28 1.5%= +25°C
Reference Voltage
IDR= 120mA
Run or Coast Mode1.82.8DR1, DR2 On-Resistance
VDR= 5VnA1250DR1, DR2 Leakage Current
Charger and Backup Modes off, NICD = 3.6VμA
Incremental supply current when on
REG2, REG3 and CH DAC off, VOUT= 2.8V
REG2, REG3 and CH DAC on
Coast Mode
Incremental supply current when on= +25°C
CONDITIONS= -40°C to +85°C
ISDO= 100μAmV200SDO Output Low
ISDO= -100μA, from REG1VVREG1
- 0.2 SDO Output High
Includes CS, SDI, SCL, DR2IN, and SYNCV0.4Logic Input Level Low
Includes CS, SDI, SCL, DR2IN, and SYNCVVREG1
- 0.4 Logic Input Level High
Charger and Backup Modes off, BATT = 0V,
OUT = 0VμA1.23NICD Input Current, Power Fail
(Note 8)
Logic Input = 0 to 3.3V; includes CS, SDI, SCL,
DR2IN, and SYNCμA1.62.01
BATT Minimum Start-Up Voltage
(Note 3)1.55.5
Logic Input Current
NICD Input Current, Standby
(Note 6)
BATT Typical Operating Range
(Note 2)
Incremental supply current when onμA
Backup Mode, NICD = 3.6V, OUT = 3VREG2 Supply Current (Note 4)2040NICD Input Supply Current, Backup
(Note 7)30CH DAC Supply Current (Note 4)1325Coast Mode Supply Current (Note 4)8751350Run Mode Supply Current (Note 4)410BATT Supply Current (Note 5)20REG3 Supply Current (Note 4)
UNITSMINTYPMAXPARAMETER
GENERAL PERFORMANCE
or 3-Cell, Step-Up/Down, o-Way Pager System ICELECTRICAL CHARACTERISTICS (continued)(OUT = 3.0V, BATT = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)-3.53.5OUT Error, Coast Mode
(Note 11)
Coast Mode, OUT = 1.8V to 4.9V
-3.53.5OUT Error, Run Mode (Note 12)
Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V
Run Mode, OUT = 1.8V to 4.9V
Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V
CONDITIONSBATT = 1.6V to 4.5VmV25OUT Line Regulation
IOUT= 80mA, COUT= 47μF with ESR < 0.25WmVp-p70OUT Voltage Ripple
LX1, LX2, BATT = 3.0VW0.91.8LX On-Resistance (Note 14)5050CSto SCL Hold Time (tCSH)to SCL Setup Time (tCSS)100SDI Setup Time (tDS)
NMOS
PMOS1.32.6= +25°C, FILT connected to REFkHz210270325Frequency, Free-Run
Backup Mode, NICD = 3.3V
fSYNC= 38.4kHz100
kHzPulse Width High (tCSW)
Frequency, Lockedto SDO Disable (tTR)
fSYNC= 38.4kHz, FILT Network = 1nFœœ(22nF + 10kΩ)kHz±15Jitter (Note 15)10
fSYNC= 38.4kHz, FILT Network = 1nFœœ(22nF + 10kΩ)ms125Capture Time (Note 15)
Backup-Regulator
On-Resistance (Note 16)50
0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1
SCL Pulse Width High or Low
(tCH, tCL)8011525
Output Current, Run Mode
(Note 10)1540
Current High
Output Current, Coast Mode
(Note 10)
UNITSMINTYPMAXPARAMETER0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1mA0.451.5Current Low
OUT = 2.8V, IOUT= 20mA, NICD = 3.3V%-3.53.5OUT Error, Backup Regulator
50% duty cycleMHz5SCL Maximum Clock Rate
OUT = 3.0V%7683Maximum LX Duty Cycle
During the inductor charge cyclemA300350400LX Switch Current Limit7070CSto SDO Output Valid (tDV)
SCL to SDO Output Valid (tDO)50SDI Hold Time (tDH)
IOUT= 1mA to 80mA, Run ModemV25OUT Load Regulation
Coast or Run Mode, OUT = 1.8V to 4.9VmV30100170OUT DAC Step Size (Note 13)
SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9)
DC-DC CONVERTER
PHASE-LOCKED LOOP (PLL)
NICD CHARGER
M or 3-Cell, Step-Up/Down, o-Way Pager System ICELECTRICAL CHARACTERISTICS (continued)(OUT = 3.0V, BATT = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
10mV overdrive
REG3 Output Voltage
IREG3= 0 to 2mA0.961.01.04V
IREG2= 0 to 24mA, OUT = 3.0V, ROFS= 15kWmV120155190REG2 Voltage Drop
3.23.33.450LBO/RSO Response Time
(Note 16)
OUT = 3.0V, IREG1= 65mA
f = 268.8kHz, CREG1= 10μF ceramic
Falling input
CONDITIONSf = 268.8kHz, CREG1= 10μF, ceramic, ROFS= 15kW,
COFS= 0.1μF, IREG2= 15mAdB3040REG2 Supply Rejection
(Note 16)
f = 268.8kHz, CREG1= 1μF ceramicdB4050REG3 Supply Rejection (Note 16)
0.580.600.63LBI/RSIN Input Threshold
At thresholds of 200mV, 800mV, and 1270mV%-2.0 2.0
- 15mV+ 15mVCH0 Error
At thresholds of 1200mV, 3200mV, and 5080mV%-3.0 3.0
- 60mV+ 60mV10CH0 Threshold Resolution
(Note 16)0.21.27CH0 Threshold Range (Note 16)
Measures NICDV1.25.08CH1 Threshold Range (Note 16)
Measures BATTV
CH1 Error
IREG2= 0.1mA to 24mAmV-50-350LBI/RSIN Input Current
IOUT= 1mA
CH2 Threshold Range (Note 16)
Measures BATT40CH2 Threshold Resolution
(Note 16)400LBO/RSO Output Low
Measures NICDmV
Output = 5.5VnA1250LBO/RSO Output LeakageCH1 Threshold Resolution
(Note 16)1.53.1REG1 PMOS On-Resistance1525
REG1 Supply Rejection (Note 16)
7.51630LBI/RSIN Input Hysteresis
(Note 16)REG2 Load Regulation
UNITSMINTYPMAXPARAMETERIOUT= 1mA, OUT = 4.9VV3.153.45REG1 Clamp VoltageTA= +25°C= -40°C to +85°C
At thresholds of 1200mV, 3200mV, and 5080mV%-3.0 3.0
- 60mV+ 60mVCH2 Error124CH0 Input Hysteresis (Note 16)
LINEAR REGULATORS
DATA-ACQUISITION AND VOLTAGE MONITORSCH1 Input Hysteresis (Note 16)4816mV
or 3-Cell, Step-Up/Down, o-Way Pager System ICELECTRICAL CHARACTERISTICS (continued)(OUT = 3.0V, BATT = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Note 1:Specifications to -40°C are guaranteed by design, not production tested.
Note 2:This is not a tested parameter, since the IC is powered from OUT, not BATT.
Note 3:Minimum start-up voltage is tested by determining when the LX pins can draw at least 15mA for 0.5μs (min) at a 285kHz
(min) repetition rate. This guarantees that the IC will deliver at least 200μA at the OUT pin.
Note 4:This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and
on the DC-to-DC converter’s efficiency.
Note 5:Current into BATT pin in addition to the supply current at OUT. This current is roughly constant from Coast to Run Mode.
Note 6:Current into NICD pin when NICD isn’t being charged and isn’t regulating OUT.
Note 7:Current into NICD pin when NICD is regulating OUT. Doesn’t include current drawn from OUT by the rest of the circuit.
Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V.
Note 8:Current into the NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won’t draw significant cur-
rent when the main battery is removed and backup is not activated.
Note 9:Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionali-
ty is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set
below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation.
Note 10:This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests.
Note 11:Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn’t include
ripple voltage due to inductor currents.
Note 12:Measured by using the internal feedback network and Run-Mode error comparator to regulate OUT. Doesn’t include ripple
voltage due to inductor currents.
Note 13:Uses the OUT measurement techniques described for the OUT error, Coast Mode, and OUT error Run Mode specifica-
tions.
Note 14:The on-resistance is for either LX1 or LX2.
Note 15:PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided
for design guidance only.
Note 16:The limits in this specification are not guaranteed and are provided for design guidance only.
CH0 = 0.2V to 1.27VnA-100100CH0 Input Current
10mV overdriveμs0.61.0CH Comparator Response Time
(Note 16)
CONDITIONS4816CH2 Input Hysteresis (Note 16)
UNITSMINTYPMAXPARAMETER
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(RUN MODE, VOUT = 3.0V)
X769-01
LOAD CURRENT (mA)
(%
VIN = 5.0V
VIN = 1.5VVIN = 2.0V
VIN = 3.5V
VIN = 2.5V
EFFICIENCY vs. LOAD CURRENT
(COAST MODE, VOUT = 3.0V)
AX769-02
LOAD CURRENT (mA)
(%VIN = 5.0V
VIN = 3.5V
VIN = 2.5V
VIN = 2.0V
VIN = 1.5V
EFFICIENCY vs. LOAD CURRENT
(COAST MODE, VOUT = 2.4V)
X769-03
LOAD CURRENT (mA)
(%VIN = 5.0V
VIN = 3.5V
VIN = 2.5V
VIN = 2.0V
VIN = 1.5V
or 3-Cell, Step-Up/Down, o-Way Pager System ICTypical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
NO-LOAD BATTERY CURRENT
vs. BATTERY VOLTAGE
AX769-04
BATTERY VOLTAGE (V)
(m
VOUT = 3.0V
COAST MODE
MAXIMUM LOAD CURRENT
vs. BATTERY VOLTAGE
AX769-05
BATTERY VOLTAGE (V)
(m
RUN MODE
COAST MODE
VOUT = 3.0V10100
START-UP BATTERY VOLTAGE
vs. LOAD CURRENTAX769-06
LOAD CURRENT (mA)
(V
VOUT = 3.0V
COAST MODE213456
NICD CHARGING CURRENT vs.
NICD VOLTAGEAX769-07
NICD VOLTAGE (V)
(m
15mA MODE
VOUT = 4.9V21345
DR1 OR DR2 ON-RESISTANCE vs. VOUTX769-08
VOUT VOLTAGE (V)
(W
LX NOISE SPECTRUM
(RUN MODE, SYNC OPERATION)
AX769-09
FREQUENCY (kHz)
(d
0.1101100100010,000
REG2 NOISE SPECTRUM
(RUN MODE)X769-10
FREQUENCY (kHz)
(d
or 3-Cell, Step-Up/Down, o-Way Pager System ICPin DescriptionOUTDC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps
(Table 5).CSChip Select for SPI Serial InterfaceLX2Connect LX2 to the other inductor terminal. LX2 is internally connected to an NFET that switches to PGND
and a PFET that switches to BATT.BATTPositive Connection to Battery. The IC is powered from OUT.REG1PFET Output Connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of the
voltage set at OUT.REG31V, 2mA Regulator Output. On via the serial interface. Low noise.R2INREG2 Input. Connect to OUT, REG1, or another voltage source.NICD15mA or 1mA Settable Charge Current from OUT to 3-Cell NiCd Stack. When the NICD_REG_ON bit is set
(Table 1), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off.REG224mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference = 10μA x ROFS).
REG2 isolates noise.DR2INLogic Input. ANDed with the DR2ON bit to control the DR2 switch.DR2Open-Drain FET Switch. On via AND of the DR2ON bit and the DR2IN pin.DR1Open-Drain FET Switch. Activated via the serial-interface bit.CH0CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the CH0
OUT register.SYNCSync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (seven times the SYNC
frequency).AGNDAnalog GroundDRGNDGround for DR1 and DR2 FET SourcesOFSResistor sets offset between OUT (or REG1 or any other point) and REG2. ROFS= 15kΩresults in 150mV.LBILow-Battery Input. Triggers LBO and internal serial bit.FILTAn external RC network sets the PLL loop response to adjust frequency lock time versus jitter: 1nF || (22nF +
10kΩ).RSINReset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV).SCLSerial Clock for SPI InterfaceRSOReset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set) to
POR state as well.REF1.28V Reference. Bypass with a 1μF capacitor.LBOOpen-Drain Output for LBI ComparatorSDOSerial Data Output for SPI InterfacePGNDPower Ground. Source of LX1 and LX2 NFETs.SDISerial Data Input for SPI Interface
NAMEFUNCTIONLX1Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET that
switches to OUT.
PIN
or 3-Cell, Step-Up/Down, o-Way Pager System ICLB0
TO S1
AND S2
LBI
CH0
0.6V
CH0
RUN/
COAST
OV0–OV4
SERIAL
I/O
CH1
CH2DAC0–DAC7
RESET
CONTROL
V FEEDBACK
CHARGE
NICD
BACKUP
REGULATOR
PWM
(PFM IN
COAST)
CHG/REG
CPLB
CP0
CP1
CP2527
SDOSDISCL26
REF
0.6VF
10mA
1.0V
REG3F
RSIN1018191615
DR1DR2INDR2AGNDDRGND
1.8W1.8W
REG2 ON
REG3 ONN
FROM
NICD
FROM
BATTERY
7-BIT
DAC
REG2
REG1
R2IN
COFS
0.1mF
OFS
NICD
ROFS
15k
10mF
10mF
OUT
SYNC
FILT
PGND
LX2
LX1
BATT
2- OR 3-CELL
BATTERY IN
68mH
22mF
47mFAOUT
1.28V
REFERENCE
1.0V–
BACKUP
REGULATOR
CLAMP ON WHEN
OV4 = 1
3.3V
CLAMP
1mA/15mA
3.3VAR1
AR2
AR31nF
22nF
10k
PLL
LBO
RSO
MAX7694
CPRS
Figure 1. MAX769 Block Diagram
