MAX7359ETG+ ,2-Wire Interfaced Low-EMI Key Switch Controller/GPOfeatures autosleep and autowake to fur- ♦ FIFO Queues Up to 16 Debounced Key Eventsther minimize th ..
MAX7359ETG+T ,2-Wire Interfaced Low-EMI Key Switch Controller/GPOFeatures2The MAX7359 I C interfaced peripheral provides micro- ♦ Optional Key Release Detection on ..
MAX735CPA ,-5V/Adjustable, Negative-Output,Inverting, Current-mode PWM Regulatorsfeatures, along with high efficiency and appli-
cations circuits that lend themselves to miniaturi ..
MAX735CPA ,-5V/Adjustable, Negative-Output,Inverting, Current-mode PWM RegulatorsFeatures
. Converts +2.7V to +9V In
Negative Output (MAX75
t" to Adjustable
. Converts +4 ..
MAX735CPA ,-5V/Adjustable, Negative-Output,Inverting, Current-mode PWM RegulatorsGeneral Description
The MAX735 and MAX755 are CMOS, inverting switch-
mode regulators with inte ..
MAX735CPA+ ,-5V, Inverting, PWM DC-DC Converterapplications.
The MAX735/MAX755 employ a high-performance current-
mode pulse-width modulation ..
MB6021A ,SINGLE CHIP CODEC WITH FILTERSFUJITSU hTCRoirLECTR()NTCS 31.5 D, " 37u=17aa 001.71.55 =1 "hu
April 1990
Edition 3.0
DA TA ..
MB6021AP ,SINGLE CHIP CODEC WITH FILTERSFUNCTIONAL DESCRIPTION
The simplified
MB6022 , Product Summary Prototyping Kits
MB6022 , Product Summary Prototyping Kits
MB6022A ,SINGLE CHIP CODEC WITH FILTERSFUNCTIONAL DESCRIPTION
The simplified
MB6M ,MINIATURE GLASS PASSIVATED SINGLE-PHASE BRIDGE RECTIFIERThermal Characteristics (TA = 25°C unless otherwise noted)Parameter Symbol MB2M MB4M MB6M UnitDevic ..
MAX7359BETG+-MAX7359ETG+-MAX7359ETG+T
2-Wire Interfaced Low-EMI Key Switch Controller/GPO
General DescriptionThe MAX7359 I2C interfaced peripheral provides micro-
processors with management of up to 64 key switches.
Key codes are generated for each press and release of
a key for easier implementation of multiple key entries.
Key inputs are monitored statically, not dynamically, to
ensure low-EMI operation. The switches can be metallic
or resistive (carbon) with up to 5kΩof resistance.
The MAX7359 features autosleep and autowake to fur-
ther minimize the power consumption of the device.
The autosleep feature puts the device in a low-power
state (1µA typ) after a sleep timeout period. The
autowake feature configures the MAX7359 to return to
normal operating mode from sleep upon a key press.
The key controller debounces and maintains a FIFO of
key-press and release events (including autorepeat, if
enabled). An interrupt (INT) output can be configured to
alert key presses either as they occur, or at maximum rate.
Any of the column drivers (COL2/PORT2–COL7/PORT7)
or the INT, if not used, can function as a general-pur-
pose output (GPO).
The MAX7359 is offered in small, 24-pin TQFN (3.5mm x
3.5mm) and 25-bump WLP (2.31mm x 2.31mm) pack-
ages for cell phones, pocket PCs, and other portable
consumer electronic applications. The MAX7359 oper-
ates over the -40°C to +85°C temperature range.
ApplicationsCell Phones
PDAs
Handheld Games
Portable Consumer Electronics
FeaturesOptional Key Release Detection on All KeysMonitor Up to 64 Keys+1.62V to +3.6V OperationAutosleep and Autowake to Minimize Current
ConsumptionUnder 1µA Sleep CurrentFIFO Queues Up to 16 Debounced Key EventsKey Debounce Time User Configurable from 9ms
to 40msLow-EMI Design Uses Static Matrix MonitoringHardware Interrupt at the FIFO Level or at the End
of Definable Time PeriodUp to Seven Open-Drain Logic Outputs Available
Capable of Driving LEDs400kbps, 5.5V-Tolerant, 2-Wire Serial InterfaceSelectable 2-Wire, Serial-Bus TimeoutFour I2C Address ChoicesSmall, 24-Pin TQFN Package (3.5mm x 3.5mm), or
25-Pin WLP Package (2.31mm x 2.31mm)
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
Ordering Information19-0850; Rev 4; 6/10
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX7359ETG+-40°C to +85°C24 TQFN-EP*
MAX7359EWA+-40°C to +85°C25 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAX7359
VCCCOL_
GND
SCL
SDA
AD0
ROW_
SWITCH
ARRAY,
UP TO 64
SWITCHES
INPUT
+1.62V TO +3.6V
INT
Typical Application Circuits
Pin ConfigurationsMAX7359234561716151413
INT
N.C.
VCC
COL7/PORT7
ROW1
ROW2ROW3
COL3/PORT3COL4/PORT4
ROW4ROW5
SCLSDA
GND
I.C.COL0
ROW0
COL1
COL5/PORT5
COL2/PORT2
COL6/PORT6
ROW6
ROW7
AD0
TOP VIEW
TQFN
(3.5mm x 3.5mm)EP*
*EP = EXPOSED PAD.
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC..........................................................................-0.3V to +4V
COL2/PORT2–COL7/PORT7....................................-0.3V to +4V
SDA, SCL, AD0, INT.................................................-0.3V to +6V
All Other Pins..............................................-0.3V to (VCC+ 0.3V)
DC Current on COL2/PORT2–COL7/PORT7 ......................25mA
GND Current.......................................................................80mA
Continuous Power Dissipation (TA= +70°C)
24-Pin TQFN (derate 15.4mW/°C above +70°C)........1229mW
25-Bump WLP (derate 19.2mW/°C above +70°C)......1194mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
24-Pin TQFN.................................................................5.4°C/W
25-Bump WLP...............................................................17°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
24-Pin TQFN...............................................................65.1°C/W
25-Bump WLP...............................................................53°C/W
Operating Temperature Range (TMINto TMAX).....-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (TQFN only, soldering, 10s)..............+300°C
Soldering Temperature (reflow).......................................+260°C
ELECTRICAL CHARACTERISTICS(VCC= +1.62V to +3.6V, TA= TMINto TMAX,unless otherwise noted. Typical values are at VCC= +2.5V, TA= +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Supply VoltageVCC1.623.60V
All key switches open, oscillator running,
COL2–COL7 configured as key switches2560
Operating Supply CurrentICC
N keys pressed(25 +
20 x N)
Sleep-Mode Supply CurrentISL0.65µA
POR1.01.6V
POR HysteresisPORHYSTVCC rising42mV
Key-Switch Source CurrentIKEY2035µA
Key-Switch Source VoltageVKEYOperating mode0.420.55V
Key-Switch ResistanceRKEY(Note 4)5kΩ
Startup Time from ShutdowntSTART22.4ms
Output Low Voltage
COL2/PORT2 to COL7/PORT7VOLPORTISINK = 10mA0.2V
INT OutputVOLINTISINK = 10mA0.5V
Oscillator FrequencyFOSC64kHz
SERIAL-INTERFACE SPECIFICATIONSSerial Bus TimeouttOUTWith bus timeout enabled1040ms
Input High Voltage
SDA, SCL, AD0VIH0.7 x
VCCV
Input Low Voltage
SDA, SCL, AD0VIL0.3 x
VCCV
Output Low Voltage SDAVOLPORTISINK = 10mA0.4V
Note 1:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO2C TIMING CHARACTERISTICS(VCC= +1.62V to +3.6V, TA= TMINto TMAX,unless otherwise noted. Typical values are at VCC= +2.5V, TA= +25°C.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput Capacitance
(SCL, SDA, AD0)CIN(Notes 4, 5)10pF
SCL Serial-Clock FrequencyfSCLBus timeout disabled0400kHz
Bus Free Time Between a STOP
and a START ConditiontBUF1.3µs
Hold Time (Repeated) START
ConditiontHD, STA0.6µs
Repeated START Condition
Setup TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD, DAT(Note 6)0.9µs
Data Setup TimetSU, DAT100ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.7µs
Rise Time of Both SDA and SCL
Signals, ReceivingtR(Notes 4, 5)20 +
0.1Cb300ns
Fall Time of Both SDA and SCL
Signals, ReceivingtF(Notes 4, 5)20 +
0.1Cb300ns
Fall Time of SDA TransmittingtF, TX(Notes 4, 7)20 +
0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Notes 4, 8)50nsap aci ti ve Load for E ach Bus Li neCb(Note 4)400pF
Note 2:All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 3:All digital inputs at VCCor GND.
Note 4:Guaranteed by design.
Note 5:Cb= total capacitance of one bus line in pF. tRand tFmeasured between +0.3VCCand +0.7VCC.
Note 6:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7:ISINK≤6mA.
Note 8:Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPOGPO PORT OUTPUT LOW VOLTAGE
vs. SINK CURRENT
MAX7359 toc01
ISINK (mA)
(mV)
VCC = +2.4V
TA = +85°C
TA = +25°C
TA = -40°C
GPO PORT OUTPUT LOW VOLTAGE
vs. SINK CURRENT
MAX7359 toc02
ISINK (mA)
(mV)
TA = +85°C
TA = -40°C
VCC = +3.0V
TA = +25°C
GPO PORT OUTPUT LOW VOLTAGE
vs. SINK CURRENT
MAX7359 toc03
ISINK (mA)
(mV)
VCC = +3.6V
TA = +85°C
TA = -40°C
TA = +25°C
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7359 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
AUTOSLEEP = OFF
TA = +85°C
TA = -40°C
TA = +25°C
KEY-SWITCH SOURCE CURRENT
vs. SUPPLY VOLTAGEMAX7359 toc05
SUPPLY VOLTAGE (V)
KEY-SWITCH SOURCE CURRENT (
COL0 = GND
TA = +85°C
TA = -40°C
TA = +25°C
SLEEP MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7359 toc06
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
Typical Operating Characteristics(VCC= +2.5V, TA= +25°C, unless otherwise noted.)
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO64kHz
OSCILLATOR
PORBUS
TIMEOUT2C
INTERFACE
CONTROL
REGISTERS
FIFO
KEY SCAN
CURRENT
SOURCE
COLUMN
DRIVES
OPEN-
DRAIN
ROW
DRIVES
COLUMN ENABLE
GPO ENABLE
ROW ENABLE
CURRENT DETECT
COL0
COL1
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
INT
SDA
SCL
*GPO
MAX7359
Functional Block Diagram
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
Detailed DescriptionThe MAX7359 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events are presented
in a 16-byte FIFO. Key-switch functionality can be traded
to provide up to six open-drain logic outputs.
The MAX7359 features an automatic sleep mode and
automatic wakeup that further reduce supply current con-
sumption. The MAX7359 can be configured to enter sleep
mode after a programmable time following a key event.
The FIFO content is maintained during sleep mode and
can be read in sleep mode. The MAX7359 does not enter
autosleep when a key is held down. The autowake feature
takes the MAX7359 out of sleep mode following a key-
Interrupt requests can be configured to be issued on a
programmable number of FIFO entries, or can be set
to a period of time to prevent overloading the micro-
processor with too many interrupts. The key-switch sta-
tus can be checked at any time by reading the
key-switch FIFO. A 1-byte read access returns both the
next key-event in the FIFO (if there is one) and the
FIFO status, so it is easy to operate the MAX7359 by
polling. If the INTpin is not required, it can be config-
ured as an open-drain general-purpose output (GPO)
capable of driving an LED.
If the application requires fewer keys to be scanned, up
to six of the key-switch outputs can be configured as
open-drain GPOs capable of driving LEDs. For each
key-switch output used as a GPO, the number of key
Pin Description
PIN
TQFNWLPNAMEFUNCTION1A1ROW2Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.
2A2ROW3Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
3A3COL3/PORT3Column Output to Key Matrix or GPO. Leave COL3/PORT3 unconnected if unused.
4B3COL4/PORT4Column Output to Key Matrix or GPO. Leave COL4/PORT4 unconnected if unused.
5A4ROW4Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.
6A5ROW5Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.
7B5ROW6Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.
8B4ROW7Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
9C5COL6/PORT6Column Output to Key Matrix or GPO. Leave COL6/PORT6 unconnected if unused.C4COL5/PORT5Column Output to Key Matrix or GPO. Leave COL5/PORT5 unconnected if unused.D5COL2/PORT2Column Output to Key Matrix or GPO. Leave COL2/PORT2 unconnected if unused.E5COL1Column Output to Key Matrix. Leave COL1 unconnected if unused.E4COL0Column Output to Key Matrix. Leave COL0 unconnected if unused.D4I.C.Internally Connected. Connect to GND for normal operation.D3GNDGroundE3AD0Adddress Input. ADO selects up to four device slave addresses (Table 10).E2SDAI2C-Compatible, Serial-Data I/OD2SCLI2C-Compatible, Serial-Clock InputE1INTActive-Low Interrupt Output. INT is open drain.D1VCCPositive Supply Voltage. Bypass VCC to GND with a 0.047µF or higher ceramic capacitor.C2, C3N.C.No Connection. Not internally connected.C1COL7/PORT7Column Output to Key Matrix or GPO. Leave COL7/PORT7 unconnected is unused.B2ROW0Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.B1ROW1Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.EPExposed Pad (TQFN only). EP internally is connected to GND. Connect EP to a ground plane
to increase thermal performance.
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
PINCOL0COL1COL2/PORT2COL3/PORT3COL4/PORT4COL5/PORT5COL6/PORT6COL7/PORT7
ROW0KEY 0KEY 8KEY 16KEY 24KEY 32KEY 40KEY 48KEY 56
ROW1KEY 1KEY 9KEY 17KEY 25KEY 33KEY 41KEY 49KEY 57
ROW2KEY 2KEY 10KEY 18KEY 26KEY 34KEY 42KEY 50KEY 58
ROW3KEY 3KEY 11KEY 19KEY 27KEY 35KEY 43KEY 51KEY 59
ROW4KEY 4KEY 12KEY 20KEY 28KEY 36KEY 44KEY 52KEY 60
ROW5KEY 5KEY 13KEY 21KEY 29KEY 37KEY 45KEY 53KEY 61
ROW6KEY 6KEY 14KEY 22KEY 30KEY 38KEY 46KEY 54KEY 62
ROW7KEY 7KEY 15KEY 23KEY 31KEY 39KEY 47KEY 55KEY 63
Table 1. Key-Switch Mapping
ADDRESS
CODE (hex)READ/WRITEPOWER-UP VALUE
(hex)
REGISTER
FUNCTIONDESCRIPTION0x00Read only0x3FKeys FIFORead FIFO key scan data out
0x01R/W0x0AConfigurationPower down, key release enable, autowakeup, and
I2C timeout enable
0x02R/W0xFFDebounceKey debounce time setting and GPO enable
0x03R/W0x00InterruptINT frequency setting
0x04R/W0xFEPortsPorts 2–7 and INT GPO control
0x05R/W0x00Key repeatDelay and frequency for key repeat
0x06R/W0x07SleepIdle time to autosleep
Table 2. Register Address Map and Power-Up Condition
Key-Scan ControllerKey inputs are scanned statically, not dynamically, to
ensure low-EMI operation. As inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The key controller debounces and maintains a FIFO of
key-press and release events (including autorepeated
key presses, if autorepeat is enabled). Table 1 shows
keys order.
_____________________Initial Power-UpOn power-up, all control registers are set to power-up
values and the MAX7359 is in sleep mode (Table 2).
Registers Description
Keys FIFO Register (0x00)The keys FIFO register contains the information pertain-
ing to the status of the keys FIFO, as well as the key
events that have been debounced (Table 3). Bits D0 to
D5 denote which of the 64 keys have been debounced
and the keys are numbered as in Table 1.
D7 indicates if there is more data in the FIFO except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one
more time to determine whether there is more data in
FIFO. It is better to use key 62 and key 63 for rarely
used keys. D6 indicates if it is a key-press or release
event except when D5:D0 indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INT
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)The configuration register controls the I2C bus timeout
feature, enables key release detection, enables autowake,
and determines how INTshould be deasserted.By writing
to bit D7, you can put the MAX7359 into sleep mode or
operating mode, however, autosleep and autowake,
when enabled, also change the status of this bit (Table 4).
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
KEYS FIFO REGISTER DATASPECIAL FUNCTIOND7D6D5D4D3D2D1D0The key number indicated by D5:D0 is a key event. D7
is always for a key press of key 62 and key 63. When
D7 is 0, the key read is the last data in the FIFO. When
D7 is 1, there is more data in the FIFO. When D6 is 1,
key data read from FIFO is a key release. When D6 is
0, key data read from FIFO is a key press.
FIFO
empty
flag
Key
release
flagXXXX
FIFO is empty.00111111
FIFO is overflow. Continue to read data in FIFO.01111111
Key 63 is pressed. Read one more time to determine
whether there is more data in FIFO.10111111
Key 63 is released. Read one more time to determine
whether there is more data in FIFO.11111111
Key repeat. Indicates the last data in FIFO.00111110
Key repeat. Indicates more data in FIFO.01111110
Key 62 is pressed. Read one more time to determine
whether there is more data in FIFO.10111110
Key 62 is released. Read one more time to determine
whether there is more data in FIFO.11111110
Table 3. Keys FIFO Register Format (0x00)
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
REGISTER BITDESCRIPTIONVALUEFUNCTIONDEFAULT VALUESleep modeSleepOperating mode
I2C write, autosleep and
autowakeup all can
change this bit. This bit
can be read back by
I2C any time for current
status.Reserved0This bit must always be 0. Improper operation
may result by writing a 1 to this location.0INT cleared when FIFO emptyINTERRUPT1
INT cleared after host read.
In this mode, I2C should read FIFO until
interrupt condition removed, or further INT
may be lost.Reserved0This bit must always be 0. Improper operation
may result by writing a 1 to this location.0DisableD3Key release enable1Enable1Reserved0This bit must always be 0. Improper operation
results by writing a 1 to this location.0DisableD1Wakeup1Key press wakeup enable1
0I2C timeout enabledD0Timeout enable1I2C timeout disabled0
Table 4. Configuration Register Format (0x01)
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
Debounce Register (0x02)The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0 through D4 set the
debounce time in increments of 1ms starting at 9ms
and ending at 40ms (Table 5). Bits D5 through D7 set
which of the GPO ports is enabled. Note the GPO ports
can be enabled only in the combinations shown in
Table 5, from all disabled to all enabled.
REGISTER DATAD6D5D4D3D2D1D0REGISTER DESCRIPTION
PORTS ENABLEDEBOUNCE TIMEDebounce time is 9msXXX00000
Debounce time is 10msXXX00001
Debounce time is 11msXXX00010
Debounce time is 12msXXX00011
Debounce time is 37msXXX11100
Debounce time is 38msXXX11101
Debounce time is 39msXXX11110
Debounce time is 40msXXX11111
GPO ports disabled (full key-scan functionality)000XXXXX
GPO port 7 enabled001XXXXX
GPO ports 7 and 6 enabled010XXXXX
GPO ports 7, 6, and 5 enabled011XXXXX
GPO ports 7, 6, 5, and 4 enabled100XXXXX
GPO ports 7, 6, 5, 4, and 3 enabled101XXXXX
GPO ports 7, 6, 5, 4, 3, and 2 enabled11XXXXXX
Power-up default setting11111111
Table 5. Debounce Register Format (0x02)
