MAX7315AEE+T ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionApplications Pin ConfigurationsLCD Backlights Keypad BacklightsTOP VIEWLED Status Indication RGB LE ..
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MAX7315AUE+ ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionELECTRICAL CHARACTERISTICS(Typical Operating Circuit, V+ = 2V to 3.6V, T = T to T , unless otherwis ..
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MAX7315AEE+-MAX7315AEE+T-MAX7315ATE-MAX7315ATE+T-MAX7315AUE+-MAX7315AUE-T
8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion Protection
General DescriptionThe MAX7315 I2C-/SMBus-compatible serial interfaced
peripheral provides microprocessors with 8 I/O ports.
Each I/O port can be individually configured as either an
open-drain current-sinking output rated at 50mA at 5.5V,
or a logic input with transition detection. A ninth port can
be used for transition detection interrupt or as a general-
purpose output. The outputs are capable of directly dri-
ving LEDs, or providing logic outputs with external
resistive pullup up to 5.5V.
PWM current drive is integrated with 8 bits of control.
Four bits are global control and apply to all LED outputs
to provide coarse adjustment of current from fully off to
fully on in 14 intensity steps. Each output then has indi-
vidual 4-bit control, which further divides the globally
set current into 16 more steps. Alternatively, the current
control can be configured as a single 8-bit control that
sets all outputs at once.
The MAX7315 is pin and software compatible with the
PCA9534 and PCA9554(A).
Each output has independent blink timing with two blink
phases. All LEDs can be individually set to be on or off
during either blink phase, or to ignore the blink control.
The blink period is controlled by a register.
The MAX7315 supports hot insertion. All port pins, the INT
output, SDA, SCL, and the slave address inputs ADO-2
remain high impedance in power-down (V+ = 0V) with up
to 6V asserted upon them.
The MAX7315 is controlled through the 2-wire I2C/SMBus
serial interface, and can be configured to one of 64 I2C
addresses.
Applications
Features400kbps, 2-Wire Serial Interface, 5.5V Tolerant2V to 3.6V OperationOverall 8-Bit PWM LED Intensity Control
Global 16-Step Intensity Control
Plus Individual 16-Step Intensity ControlAutomatic Two-Phase LED Blinking50mA Maximum Port Output CurrentSupports Hot InsertionOutputs Are 5.5V-Rated Open DrainInputs Are Overvoltage Protected to 5.5VTransition Detection with Interrupt OutputLow Standby Current (1.2µA typ; 3.3µA max)Tiny 3mm x 3mm, Thin QFN Package-40°C to +125°C Temperature RangeAll Ports Can Be Configured as Inputs or Outputs
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection11109
INT/O8P7P6
GND
16
15
14
13
AD1
ADO34
AD2P1P2
SDA
SCL
THIN QFNTOP VIEW
MAX7315ATE
Pin Configurations19-3056; Rev 3; 1/05
EVALUATION
KIT
AVAILABLE
Ordering Information
PARTTEMP
RANGE
PIN-
PACKAGE
TOP
MARK
PKG
CODEMAX7315ATE-40°Cto +125°C
16 Thin QFN
3mm x 3mm0.8mm
AAUT1633-4
MAX7315AEE-40°Cto +125°C16 QSOP——
MAX 7315AU E-40°Cto +125°C16 TSSOP——
Pin Configurations continued at end of data sheet.
LCD Backlights
LED Status Indication
Portable Equipment
Laptop Computers
Keypad Backlights
RGB LED Drivers
Cellular Phones
Typical Application Circuit appears at end of data sheet.
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with respect to GND)
V+.............................................................................-0.3V to +4V
SCL, SDA, AD0, AD1, AD2, P0–P7..........................-0.3V to +6V
INT/O8 .....................................................................-0.3V to +8V
DC Current on P0–P7, INT/O8............................................55mA
DC Current on SDA.............................................................10mA
Maximum GND Current....................................................190mA
Continuous Power Dissipation (TA=+70°C)
16-Pin TSSOP (derate 9.4mW/°C over +70°C)............754mW
16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW
16-Pin QFN (derate 14.7mW/°C over +70°C)............1176mW
Operating Temperature Range (TMINto TMAX)-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(Typical Operating Circuit, V+ = 2V to 3.6V, TA=TMINto TMAX,unless otherwise noted. Typical values are at V+ = 3.3V, TA=+25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Supply VoltageV+23.6V
Output Load External Supply
VoltageVEXT05.5V=+25°C1.22.3=-40°C to +85°C2.6Standby Current
(Interface Idle, PWM Disabled)I+
SCLand SDAat V +;other
digital inp uts at V +or GN D;
PWM intensi tycontr ol disab led TA=TMIN to TMAX3.3=+25°C712.1=-40°C to +85°C13.5Supply Current
(Interface Idle, PWM Enabled)I+
SCLand SDAat V +;other
digital inp uts at V +or GN D;
PWM intensi tycontr ol enab led TA=TMIN to TMAX14.4=+25°C4076=-40°C to +85°C78
Supply Current
(Interface Running, PWM
Disabled)
fSCL = 400kHz; other digital
inputs at V+ or GND; PWM
intensity control disabledTA=TMIN to TMAX80=+25°C51110=-40°C to +85°C117
Supply Current
(Interface Running, PWM
Enabled)
fSCL = 400kHz; other digital
inputs at V+ or GND; PWM
intensity control enabledTA=TMIN to TMAX122
Input High Voltage
SDA, SCL, AD0, AD1, AD2,
P0–P7
VIH0.7 ✕V
Input Low Voltage
SDA, SCL, AD0, AD1, AD2,
P0–P7
VIL0.3 ✕V
Input Leakage Current
SDA, SCL, AD0, AD1, AD2,
P0–P7
IIH,IILInput = GND or V+-0.2+0.2µA
Input Capacitance
SDA, SCL, AD0, AD1, AD2,
8pF
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
ELECTRICAL CHARACTERISTICS (continued)(Typical Operating Circuit, V+ = 2V to 3.6V, TA=TMINto TMAX,unless otherwise noted. Typical values are at V+ = 3.3V, TA=+25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS=+25°C0.150.25=-40°C to +85°C0.29V+ = 2V, ISINK = 20mA=TMIN to TMAX0.31=+25°C0.130.22=-40°C to +85°C0.25V+ = 2.5V, ISINK = 20mA=TMIN to TMAX0.27=+25°C0.120.22=-40°C to +85°C0.23
Output Low Voltage
P0–P7, INT/O8VOL
V+ = 3.3V, ISINK = 20mA=TMIN to TMAX0.25
Output Low-Voltage SDAVOLSDAISINK = 6mA0.4V
PWM Clock FrequencyfPWM32kHz
TIMING CHARACTERISTICS(Typical Operating Circuit, V+ = 2V to 3.6V, TA=TMINto TMAX,unless otherwise noted. Typical values are at V+ = 3.3V, TA=+25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSerial Clock FrequencyfSCL400kHz
Bus Free Time Between a STOP and a START
ConditiontBUF1.3µs
Hold Time, Repeated START ConditiontHD, STA0.6µs
Repeated START Condition Setup TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD, DAT(Note 2)0.9µs
Data Setup TimetSU, DAT180ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.7µs
Rise Time of Both SDA and SCL Signals, ReceivingtR(Notes 3, 4)200 +
0.1Cb300ns
Fall Time of Both SDA and SCL Signals, ReceivingtF(Notes 3, 4)200 +
0.1Cb300ns
Fall Time of SDA TransmittingtF.TX(Notes 3, 5)200 +
0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Note 6)50ns
Capacitive Load for Each Bus LineCb(Note 3)400pF
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
TIMING CHARACTERISTICS (continued)(Typical Operating Circuit, V+ = 2V to 3.6V, TA=TMINtoTMAX,unless otherwise noted. Typical values are at V+ = 3.3V, TA=+25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInterrupt ValidtIVFigure 106.5µs
Interrupt ResettIRFigure 101µs
Output Data ValidtDVFigure 105µs
Input Data Setup TimetDSFigure 10100ns
Input Data Hold TimetDHFigure 101µs
Note 1:All parameters tested at TA=+25°C. Specifications over temperature are guaranteed by design.
Note 2:Amaster device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 3:Guaranteed by design.
Note 4:Cb=total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 5:ISINK≤6mA. Cb=total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 6:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
STANDBY CURRENT vs. TEMPERATUREMAX7315
toc01
STANDBY
CURRENT
V+=3.6V
PWM ENABLED=2.7V
PWM ENABLED=2V
PWM DISABLED
V+ = 2.7V
PWM DISABLED
V+=3.6V
PWM
DISABLED
V+=2V
PWM ENABLED
SUPPLY CURRENT vs. TEMPERATURE
(PWM DISABLED; fSCL =400kHz)MAX7315
toc02
SUPPLY
CURRENT
V+=3.6V
V+=2.7V
V+ = 2V
SUPPLY CURRENT vs. TEMPERATURE
(PWM ENABLED; fSCL =400kHz)MAX7315
toc03
SUPPLY
CURRENT
V+ = 3.6V
V+=2.7V
V+=2V
__________________________________________Typical Operating Characteristics(TA=+25°C, unless otherwise noted.)
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
PORT OUTPUT LOW VOLTAGE WITH 50mA
LOAD CURRENT vs. TEMPERATUREPORT
OUTPUT
LOW
VOLTAGE
(V)
MAX7315
toc04
TEMPERATURE (°C)
V+=3.6V=2.7V
V+ = 2V
PORT OUTPUT LOW VOLTAGE WITH 20mA
LOAD CURRENT vs. TEMPERATUREMAX7315
toc05
TEMPERATURE (°C)
PORT
OUTPUT
LOW
VOLTAGE
(V)
ALL OUTPUTS LOADED
V+ = 3.6VV+=2.7V
V+=2V
PWM CLOCK FREQUENCY
vs. TEMPERATUREMAX7315
toc06
TEMPERATURE (°C)
PWM
CLOCK
FREQUENCY
-40125=3.6V
V+=2VV+=2.7V
NORMALIZED TO V+ = 3.3V, TA=+25°C
SCOPE SHOT OF 2 OUTPUT PORTS MAX7315 toc07
2ms/div
OUTPUT 1,
2V/div
OUTPUT 2,
2V/div
MASTER INTENSITY SET TO 1/15
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16
OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 15/16
SCOPE SHOT OF 2 OUTPUT PORTSMAX7315 toc08
2ms/div
OUTPUT 1,
2V/div
OUTPUT 2,
2V/div
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16
MASTER INTENSITY SET TO 14/15
OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 14/15
SINK CURRENT vs. VOLMAX7315
toc09
SINK CURRENT (mA)
(V)40302010
V+=2V
V+ = 2.7V
ONLY ONE OUTPUT LOADED
V+ = 3.3V
V+=3.6V
Typical Operating Characteristics (continued)(TA=+25°C, unless otherwise noted.)
MAX7315
Functional OverviewThe MAX7315 is a general-purpose input/output (GPIO)
peripheral that provides eight I/O ports, P0–P7, con-
trolled through an I2C-compatible serial interface. A 9th
output-only port, INT/O8, can be configured as an inter-
supply voltage. The MAX7315 is rated for a ground cur-
rent of 190mA, allowing all nine outputs to sink 20mA at
the same time. Figure 1 shows the output structure of
the MAX7315. The ports default to inputs on power-up.
Port Inputs and Transition Detection
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
PIN
QSOP/TSSOPQFN
NAMEFUNCTION1, 2, 315, 16, 1AD0, AD1,
AD2
Address Inputs. Sets device slave address. Connect to either GND, V+,
SCL, or SDA to give 64 logic combinations. See Table 1.
4–7, 9–122–5, 7–10P0–P7Input/Output Ports. P0–P7 are open-drain I/Os rated at 5.5V, 50mA.6GNDGround. Do not sink more than 190mA into the GND pin.11INT/O8Output Port. Open-drain output rated at 7.0V, 50mA. Configurable as
interrupt output or general-purpose output.12SCLI2C-Compatible Serial Clock Input13SDAI2C-Compatible Serial Data I/O14V+Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic
capacitorPADExposed padExposed Pad on Package Underside. Connect to GND.
Pin DescriptionFigure 1. Simplified Schematic of I/O Ports
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
WRITE PULSE
READ PULSE
CONFIGURATION
REGISTER
INPUT PORT
REGISTER
OUTPUT
PORT
REGISTER
OUTPUT PORT
REGISTER DATA
I/O PIN
GND
INPUT PORT
REGISTER DATA
TO INT
ports register latches the current-input logic level of the
affected eight ports. Transition detection allows all ports
configured as inputs to be monitored for changes in
their logic status. The action of reading the input ports
register samples the corresponding 8 port bits’ input
condition. This sample is continuously compared with
the actual input conditions. A detected change in input
condition causes the INT/O8 interrupt output to go low,
if configured as an interrupt output. The interrupt is
cleared either automatically if the changed input returns
to its original state, or when the input ports register is
read.
The INT/O8 pin can be configured as either an interrupt
output or as a 9th output port with the same static or
blink controls as the other eight ports (Table 4).
Port Output Control and LED BlinkingThe blink phase 0 register sets the output logic levels of
the eight ports P0–P7 (Table 8). This register controls
the port outputs if the blink function is disabled. A dupli-
cate register, the blink phase 1 register, is also used if
the blink function is enabled (Table 9). In blink mode,
the port outputs can be flipped between using the blink
phase 0 register and the blink phase 1 register using
software control (the blink flip flag in the configuration
register) (Table 4).
PWM Intensity ControlThe MAX7315 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity con-
trol. PWM intensity control can be enabled on an out-
put-by-output basis, allowing the MAX7315 to provide
any mix of PWM LED drives and glitch-free logic out-
puts (Table 10). PWM can be disabled entirely, in which
case all output ports are static and the MAX7315 oper-
ating current is lowest because the internal oscillator is
turned off.
PWM intensity control uses a 4-bit master control and 4
bits of individual control per output (Tables 13, 14). The
4-bit master control provides 16 levels of overall intensi-
ty control, which applies to all PWM-enabled output
ports. The master control sets the maximum pulse width
from 1/15 to 15/15 of the PWM time period. The individ-
ual settings comprise a 4-bit number further reducing
the duty cycle to be from 1/16 to 15/16 of the time win-
dow set by the master control.
For applications requiring the same PWM setting for all
output ports, a single global PWM control can be used
instead of all the individual controls to simplify the con-
trol software and provide 240 steps of intensity control
(Tables 10 and 13).
Standby ModeWhen the serial interface is idle and the PWM intensity
control is unused, the MAX7315 automatically enters
standby mode. If the PWM intensity control is used, the
operating current is slightly higher because the internal
PWM oscillator is running. When the serial interface is
active, the operating current also increases because
the MAX7315, like all I2Cslaves, has to monitor every
transmission.
Serial Interface
Serial AddressingThe MAX7315 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7315 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7315 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7315 SCL line operates
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion ProtectionSCL
SDA tF
tBUF
START
STOP
REPEATED START CONDITION START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT tLOW
tHIGH
tHD,STA
MAX7315only as an input. A pullup resistor, typically 4.7kΩ,is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7315
7-bit slave address plus R/Wbit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop ConditionsBoth SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure3).
Bit TransferOne data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
AcknowledgeThe acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7315, the device gen-
erates the acknowledge bit because the MAX7315 is
the recipient. When the MAX7315 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave AddressThe MAX7315 has a 7-bit long slave address (Figure6).
The eighth bit following the 7-bit slave address is the
R/Wbit. The R/Wbit is low for a write command, high
for a read command.
The slave address bits A6 through A0 are selected by
the address inputs AD0, AD1, and AD2. These pins can
be connected to GND, V+, SDA, or SCL. The MAX7315
has 64 possible slave addresses (Table 1) and, there-
fore, a maximum of 64 MAX7315 devices can be con-
trolled independently from the same interface.
Message Format for Writing the MAX7315write to the MAX7315 comprises the transmission of
the MAX7315’s slave address with the R/Wbit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The command
byte determines which register of the MAX7315 is to be
written to by the next byte, if received (Table 2). If a
STOP condition is detected after the command byte is
received, then the MAX7315 takes no further action
beyond storing the command byte.
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion ProtectionFigure 3. Start and Stop Conditions
SDA
SCL
START
CONDITION
STOP
CONDITIONP
Figure 4. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 5. Acknowledge
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGESTART
CONDITION
SDA BY
RECEIVER289
SDA
MSBLSB
ACKA4A1A6A3A0A2R/W
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
Table 1. MAX7315 I2CSlave Address Map
DEVICE ADDRESSPIN AD2PIN AD1PIN AD0A5A4A3A2A1A0GNDSCLGND0010000
GNDSCLV+0010001
GNDSDAGND0010010
GNDSDAV+0010011SCLGND0010100SCLV+0010101SDAGND0010110SDAV+0010111
GNDSCLSCL0011000
GNDSCLSDA0011001
GNDSDASCL0011010
GNDSDASDA0011011SCLSCL0011100SCLSDA0011101SDASCL0011110SDASDA0011111
GNDGNDGND0100000
GNDGNDV+0100001
GNDV+GND0100010
GNDV+V+0100011GNDGND0100100GNDV+0100101V+GND0100110V+V+0100111
GNDGNDSCL0101000
GNDGNDSDA0101001
GNDV+SCL0101010
GNDV+SDA0101011GNDSCL0101100GNDSDA0101101V+SCL0101110V+SDA0101111
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
Table 1. MAX7315 I2CSlave Address Map (continued)
DEVICE ADDRESSPIN AD2PIN AD1PIN AD0A5A4A3A2A1A0SCLSCLGND1010000
SCLSCLV+1010001
SCLSDAGND1010010
SCLSDAV+1010011
SDASCLGND1010100
SDASCLV+1010101
SDASDAGND1010110
SDASDAV+1010111
SCLSCLSCL1011000
SCLSCLSDA1011001
SCLSDASCL1011010
SCLSDASDA1011011
SDASCLSCL1011100
SDASCLSDA1011101
SDASDASCL1011110
SDASDASDA1011111
SCLGNDGND1100000
SCLGNDV+1100001
SCLV+GND1100010
SCLV+V+1100011
SDAGNDGND1100100
SDAGNDV+1100101
SDAV+GND1100110
SDAV+V+1100111
SCLGNDSCL1101000
SCLGNDSDA1101001
SCLV+SCL1101010
SCLV+SDA1101011
SDAGNDSCL1101100
SDAGNDSDA1101101
SDAV+SCL1101110
SDAV+SDA1101111
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX7315 selected by the command byte (Figure
8). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7315 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 register or blink phase 1 register) is given in
Figure 10.
Message Format for ReadingThe MAX7315 is read using the MAX7315’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write (Table 2). Thus, a read is initiated by first configur-
tive bytes from the MAX7315 with the first data byte
being read from the register addressed by the initial-
ized command byte. When performing read-after-write
verification, remember to reset the command byte’s
address because the stored command byte address
has been autoincremented after the write (Table 2). A
diagram of a read from the input ports register is shown
in Figure 10reflecting the states of the ports.
Operation with Multiple MastersIf the MAX7315 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7315 should
use a repeated start between the write, which sets the
MAX7315’s address pointer, and the read(s) that takes
the data from the location(s) (Table 2). This is because it
is possible for master 2 to take over the bus after masterhas set up the MAX7315’s address pointer but before
master 1 has read the data. If master 2 subsequently
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion ProtectionFigure 8. Command and Single Data Byte ReceivedAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
BYTE
AUTOINCREMENT MEMORY ADDRESS
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6
ACKNOWLEDGE FROM MAX7315ACKNOWLEDGE FROM MAX7315
ACKNOWLEDGE FROM MAX7315
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7315'S REGISTERS
R/W
Figure 9. n Data Bytes ReceivedAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
BYTES
AUTOINCREMENT MEMORY ADDRESS
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6
ACKNOWLEDGE FROM MAX7315ACKNOWLEDGE FROM MAX7315
ACKNOWLEDGE FROM MAX7315
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7315'S REGISTERS
R/W
Figure 7. Command Byte ReceivedAP0SLAVE ADDRESSCOMMAND BYTE
ACKNOWLEDGE FROM MAX7315
D15D14D13D12D11D10D9D8COMMAND BYTE IS STORED ON RECEIPT OF
STOP CONDITION
ACKNOWLEDGE FROM MAX7315R/W
MAX7315
Command Address AutoincrementingThe command address stored in the MAX7315 circu-
lates around grouped register functions after each data
byte is written or read (Table 2).
Device Resetadevice reset input is needed, consider the
MAX7316. The MAX7316 includes a RSTinput, which
clears any transaction to or from the MAX7316 on the
serial interface and configures the internal registers to
the same state as a power-up reset.
Detailed Description
Initial Power-UpOn power-up all control registers are reset and the
MAX7315 enters standby mode (Table 3). Power-up
status makes all ports into inputs and disables both the
PWM oscillator and blink functionality.
Configuration RegisterThe configuration register is used to configure the PWM
intensity mode, interrupt, and blink behavior, operate
the INT/O8 output, and read back the interrupt status
(Table 4).
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion ProtectionFigure 10. Read, Write, and Interrupt Timing Diagrams
SLAVE ADDRESS23456789A6A5A4A3A2A1A00A0000000
COMMAND BYTEAAP
START CONDITIONACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM SLAVESTOP
CONDITION
P7–P0DATA1 VALIDDATA2 VALID
SLAVE ADDRESS23456789A6A5A4A3A2A1A01A
COMMAND BYTE
ANA
START CONDITIONACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM MASTER
P7–P0
STOP CONDITION
NO ACKNOWLEDGE FROM
MASTER
DATA2DATA3
tDVtDV
SLAVE ADDRESS23456789A6A5A4A3A2A1A01A
COMMAND BYTE
ANA
START CONDITIONACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM MASTER
P7–P0
STOP CONDITION
NO ACKNOWLEDGE FROM
MASTER
DATA1DATA2DATA3DATA4
tDHtDS
DATA1
tIVtIRtIRtIV
SCL
SDA
SCL
SDA
SCL
SDA
WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)
READ FROM INPUT PORTS REGISTERS
INTERRUPT VALID/RESETR/W
MSBLSBDATA1
MSBLSBDATA1
MSBLSBDATA2MSBLSBDATA4
MSBLSBDATA4
MSBLSBDATA2
R/W
R/W
INT
Ports ConfigurationThe 8 I/O ports P0 through P7 can be configured to any
combination of inputs and outputs using the ports con-
figuration register (Table 5). The INT/O8 output can also
be configured as an extra general-purpose output
using the configuration register (Table 4).
Input PortsThe input ports register is read only (Table 6). It reflect
the incoming logic levels of the ports, regardless of
whether the port is defined as an input or an output by
the ports configuration register. Reading the input ports
register latches the current-input logic level of the
affected eight ports. A write to the input ports register is
ignored.
Transition DetectionAll ports configured as inputs are always monitored for
changes in their logic status. The action of reading the
input ports register or writing to the configuration regis-
ter samples the corresponding 8 port bits’ input condi-
tion (Tables 4, 6). This sample is continuously
compared with the actual input conditions. A detected
change in input condition causes an interrupt condition.
The interrupt is cleared either automatically if the
changed input returns to its original state, or when the
input ports register is read, updating the compared
data (Figure 10). Randomly changing a port from an
output to an input may cause a false interrupt to occur if
the state of the input does not match the content of the
input ports register. The interrupt status is available as
the interrupt flag INTin the configuration register (Table
4).
ization, so if all the ports are pulled to valid logic levels
at that time an interrupt does not occur at power-up.
INT/O8 Output
The INT/O8 output pin can be configured as either the
INToutput that reflects the interrupt flag logic state or asgeneral-purpose output O8. When used as a general-
purpose output, the INT/O8 pin has the same blink and
PWM intensity control capabilities as the other ports.
Set the interrupt enable I bit in the configuration register
to configure INT/O8 as the INToutput (Table 4). Clear
interrupt enable to configure INT/O8 as the O8. O8
logic state is set by the 2 bits O1 and O0 in the configu-
ration register. O8 follows the rules for blinking selected
by the blink enable flag E in the configuration register. If
blinking is disabled, then interrupt output control O0
alone sets the logic state of the INT/O8 pin. If blinking is
enabled, then both interrupt output controls O0 and O1
set the logic state of the INT/O8 pin according to the
blink phase. PWM intensity control for O8 is set by the 4
global intensity bits in the master, O8 intensity register
(Table 13).
Blink ModeIn blink mode, the output ports can be flipped between
using either the blink phase 0 register or the blink phaseregister. Flip control is by software control (the blink flip
flag B in the configuration register) (Table 4). If hardware
flip control is needed, consider the MAX7316, which
includes a BLINK input, as well as software control.
The blink function can be used for LED effects by pro-
gramming different display patterns in the two sets of
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
Table 2. Register Address Map
REGISTERADDRESS CODE
(HEX)
AUTOINCREMENT
ADDRESSRead input ports0x000x00 (no change)
Blink phase 0 outputs0x010x01 (no change)
Ports configuration0x030x03 (no change)
Blink phase 1 outputs0x090x09 (no change)
Master, O8 intensity0x0E0x0E (no change)
Configuration0x0F0x0F (no change)
Outputs intensity P1, P00x100x11
Outputs intensity P3, P20x110x12
Outputs intensity P5, P40x120x13
Outputs intensity P7, P60x130x10
