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MAX7314AEG+-MAX7314ATG+-MAX7314ATG+T
18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion Protection
General DescriptionThe MAX7314 I2C-compatible serial interfaced periph-
eral provides microprocessors with 16 I/O ports plus one
output-only port and one input-only port. Each I/O port
can be individually configured as either an open-drain
current-sinking output rated at 50mA and 5.5V, or a logic
input with transition detection. The output-only port can
be assigned as an interrupt output for transition detec-
tion. The outputs are capable of driving LEDs, or provid-
ing logic outputs with external resistive pullup up to 5.5V.
Eight-bit PWM current control is built in for all 17 output
ports. A 4-bit global control applies to all LED outputs
and provides coarse adjustment of current from fully off
to fully on with 14 intensity steps in between. Each out-
put has an individual 4-bit control, which further divides
the globally set current into 16 more steps.
Alternatively, the current control can be configured as a
single 8-bit control that sets all outputs at once.
Each output has independent blink timing with two blink
phases. All LEDs can be individually set to be on or off
during either blink phase, or to ignore the blink control.
The blink period is controlled by a clock input (up to 1kHz)
on BLINK or by a register. The BLINK input can also be
used as a logic control to turn the LEDs on and off, or as a
general-purpose input.
The MAX7314 supports hot insertion. All port pins, the
INToutput, SDA, SCL, RST, BLINK, and the slave
address input ADO remain high impedance in power-
down (V+ = 0V) with up to 6V asserted upon them.
The MAX7314 is controlled through a 2-wire serial inter-
face, and uses four-level logic to allow four I2C
addresses from only one select pin.
ApplicationsLCD Backlights
LED Status Indication
Relay Drivers
Keypad Backlights
RGB LED Drivers
System I/O Ports
Features400kbps, 2-Wire Serial Interface, 5.5V Tolerant2V to 3.6V OperationOverall 8-Bit PWM LED Intensity Control
Global 16-Step Intensity Control
Individual 16-Step Intensity Controls2-Phase LED Blinking50mA Maximum Port Output CurrentSupports Hot InsertionOutputs are 5.5V-Rated Open DrainInputs are Overvoltage Protected to 5.5VTransition Detection with Interrupt Output1.2µA (typ), 3.6µA (max) Operating CurrentSmall 4mm x 4mm, Thin QFN Package-40°C to +125°C Temperature Range
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion ProtectionMAX7314
P10
3.3V
SDASDA
AD0
3.3V5V
P11
P12
P13
P14
P15
SCLSCL
BLINKI/O
RSTI/O
OUTPUT
OUTPUT
GND
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
0.047μF
INTINT/O16
Typical Application Circuit19-3170; Rev 4; 4/05
EVALUATION KIT
AVAILABLE
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX7314ATG-40°C to +125°C
24 Thin QFN
4mm x 4mm
x 0.8mm
T2444-4
MAX7314AEG-40°C to +125°C24 QSOP—
Pin Configurations continued at end of data sheet.
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with respect to GND)
V+.............................................................................-0.3V to +4V
SCL, SDA, AD0, BLINK, RST, P0–P15.....................-0.3V to +6V
INT/O16 ...................................................................-0.3V to +8V
DC Current on P0–P15, INT/O16........................................55mA
DC Current on SDA.............................................................10mA
Maximum GND Current....................................................350mA
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C over +70°C)..............761mW
24-Pin QFN (derate 20.8mW/°C over +70°C)............1666mW
Operating Temperature Range
(TMINto TMAX).............................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Supply VoltageV+23.6V
Output Load External Supply
VoltageVEXT05.5V
TA = +25°C1.22.3
TA = -40°C to +85°C2.8Standby Current
(Interface Idle, PWM Disabled)I+C L and S D A at V + ; other i g i tal i np uts at V + or GN D ;WM i ntensi ty contr ol d i sab l ed TA = TMIN to TMAX3.6
TA = +25°C8.515.1
TA = -40°C to +85°C16.5Supply Current
(Interface Idle, PWM Enabled)I+C L and S D A at V + ; other i g i tal i np uts at V + or GN D ;WM i ntensi ty contr ol d i sab l ed TA = TMIN to TMAX17.2
TA = +25°C5095.3
TA = -40°C to +85°C99.2
Supply Current
(Interface Running, PWM
Disabled)
fSCL = 400kHz; other digital
inputs at V+ or GND; PWM
intensity control enabledTA = TMIN to TMAX102.4
TA = +25°C57110.2
TA = -40°C to +85°C117.4
Supply Current
(Interface Running, PWM
Enabled)
fSCL = 400kHz; other digital
inputs at V+ or GND; PWM
intensity control enabledTA = TMIN to TMAX122.1
Input High Voltage
SDA, SCL, AD0, BLINK, P0–P15VIH0.7 xV
Input Low Voltage
SDA, SCL, AD0, BLINK, P0–P15VIL0.3 xV
Input Leakage Current
SDA, SCL, AD0, BLINK, P0–P15IIH, IIL0 ≤ input voltage ≤ 5.5V-0.2+0.2µA
Input Capacitance
SDA, SCL, AD0, BLINK, P0–P158pF
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
ELECTRICAL CHARACTERISTICS (continued)(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA= + 25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSTA = +25°C0.150.26
TA = -40°C to +85°C0.3V+ = 2V, ISINK = 20mA
TA = TMIN to TMAX0.32
TA = +25°C0.130.23
TA = -40°C to +85°C0.26V+ = 2.5V, ISINK = 20mA
TA = TMIN to TMAX0.28
TA = +25°C0.120.23
TA = -40°C to +85°C0.24
Output Low Voltage
P0–P15, INT/O16VOL
V+ = 3.3V, ISINK = 20mA
TA = TMIN to TMAX0.26
Output Low-Voltage SDAVOLSDAISINK = 6mA0.4V
PWM Clock FrequencyfPWM32kHz
TIMING CHARACTERISTICS(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSerial Clock FrequencyfSCL400kHz
Bus Free Time Between a STOP and a START
ConditiontBUF1.3µs
Hold Time, Repeated START ConditiontHD, STA0.6µs
Repeated START Condition Setup TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD, DAT(Note 2)0.9µs
Data Setup TimetSU, DAT180ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.7µs
Rise Time of Both SDA and SCL Signals, ReceivingtR(Notes 3, 4)20 +
0.1Cb300ns
Fall Time of Both SDA and SCL Signals, ReceivingtF(Notes 3, 4)20 +
0.1Cb300ns
Fall Time of SDA TransmittingtF.TX(Notes 3, 5)20 +
0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Note 6)50ns
Capacitive Load for Each Bus LineCb(Note 3)400pF
RST Pulse WidthtW1µs
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
TIMING CHARACTERISTICS (continued)(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInterrupt ValidtIVFigure 106.5µs
Interrupt ResettIRFigure 101µs
Output Data ValidtDVFigure 105µs
Input Data Set-Up TimetDSFigure 10100ns
Input Data Hold TimetDHFigure 101µs
Note 1:All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 3:Guaranteed by design.
Note 4:Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 5:ISINK≤6mA. Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 6:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
STANDBY CURRENT vs. TEMPERATUREMAX7314 toc01
TEMPERATURE (°C)
STANDBY CURRENT (
V+ = 3.6V
PWM ENABLED
V+ = 2.7V
PWM ENABLED
V+ = 2V
PWM DISABLED
V+ = 2.7V
PWM DISABLED
V+ = 3.6V
PWM
DISABLED
V+ = 2V
PWM ENABLED
SUPPLY CURRENT vs. TEMPERATURE
(PWM DISABLED; fSCL = 400kHz)MAX7314 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (
V+ = 3.6V
V+ = 2.7V
V+ = 2V
SUPPLY CURRENT vs. TEMPERATURE
(PWM ENABLED; fSCL = 400kHz)MAX7314 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (
V+ = 3.6V
V+ = 2.7V
V+ = 2V
__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
PORT OUTPUT LOW VOLTAGE WITH 50mA
LOAD CURRENT vs. TEMPERATUREPORT OUTPUT LOW VOLTAGE V
(V)
MAX7314 toc04
TEMPERATURE (°C)
V+ = 3.6V
V+ = 2.7V
V+ = 2V
PORT OUTPUT LOW VOLTAGE WITH 20mA
LOAD CURRENT vs. TEMPERATUREMAX7314 toc05
TEMPERATURE (°C)
PORT OUTPUT LOW VOLTAGE V
(V)
ALL OUTPUTS LOADED
V+ = 3.6VV+ = 2.7V
V+ = 2V
PWM CLOCK FREQUENCY
vs. TEMPERATUREMAX7314 toc06
TEMPERATURE (°C)
PWM CLOCK FREQUENCY (kHz)
V+ = 3.6V
V+ = 2VV+ = 2.7V
NORMALIZED TO V+ = 3.3V, TA = +25°C
SCOPE SHOT OF 2 OUTPUT PORTS MAX7314 toc07
2ms/div
OUTPUT 1,
2V/div
OUTPUT 2,
2V/div
MASTER INTENSITY SET TO 1/15
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16
OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 15/16
SCOPE SHOT OF 2 OUTPUT PORTSMAX7314 toc08
2ms/div
OUTPUT 1
2V/div
OUTPUT 2
2V/div
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16
MASTER INTENSITY SET TO 14/15
OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 14/15
MAX7314 toc09
SINK CURRENT vs. VOLSINK CURRENT (mA)
(V)40302010
V+ = 2V
V+ = 2.7V
ONLY ONE OUTPUT LOADED
V+ = 3.3V
V+ = 3.6V
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX7314
Functional OverviewThe MAX7314 is a general-purpose input/output (GPIO)
peripheral that provides 16 I/O ports, P0–P15, con-
trolled through an I2C-compatible serial interface. A
17th output-only port, INT/O16, can be configured as
an interrupt output or as a general-purpose output port.
All output ports sink loads up to 50mA connected to
external supplies up to 5.5V, independent of the
MAX7314’s supply voltage. The MAX7314 is rated for a
ground current of 350mA, allowing all 17 outputs to sink
20mA at the same time. Figure 1 shows the output
structure of the MAX7314. The ports default to inputs on
power-up.
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Pin DescriptionFigure 1. Simplified Schematic of I/O Ports
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
WRITE PULSE
READ PULSE
CONFIGURATION
REGISTER
INPUT PORT
REGISTER
OUTPUT
PORT
REGISTER
OUTPUT PORT
REGISTER DATA
I/O PIN
GND
INPUT PORT
REGISTER DATA
TO INT
PIN
QSOPQFNNAMEFUNCTION122INT/O16Output Port. Open-drain output rated at 7V, 50mA. Configurable as interrupt
output or general-purpose output.
223RSTReset Input. Active low clears the 2-wire interface and puts the device in the
same condition as power-up reset.24AD0Address Input. Sets device slave address. Connect to either GND, V+, SCL,
or SDA to give four logic combinations. See Table 1.
4–11, 13–201–8, 10–17P0–P15Input/Output Ports. P0–P15 are open-drain I/Os rated at 5.5V, 50mA.9GNDGround. Do not sink more than 350mA into the GND pin.18BLINKInput Port Configurable as Blink Control or General-Purpose Input19SCLI2C-Compatible Serial Clock Input20SDAI2C-Compatible Serial Data I/O21V+Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic
capacitor.PADExposed PadExposed Pad on Package Underside. Connect to GND.
Port Inputs and Transition DetectionInput ports registers reflect the incoming logic levels of
the port pins, regardless of whether the pin is defined
as an input or an output. Reading an input ports regis-
ter latches the current-input logic level of the affected
eight ports. Transition detection allows all ports config-
ured as inputs to be monitored for changes in their
logic status. The action of reading an input ports regis-
ter samples the corresponding 8 port bits’ input condi-
tion. This sample is continuously compared with the
actual input conditions. A detected change in input
condition causes the INT/O16 interrupt output to go
low, if configured as an interrupt output. The interrupt is
cleared either automatically if the changed input
returns to its original state, or when the appropriate
input ports register is read.
The INT/O16 pin can be configured as either an inter-
rupt output or as a 17th output port with the same static
or blink controls as the other 16 ports (Table 4).
Port Output Control and LED BlinkingThe two blink phase 0 registers set the output logic lev-
els of the 16 ports P0–P15 (Table 8). These registers
control the port outputs if the blink function is disabled.
A duplicate pair of registers, the blink phase 1 registers,
are also used if the blink function is enabled (Table 9).
In blink mode, the port outputs can be flipped between
using the blink phase 0 registers and the blink phase 1
registers using hardware control (the BLINK input)
and/or software control (the blink flip flag in the configu-
ration register) (Table 4). The logic level of the BLINK
input can be read back through the blink status bit in
the configuration register (Table 4). The BLINK input,
therefore, can be used as a general-purpose logic input
(GPI port) if the blink function is not required.
PWM Intensity ControlThe MAX7314 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity control.
PWM intensity control can be enabled on an output-by-
output basis, allowing the MAX7314 to provide any mix
of PWM LED drives and glitch-free logic outputs (Table
10). PWM can be disabled entirely, in which case all out-
put ports are static and the MAX7314 operating current
is lowest because the internal oscillator is turned off.
PWM intensity control uses a 4-bit master control and 4
bits of individual control per output (Tables 13, 14). The
4-bit master control provides 16 levels of overall intensi-
ty control, which applies to all PWM-enabled output
ports. The master control sets the maximum pulse
width from 1/15 to 15/15 of the PWM time period. The
individual settings comprise a 4-bit number, further
reducing the duty cycle to be from 1/16 to 15/16 of the
time window set by the master control.
For applications requiring the same PWM setting for all
output ports, a single global PWM control can be used
instead of all the individual controls to simplify the con-
trol software and provide 240 steps of intensity control
(Tables 10 and 13).
Standby ModeWhen the serial interface is idle and the PWM intensity
control is unused, the MAX7314 automatically enters
standby mode. If the PWM intensity control is used, the
operating current is slightly higher because the internal
PWM oscillator is running. When the serial interface is
active, the operating current also increases because
the MAX7314, like all I2C slaves, has to monitor every
transmission.
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion ProtectionFigure 2. 2-Wire Serial Interface Timing Details
SCL
SDA tF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT tLOW
tHIGH
tHD,STA
MAX7314
Serial Interface
Serial AddressingThe MAX7314 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7314 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7314 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX7314 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7314
7-bit slave address plus R/Wbit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop ConditionsBoth SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit TransferOne data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
AcknowledgeThe acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7314, the device gen-
erates the acknowledge bit because the MAX7314 is
the recipient. When the MAX7314 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave AddressThe MAX7314 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/Wbit. The R/Wbit is low for a write command, high
for a read command.
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion ProtectionFigure 3. Start and Stop Conditions
SDA
SCL
START
CONDITION
STOP
CONDITION
Figure 4. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 5. Acknowledge
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGESTART
CONDITION
SDA BY
RECEIVER89
Figure 6. Slave Address
SDA
SCL
MSBLSB
ACK00A600A2R/W
The second (A5), third (A4), fourth (A3), sixth (A1), and
last (A0) bits of the MAX7314 slave address are always
1, 0, 0, 0, and 0. Slave address bits A6 and A2 are
selected by the address input AD0. AD0 can be con-
nected to GND, V+, SDA, or SCL. The MAX7314 has four
possible slave addresses (Table 1), and therefore a
maximum of four MAX7314 devices can be controlled
independently from the same interface.
Message Format for Writing the MAX7314A write to the MAX7314 comprises the transmission of
the MAX7314’s slave address with the R/Wbit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The com-
mand byte determines which register of the MAX7314
is to be written to by the next byte, if received (Table 2).
If a STOP condition is detected after the command byte
is received, then the MAX7314 takes no further action
beyond storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX7314 selected by the command byte (Figure
8). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7314 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 registers or blink phase 1 registers) is given in
Figure 10.
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 1. MAX7314 Address Map
DEVICE ADDRESSPIN AD0A5A4A3A2A1A0SCL1100000
SDA1100100
GND01000000100100
Figure 8. Command and Single Data Byte ReceivedAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
BYTE
AUTOINCREMENT MEMORY ADDRESS
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6
ACKNOWLEDGE FROM MAX7314ACKNOWLEDGE FROM MAX7314
ACKNOWLEDGE FROM MAX7314
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7314's REGISTERS
R/W
Figure 9. n Data Bytes ReceivedAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
BYTES
AUTOINCREMENT MEMORY ADDRESS
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6
ACKNOWLEDGE FROM MAX7314ACKNOWLEDGE FROM MAX7314
ACKNOWLEDGE FROM MAX7314
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7314's REGISTERS
R/W
Figure 7. Command Byte ReceivedAP0SLAVE ADDRESSCOMMAND BYTE
ACKNOWLEDGE FROM MAX7314
D15D14D13D12D11D10D9D8COMMAND BYTE IS STORED ON RECEIPT OF
STOP CONDITION
ACKNOWLEDGE FROM MAX7314R/W
MAX7314
Message Format for ReadingThe MAX7314 is read using the MAX7314’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write (Table 2). Thus, a read is initiated by first configur-
ing the MAX7314’s command byte by performing a
write (Figure 7). The master can now read n consecu-
tive bytes from the MAX7314 with the first data byte
being read from the register addressed by the initial-
ized command byte. When performing read-after-write
verification, remember to reset the command byte’s
address because the stored command byte address
has been autoincremented after the write (Table 2). A
diagram of a read from the input ports registers is
shown in Figure 10 reflecting the states of the ports.
Operation with Multiple MastersIf the MAX7314 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7314 should
use a repeated start between the write, which sets the
MAX7314’s address pointer, and the read(s) that takes
the data from the location(s) (Table 2). This is because it
is possible for master 2 to take over the bus after master
1 has set up the MAX7314’s address pointer but before
master 1 has read the data. If master 2 subsequently
changes the MAX7314’s address pointer, then master
1’s delayed read can be from an unexpected location.
Command Address AutoincrementingThe command address stored in the MAX7314 circu-
lates around grouped register functions after each data
byte is written or read (Table 2).
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion ProtectionFigure 10. Read, Write, and Interrupt Timing Diagrams
SLAVE ADDRESS23456789A6A5A4A3A2A1A00A0000000
COMMAND BYTEAAP
START CONDITIONACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM SLAVESTOP
CONDITION
P7–P0
P15– P8
DATA1 VALID
DATA2 VALID
SLAVE ADDRESS23456789A6A5A4A3A2A1A01A
COMMAND BYTE
ANA
START CONDITIONACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM MASTER
P7–P0
P15–P8
STOP CONDITION
NO ACKNOWLEDGE FROM
MASTER
DATA2
DATA4DATA3
tDV
tDV
SLAVE ADDRESS23456789A6A5A4A3A2A1A01A
COMMAND BYTE
ANA
START CONDITIONACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM MASTER
P7–P0
P15–P8
STOP CONDITION
NO ACKNOWLEDGE FROM
MASTER
DATA1DATA2DATA3DATA4
DATA6DATA5
tDH
tDS
DATA1
tIVtIRtIRtIV
SCL
SDA
SCL
SDA
SCL
SDA
WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)
READ FROM INPUT PORTS REGISTERS
INTERRUPT VALID/RESETR/W
MSBLSBDATA1
MSBLSBDATA1
MSBLSBDATA2MSBLSBDATA4
MSBLSBDATA6
MSBLSBDATA2
R/W
R/W
INT
Device ResetThe reset input RSTis an active-low input. When taken
low, RSTclears any transaction to or from the MAX7314
on the serial interface and configures the internal regis-
ters to the same state as a power-up reset (Table 3),
which resets all ports as inputs. The MAX7314 then
waits for a START condition on the serial interface.
Detailed Description
Initial Power-UpOn power-up, and whenever the RSTinput is pulled
low, all control registers are reset and the MAX7314
enters standby mode (Table 3). Power-up status makes
all ports into inputs and disables both the PWM oscilla-
tor and blink functionality. RSTcan be used as a hard-
ware shutdown input, which effectively turns off any
LED (or other) loads and puts the device into its lowest
power condition.
Configuration RegisterThe configuration register is used to configure the PWM
intensity mode, interrupt, and blink behavior, operate
the INT/O16 output, and read back the interrupt status
(Table 4).
Ports ConfigurationThe 16 I/O ports P0 through P15 can be configured to
any combination of inputs and outputs using the ports
configuration registers (Table 5). The INT/O16 output
can also be configured as an extra general-purpose
output, and the BLINK input can be configured as an
extra general-purpose input using the configuration
register (Table 4).
Input PortsThe input ports registers are read only (Table 6). They
reflect the incoming logic levels of the ports, regardless of
whether the port is defined as an input or an output by the
ports configuration registers. Reading an input ports reg-
ister latches the current-input logic level of the affected
eight ports. A write to an input ports register is ignored.
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 2. Register Address Map
REGISTERADDRESS CODE
(hex)
AUTOINCREMENT
ADDRESSRead input ports P7–P00x000x01
Read input ports P15–P80x010x00
Blink phase 0 outputs P7–P00x020x03
Blink phase 0 outputs P15–P80x030x02
Ports configuration P7–P00x060x07
Ports configuration P15–P80x070x06
Blink phase 1 outputs P7–P00x0A0x0B
Blink phase 1 outputs P15–P80x0B0x0A
Master, O16 intensity0x0E0x0E (no change)
Configuration0x0F0x0F (no change)
Outputs intensity P1, P00x100x11
Outputs intensity P3, P20x110x12
Outputs intensity P5, P40x120x13
Outputs intensity P7, P60x130x14
Outputs intensity P9, P80x140x15
Outputs intensity P11, P100x150x16
Outputs intensity P13, P120x160x17
Outputs intensity P15, P140x170x10
MAX7314
Transition DetectionAll ports configured as inputs are always monitored for
changes in their logic status. The action of reading an
input ports register or writing to the configuration regis-
ter samples the corresponding 8 port bits’ input condi-
tion (Tables 4, 6). This sample is continuously
compared with the actual input conditions. A detected
change in input condition causes an interrupt condition.
The interrupt is cleared either automatically if the
changed input returns to its original state, or when the
appropriate input ports register is read, updating the
compared data (Figure 10). Randomly changing a port
from an output to an input may cause a false interrupt
to occur if the state of the input does not match the
content of the appropriate input ports register. The
interrupt status is available as the interrupt flag INTin
the configuration register (Table 4).
The input status of all ports is sampled immediately
after power-up as part of the MAX7314’s internal initial-
ization, so if all the ports are pulled to valid logic levels
at that time, an interrupt does not occur at power-up.
INT/O16 Output
The INT/O16 output pin can be configured as either the
INToutput that reflects the interrupt flag logic state or as
a general-purpose output O16. When used as a general-
purpose output, the INT/O16 pin has the same blink and
PWM intensity control capabilities as the other ports.
Set the interrupt enable I bit in the configuration register
to configure INT/O16 as the INToutput (Table 4). Clear
interrupt enable to configure INT/O16 as the O16. The
O16 logic state is set by the 2 bits O1 and O0 in the
configuration register. O16 follows the rules for blinking
selected by the blink enable flag E in the configuration
register. If blinking is disabled, then interrupt output
control O0 alone sets the logic state of the INT/O16 pin.
If blinking is enabled, then both interrupt output con-
trols O0 and O1 set the logic state of the INT/O16 pin
according to the blink phase. PWM intensity control for
O16 is set by the 4 global intensity bits in the master
and O16 intensity register (Table 13).
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 3. Power-Up Configuration
REGISTER DATAREGISTER FUNCTIONPOWER-UP CONDITION
ADDRESS
CODE
(hex)D7D6D5D4D3D2D1D0Blink phase 0 outputs P7–P0High-impedance outputs0x0211111111
Blink phase 0 outputs P15–P8High-impedance outputs0x0311111111
Ports configuration P7–P0Ports P7–P0 are inputs0x0611111111
Ports configuration P15–P8Ports P15–P8 are inputs0x0711111111
Blink phase 1 outputs P7–P0High-impedance outputs0x0A11111111
Blink phase 1 outputs P15–P8High-impedance outputs0x0B11111111
Master, O16 intensityPWM oscillator is disabled;
O16 is static logic output0x0E00001111
Configuration
INT/O16 is interrupt output;
blink is disabled;
global intensity is enabled
0x0F00001100
Outputs intensity P1, P0P1, P0 are static logic outputs0x1011111111
Outputs Intensity P3, P2P3, P2 are static logic outputs0x1111111111
Outputs intensity P5, P4P5, P4 are static logic outputs0x1211111111
Outputs intensity P7, P6P7, P6 are static logic outputs0x1311111111
Outputs intensity P9, P8P9, P8 are static logic outputs0x1411111111
Outputs intensity P11, P10P11, P10 are static logic outputs0x1511111111
Outputs intensity P13, P12P13, P12 are static logic outputs0x1611111111
Outputs intensity P15, P14P15, P14 are static logic outputs0x1711111111
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 4. Configuration Register
REGISTER DATAREGISTER
ADDRESS
CODE
(hex)D7D6D5D4D3D2D1D0
CONFIGURATION
R/W0x0F
INTERRUPT
STATUS
BLINK
STATUS
INTERRUPT
OUTPUT
CONTROL
AS GPO
INTERRUPT
ENABLE
GLOBAL
INTENSITY
BLINK FLIP
BLINK
ENABLEWrite device configuration0
Read back device configuration1INT
BLINKO1O0IGBEDisable blink—XXXXXXX
0Enable blink—XXXXXXX
1XXXXXX
01Flip blink register (see text)—XXXXXX
11Disable global intensity control—intensity
is set by registers 0x10–0x17 for ports P0
through P15 when configured as outputs,
and by D3–D0 of register 0x0E for
INT/O16 when INT/O16 pin is configured
as an output portXXXXX
0XX
Enable global intensity control—intensity
for all ports configured as outputs is set
by D3–D0 of register 0x0EXXXXX
1XX
Disable data change interrupt—INT/O16
output is controlled by the O0 and O1 bits—XXXX
0XXX
Enable data change interrupt—INT/O16
output is controlled by port input data
changeXXXX
1XXX
INT/O16 output is low (blink is disabled)—XXX
00XX
0INT/O16 output is high impedance (blink
is disabled)—XXX
10XX
0INT/O16 outp ut i s l ow d ur i ng b l i nk p hase 0—XXX
00XX
1INT/O16 output is high impedance during
blink phase 0—XXX
10XX
1INT/O16 outp ut i s l ow d ur i ng b l i nk p hase 1—XX
0X
0XX
1INT/O16 output is high impedance during
blink phase 1—XX
1X
0XX
1X = Don’t care.
