MAX7300ATL+ ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O ExpanderElectrical Characteristics(Typical Operating Circuit, V = 2.5V to 5.5V, T = T to T , unless otherwi ..
MAX7300ATL+T ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O ExpanderFeaturesThe MAX7300 compact, serial-interfaced, I/O expansion ● 400kbps I2C-Compatible Serial Inter ..
MAX7301AAI+ ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderMAX7301 4-Wire-Interfaced, 2.5V to 5.5V,20-Port and 28-Port I/O Expander
MAX7301AAI+T ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderGeneral Description Beneits and
MAX7301AAX ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderApplicationsWhite GoodsTypical Operating CircuitAutomotiveGaming Machines 3V36 32V+ P4 I/O 4Industr ..
MAX7301AAX ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderFeaturesThe MAX7301 compact, serial-interfaced I/O expander♦ High-Speed 26MHz SPI-/QSPI-™/MICROWIRE ..
MB4M ,MINIATURE GLASS PASSIVATED SINGLE-PHASE BRIDGE RECTIFIERapplications0.205 (5.21)0.179 (4.55)0.195 (4.95)Mechanical Data0.049 (1.24)0.039 (0.99)0.106 (2.70) ..
MB4S ,Bridge RectifiersThermal Characteristics (T = 25°C unless otherwise noted)AParameter Symbol MB2S MB4S MB6S UnitDevic ..
MB4S_NL ,0.5A Bridge RectifierFeatures• Low leakage+ +- +• Surge overload rating:35 amperes peak.~ ~• Ideal for printed cir ..
MB501 , TECHNICAL SPECIFICATIONS OF SINGLE-PHASE SILICON BRIDGE RECTIFIER
MB501 , TECHNICAL SPECIFICATIONS OF SINGLE-PHASE SILICON BRIDGE RECTIFIER
MB501L ,TWO MODULE PRESCALERSA ust 1995 I do
'l'fi1'j,','ltf, f FUJITSU
M350 f L/504/504L
TWO MODUL US PRESCALERS
TWO MO ..
MAX7300AAX+-MAX7300ATL+-MAX7300ATL+T
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
Pin Configurations continued at end of data sheet.●White Goods●Industrial Controllers●System Monitoring
General DescriptionThe MAX7300 compact, serial-interfaced, I/O expansion
peripheral provides microprocessors with up to 28 ports.
Each port is individually user configurable to either a logic
input or logic output.
Each port can be configured as either a push-pull logic
output capable of sinking 10mA and sourcing 4.5mA, or
a Schmitt logic input with optional internal pullup. Seven
ports feature configurable transition detection logic, which
generates an interrupt upon change of port logic level. The
MAX7300 is controlled through an I2C-compatible 2-wire
serial interface, and uses four-level logic to allow 16 I2C
addresses from only two select pins.
The MAX7300AAX and MAX7300ATL have 28 ports and
are available in 36-pin SSOP and 40-pin TQFN packages,
respectively. The MAX7300AAI and MAX7300ATI have 20
ports and are available in 28-pin SSOP and TQFN pack-
ages. For an SPI-interfaced version, refer to the MAX7301
data sheet. For a pin-compatible port expander with addi-
tional 24mA constant-current LED drive capability, refer to
the MAX6956 data sheet.
Features●400kbps I2C-Compatible Serial Interface●2.5V to 5.5V Operation●-40°C to +125°C Temperature Range●20 or 28 I/O Ports, Each Configurable as Push-Pull Logic Output Schmitt Logic Input Schmitt Logic Input with Internal Pullup●11µA (max) Shutdown Current ●Logic Transition Detection for Seven I/O Ports
*EP = Exposed pad.
Devices are also available in a lead(Pb)-free/RoHS-compliant
package. Specify lead-free by adding “+” to the part number
when ordering. Devices are also available in tape-and-reel
packaging. Specify tape and reel by adding “T” to the part
number when ordering.
PARTTEMP RANGEPIN-PACKAGEMAX7300AAI-40°C to +125°C28 SSOP
MAX7300ATI-40°C to +125°C28 TQFN-EP*
MAX7300AAX-40°C to +125°C36 SSOP
MAX7300ATL-40°C to +125°C40 TQFN-EP*
AD1
SCL
SDA
P31
P30
P22
P29
P28
P27
P26
P25
P24
P23
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
AD0
GND
GND
ISET
28 SSOPTOP VIEW
MAX7300
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander P10
P12
P13
P11
P15
P14
P17
P18
P16
P20
P19
I/O 5
I/O 4
I/O 7
I/O 8
I/O 6
I/O 10
I/O 9
I/O 12
I/O 13
I/O 11
I/O 15
I/O 14
I/O 17
I/O 18
I/O 16
I/O 20
I/O 19
I/O 21
I/O 22
I/O 23
P22
P23
P21
GND
GND
AD0
AD1
SCL
P30
P29
P31
P27
P28
P25
P24
P26
SDA
MAX7300AAX
DATA
CLOCK
I/O 24
I/O 25
I/O 27
I/O 26
I/O 29
I/O 30
I/O 28
I/O 31
47nF
39kΩ1ISET
Typical Operating Circuit
Ordering Information
Pin Conigurations
Application
Voltage (with respect to GND)
V+ ............................................................................-0.3V to +6V
SCL, SDA, AD0, AD1 ..............................................-0.3V to +6V
All Other Pins ..............................................-0.3V to (V+ + 0.3V)
P4–P31 Current ...............................................................±30mA
GND Current ....................................................................800mA
Continuous Power Dissipation (TA = +70°C)28-Pin SSOP (derate 9.1mW/°C above +70°C) ..........727mW28-Pin TQFN (derate 21.3mW/°C above +70°C) ......1702mW36-Pin SSOP (derate 11.8mW/°C above +70°C) ........941mW40-Pin TQFN (derate 26.3mW/°C above TA = +70°C) ....2105mW
Operating Temperature Range
TMIN to TMAX) ...............................................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)Lead (Pb)-free packages .............................................+260°CPackages containing lead (Pb) ....................................+240°C
(Typical Operating Circuit, VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Supply VoltageV+2.55.5V
Shutdown Supply CurrentISHDNAll digital inputs at
V+ or GND
TA = +25°C5.58TA = -40°C to +85°C10
TMIN to TMAX11
Operating Supply Current IGPOH
All ports programmed
as outputs high, no
load, all other inputs
at V+ or GND
TA = +25°C180240TA = -40°C to +85°C260
TMIN to TMAX280
Operating Supply Current IGPOL
All ports programmed
as outputs low, no
load, all other inputs
at V+ or GND
TA = +25°C170210TA = -40°C to +85°C230
TMIN to TMAX240
Operating Supply Current IGPI
All ports programmed
as inputs without
pullup, ports, and all
other inputs at V+ or
GND
TA = +25°C110135TA = -40°C to +85°C140
TMIN to TMAX145
INPUTS AND OUTPUTSLogic High Input Voltage
Port InputsVIH0.7 xV
Logic Low Input Voltage
Port InputsVIL0.3 xV
Input Leakage CurrentIIH, IILGPIO inputs without pullup,
VPORT = V+ to GND-100±1+100nA
GPIO Input Internal Pullup to V+IPUVV+ = 2.5V121930µAVV+ = 5.5V80120180
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Electrical CharacteristicsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
(VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
(Typical Operating Circuit, VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSerial Clock FrequencyfSCL400kHz
Bus Free Time Between a STOP
and a START Condition tBUF1.3µs
Hold Time (Repeated) START
ConditiontHD, STA0.6µs
Repeated START Condition
Setup TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD, DAT(Note 3)15900ns
Data Setup TimetSU, DAT100ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.7µs
Rise Time of Both SDA and SCL
Signals, ReceivingtR(Notes 2, 4)20 +
0.1Cb300ns
Fall Time of Both SDA and SCL
Signals, ReceivingtF(Notes 2, 4)20 +
0.1Cb300ns
Fall Time of SDA TransmittingtF,TX(Notes 2, 5)20 +
0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Notes 2, 6)050ns
Capacitive Load for Each Bus
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput High VoltageVOH
GPIO outputs, ISOURCE = 2mA,
TA = -40°C to +85°C
V+ -
0.7VGPIO outputs, ISOURCE = 1mA,
TA = TMIN to TMAX (Note 2)
V+ -
Port Sink CurrentIOLVPORT = 0.6V21018mA
Output Short-Circuit CurrentIOLSCPort configured output low, shorted to V+2.751120mA
Input High-Voltage SDA, SCL,
AD0, AD1VIH0.7 xV
Input Low-Voltage SDA, SCL,
AD0, AD1VIL0.3 xV
Input Leakage Current SDA, SCLIIH, IIL-50+50nA
Input Capacitance (Note 2)10pF
Output Low-Voltage SDAVOLISINK = 6mA0.4V
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Timing Characteristics (Figure 2)
Electrical Characteristics (continued)
(RISET = 39kΩ, TA = +25°C, unless otherwise noted.)
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 5: ISINK ≤ 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
(VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
OPERATING SUPPLY CURRENT vs. V+
(OUTPUTS UNLOADED)MAX7300 toc03
V+ (V)
SUPPLY CURRENT ( mA)
ALL PORTS INPUT
(PULLUPS DISABLED)
ALL PORTS OUTPUT (0)
ALL PORTS OUTPUT (1)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATUREMAX7300 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (A)
VV+ = 5.5V
VV+ = 3.3V
VV+ = 2.5V
OPERATING SUPPLY CURRENT
vs. TEMPERATUREMAX7300 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VV+ = 2.5V TO 5.5V
NO LOAD
ALL PORTS
OUTPUT (1)
ALL PORTS
OUTPUT (0)
ALL PORTS INPUT HIGH
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Typical Operating Characteristics
Timing Characteristics (Figure 2) (continued)
(RISET = 39kΩ, TA = +25°C, unless otherwise noted.)
GPO SHORT-CIRCUIT CURRENT
vs. TEMPERATUREMAX7300 toc07
TEMPERATURE (°C)
PORT CURRENT (mA)
GPO = 0, PORT
SHORTED TO V+
GPO = 1, PORT
SHORTED TO GND
GPI PULLUP CURRENT
vs. TEMPERATUREMAX7300 toc06
TEMPERATURE (°C)
PULLUP CURRENT (A)
VV+ = 5.5V
VV+ = 3.3V
VV+ = 2.5V
GPO SOURCE CURRENT vs. TEMPERATURE
(OUTPUT = 1)MAX7300 toc05
TEMPERATURE (°C)
PORT SOURCE CURRENT (mA)
VPORT = 1.4V
VV+ = 5.5V
VV+ = 3.3V
VV+ = 2.5V
GPO SINK CURRENT vs. TEMPERATURE
(OUTPUT = 0)MAX7300 toc04
TEMPERATURE (°C)
PORT SINK CURRENT (mA)
VV+ = 2.5V TO 5.5V, VPORT = 0.6V
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Typical Operating Characteristics (continued)
Detailed DescriptionThe MAX7300 general-purpose input/output (GPIO)
peripheral provides up to 28 I/O ports, P4 to P31, con-
trolled through an I2C-compatible serial interface. The
ports can be configured to any combination of logic inputs
and logic outputs, and default to logic inputs on power-up.
Figure 1 is the MAX7300 functional diagram. Any I/O port
can be configured as a push-pull output (sinking 10mA,
sourcing 4.5mA), or a Schmitt-trigger logic input. Each
input has an individually selectable internal pullup resis-
tor. Additionally, transition detection allows seven ports
(P24 to P30) to be monitored in any maskable combina-
tion for changes in their logic status. A detected transi-
tion is flagged through a status register bit, as well as an
interrupt pin (port P31), if desired.
The port configuration registers individually set the 28
ports, P4 to P31, as GPIO. A pair of bits in registers
0x09 through 0x0F sets each port’s configuration
(Tables 1 and 2).
The 36-pin MAX7300AAX and 40-pin MAX7300ATL have
28 ports, P4 to P31. The 28-pin MAX7300ANI,
MAX7300AAI, and MAX7300ATI have only 20 ports avail-
able, P12 to P31. The eight unused ports should be
configured as outputs on power-up by writing 0x55 to
registers 0x09 and 0x0A. If this is not done, the eight
unused ports remain as unconnected inputs and quies-
cent supply current rises, although there is no damage
to the part.
Register Control of I/O Ports
Across Multiple DriversThe MAX7300 offers 20 or 28 I/O ports, depending on
package choice. Two addressing methods are avail-
able. Any single port (bit) can be written (set/cleared)
at once; or, any sequence of eight ports can be written
(set/cleared) in any combination at once. There are no
boundaries; it is equally acceptable to write P0 to P7, P1
to P8, or P31 to P38 (P32 to P38 are nonexistent, so the
instructions to these bits are ignored).
ShutdownWhen the MAX7300 is in shutdown mode, all ports are
forced to inputs, and the pullup current sources are
turned off. Data in the port and control registers remain
unaltered, so port configuration and output levels are
restored when the MAX7300 is taken out of shutdown.
The MAX7300 can still be programmed while in shutdown
mode. For minimum supply current in shutdown mode,
logic inputs should be at GND or V+ potential. Shutdown
mode is exited by setting the S bit in the configuration
PINNAMEFUNCTION28 SSOP28 TQFN-EP36 SSOP40 TQFN-EP26136ISETBias Current Setting. Connect ISET to GND through a resistor
(RISET) value of 39kΩ to 120kΩ.
2, 327, 282, 337, 38, 39GNDGround1440AD0Address Input 0. Sets device slave address. Connect to either
GND, V+, SCL, SDA to give four logic combinations. See Table 3.
5–242–21——P12–P31I/O Ports. P12 to P31 can be conigured as push-pull outputs,
CMOS-logic inputs, or CMOS-logic inputs with weak pullup resistor.—5–321–10, 12–19,
21–30P4–P31I/O Ports. P4 to P31 can be conigured as push-pull outputs,
CMOS-logic inputs, or CMOS-logic inputs with weak pullup resistor.——11, 20, 31N.C.No Connection. Not internally connected.223332SDAI2C-Compatible Serial-Data I/O233433SCLI2C-Compatible Serial-Clock Input243534AD1Address Input 1. Sets device slave address. Connect to either
GND, V+, SCL, SDA to give four logic combinations. See Table 3.253635V+Positive Supply Voltage. Bypass V+ to GND with minimum
0.047µF capacitor.———EP
Exposed Pad (TQFN Only). EP is internally connected to GND.
Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Pin Description
Serial Interface
Serial AddressingThe MAX7300 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7300, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7300 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7300 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7300
7-bit slave address plus R/W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
START and STOP ConditionsBoth SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit TransferOne data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
AcknowledgeThe acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is
sta-ble low during the high period of the clock pulse.
When the master is transmitting to the MAX7300, the
Table 2. Port Configuration Matrix
Table 1. Port Configuration Map
MODEFUNCTION
PORT
REGISTER
(0x20–0x5F)
PIN BEHAVIORADDRESS
CODE (HEX)
PORT
CONFIGURATION
BIT PAIR
UPPERLOWERDO NOT USE THIS SETTING0x09 to 0x0F00
OutputGPIO OutputRegister bit = 0Active-low logic output0x09 to 0x0F01Register bit = 1Active-high logic output
InputGPIO Input
without PullupRegister bit =
input logic level
Schmitt logic input0x09 to 0x0F10
InputGPIO Input with PullupSchmitt logic input with pullup0x09 to 0x0F11
REGISTERADDRESS
CODE (HEX)
REGISTER DATAD6D5D4D3D2D1D0Port Configuration for P7, P6, P5, P40x09P7P6P5P4
Port Configuration for P11, P10, P9, P80x0AP11P10P9P8
Port Configuration for P15, P14, P13, P120x0BP15P14P13P12
Port Configuration for P19, P18, P17, P160x0CP19P18P17P16
Port Configuration for P23, P22, P21, P200x0DP23P22P21P20
Port Configuration for P27, P26, P25, P240x0EP27P26P25P24
Port Configuration for P31, P30, P29, P280x0FP31P30P29P28
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
MAX7300 is the recipient. When the MAX7300 is
transmitting to the master, the master generates the
acknowledge bit since the master is the recipient.
Slave AddressThe MAX7300 has a 7-bit-long slave address (Figure
6). The eighth bit following the 7-bit slave address is
the RW bit. It is low for a write command and high for a
read command.
The first 3 bits (MSBs) of the MAX7300 slave address
are always 100. Slave address bits A3, A2, A1, and A0
are selected by the address inputs, AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX7300 has 16 possible slave
addresses (Table 3), and therefore a maximum of 16
MAX7300 devices can share the same interface.
Message Format for Writing
the MAX7300A write to the MAX7300 comprises the transmission
of the MAX7300’s slave address with the R/W bit set
to zero, followed by at least 1 byte of information. The
first byte of information is the command byte. The com-
mand byte determines which register of the MAX7300
is to be written by the next byte, if received. If a STOP
condition is detected after the command byte is
received, then the MAX7300 takes no further action
(Figure 7) beyond storing the command byte.
Figure 1. MAX7300 Functional Diagram
SLAVE ADDRESS BYTED1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
R/WDATA
SDA
SCL
PORT REGISTERS
GPIO
CONFIGURATION
P4 TO P31
ADDRESS
MATCHER
AD0
AD1
COMMAND BYTEDATA BYTE
R/W7-BIT DEVICE ADDRESS
TO COMMAND REGISTERSTO/FROM DATA REGISTERS
GPIO DATA
R/W
CONFIGURATION
REGISTERSPORT CHANGE
DETECTOR
MASK REGISTER
COMMAND
REGISTER DECODE
DATA BYTECOMMAND BYTE
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Any bytes received after the command byte are consid-
ered data bytes. The first data byte goes into the internal
register of the MAX7300 selected by the command byte
(Figure 8). If multiple data bytes are transmitted before
a STOP condition is detected, these bytes are gener-
ally stored in subsequent MAX7300 internal registers
because the command byte address generally autoincre-
ments (Table 4).
Message Format for Reading The MAX7300 is read using the MAX7300’s internally
stored command byte as address pointer, the same way
a write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
(Table 4). Thus, a read is initiated by first configuring the
MAX7300’s command byte by performing a write (Figure
7). The master can now read ‘n’ consecutive bytes from
the MAX7300, with the first data byte being read from
the register addressed by the initialized command byte
(Figure 9). When performing read-after-write verification,
remember to reset the command byte’s address because
the stored control byte address generally has been auto-
incremented after the write (Table 4). Table 5 is the regis-
ter address map.
Figure 4. Bit Transfer
Figure 3. Start and Stop Conditions
Figure 2. 2-Wire Serial Interface Timing Details
SDA
SCL
DATA LINE STABLE; DATA VALIDCHANGE OF DATA ALLOWED
SDA
SCLS
START
CONDITION
STOP
CONDITION
SCL
SDA
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
tSU, DAT
tHD, DATtLOW
tHD, STA
tHIGHtF
tSU, STA
tHD, STA
tSU, STO
tBUF
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Operation with Multiple MastersIf the MAX7300 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7300 should
use a repeated start between the write, which sets the
MAX7300’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is pos-
sible for master 2 to take over the bus after master 1
has set up the MAX7300s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes, the MAX7300’s address pointer, then master 1’s
delayed read can be from an unexpected location.
Command Address Autoincrementing Address autoincrementing allows the MAX7300 to be
configured with the shortest number of transmissions by
minimizing the number of times the command address
needs to be sent. The command address stored in the
MAX7300 generally increments after each data byte is
written or read (Table 4).
Initial Power-UpOn initial power-up, all control registers are reset and the
MAX7300 enters shutdown mode (Table 6).
Transition (Port Data Change) DetectionPort transition detection allows any combination of the
seven ports P24–P30 to be continuously monitored for
changes in their logic status (Figure 10). A detected
change is flagged on the transition detection mask reg-
ister INT status bit, D7 (Table 10). If port P31 is config-
ured as an output (Tables 1 and 2), then P31 also
automatically becomes an active-high interrupt output
(INT), which follows the condition of the INT status bit.
Port P31 is set as output by writing bit D7 = 0 and bit
D6 = 1 to the port configuration register (Table 1). Note
that the MAX7300 does not identify which specific
port(s) caused the interrupt, but provides an alert that
one or more port levels have changed.
The mask register contains 7 mask bits that select
which of the seven ports P24–P30 are to be monitored
(Table 10). Set the appropriate mask bit to enable that
Figure 6. Slave Address
Figure 5. Acknowledge
SDA
SCL0A3A2A1A00
MSBLSB
R/WACK
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGMENTSTART CONDITION
SDA
BY RECEIVER289
MAX73002-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
