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MAX7049ATI+
High-Performance, 288MHz to 945MHz ASK/FSK ISM Transmitter
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
General Description
The MAX7049 high-performance, single-chip, ultra-
low-power ASK/FSK UHF transmitter operates in the
industrial, scientific, medical (ISM) band at 288MHz to
945MHz carrier frequencies. The IC also includes a low
phase noise fractional-N synthesizer for precise tuning,
fast frequency agility, and low out-of-band power. To
support narrow-band applications, the IC has both
amplitude-shaping and frequency-shaping functions that
enable the user to optimize spectral efficiency. The IC
offers Tx power up to +15dBm. These features make the
transmitter ideally suited for long-range applications.
Additional system-level features of the IC include a digital
temperature sensor and a number of flexible GPOs for
monitoring radio status and for the control of external
functions. A complete transmitter system can be built
using a low-end microprocessor control unit (MCU), the
IC, a crystal, and a small number of passive components.
The IC is available in a small, 5mm x 5mm, 28-pin TQFN
package with an exposed pad. It is specified to operate
in the -40°C to +125°C automotive temperature range.
Applications
Automatic Meter Reading (AMR)
RF Modules
Long-Range, One-Way Remote Keyless Entry (RKE)
Wireless Sensor Networks
TPMS
Home Security
Home Automation
RFID
Remote Controls
Benefits and Features
S Transmitter (Tx) Provides Long Transmit Range Up to +15dBm 21mA Tx Current for +10dBm Tx Power* 41mA Tx Current for +15dBm Tx Power* Modulation Shaping, ASK, FSK
S General Delivers Long Battery Life < 50nA Shutdown Current < 350nA Sleep Current Minimizes the Number of I/Os Required Between the IC and the MCU Serial Peripheral Interface (SPI™) Regulatory Compliant FCC Part 15 Frequency Hopping ETSI EN300-220 Compatible On-Chip Temperature Sensor Fast Fractional-N Synthesizer with a User-Defined External Loop Filter
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX7049.related.
Ordering Information appears at end of data sheet.
*VDD = 3.0V. Includes losses for the matching network and
regulatory-compliant harmonic filter.
EVALUATION KIT AVAILABLE
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Absolute Maximum Ratings ......................................................................5
DC Electrical Characteristics .....................................................................5
AC Electrical Characteristics .....................................................................6
Typical Operating Characteristics .................................................................9
Pin Configuration .............................................................................13
Pin Description...............................................................................13
Functional Diagram ...........................................................................15
Detailed Description...........................................................................15
Architectural Overview and Applications Circuit....................................................15
Digital Inputs and Outputs ....................................................................17
Digital Inputs ............................................................................17
Digital Outputs...........................................................................17
Serial Peripheral Interface (SPI) .............................................................19
SPI Commands ..........................................................................20
Operating Mode Overview..................................................................21
Sleep Mode .............................................................................22
Temperature Sensor Mode..................................................................23
Tx Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Frequency-Hopping Spread-Spectrum (FHSS) Operation .........................................24
Functional Descriptions.......................................................................25
Crystal Oscillator .........................................................................25
Fractional-N Synthesizer ...................................................................26
Tx ASK Mode............................................................................26
Tx FSK Mode Using Frequency Waveshaping...................................................27
Tx Pulse FSK Mode .......................................................................29
Loop Bandwidth..........................................................................29
Lock Detector............................................................................30
Power Amplifier ..........................................................................31
Tx ASK Mode Using Amplitude Waveshaping...................................................33
Tx FSK Mode Amplitude Ramp ..............................................................34
Register Details ..............................................................................35
Detailed Register Descriptions .................................................................37
Layout Considerations .........................................................................49
Ordering Information ..........................................................................50
Chip Information..............................................................................50
Package Information...........................................................................50
TABLE OF CONTENTS
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Figure 1. SPI Timing Diagram.....................................................................8
Figure 2. Typical Operating Circuit ...............................................................16
Figure 3. Digital Inputs.........................................................................17
Figure 4. Digital Outputs .......................................................................18
Figure 5. Digital Output Options..................................................................18
Figure 6. SPI Format...........................................................................20
Figure 7. SPI Write Command Format .............................................................20
Figure 8. SPI Read Command Format.............................................................21
Figure 9. SPI Read-All Command Format ..........................................................21
Figure 10. SPI Reset Command Format............................................................21
Figure 11. Operating Modes.....................................................................21
Figure 12. Tx Warmup Timing Diagram ............................................................23
Figure 13. Frequency-Hopping Spread-Spectrum (FHSS) Flowchart .....................................24
Figure 14. Recommended Crystal Connection to the IC...............................................25
Figure 15. Fractional-N Synthesizer Configuration Tx ASK Mode ........................................27
Figure 16. Tx FSK Mode Programming ............................................................28
Figure 17. Tx FSK Frequency Waveshaping Timing Diagram ...........................................28
Figure 18. Synthesizer Loop Filter Topology ........................................................30
Figure 19. Lock Detector Delay Function...........................................................30
Figure 20. Power Amplifier Topology and Optimum Signal Swings.......................................31
Figure 21. Tx ASK Mode Programming ............................................................32
Figure 22. ASK Waveshaping Timing Diagram ......................................................33
Figure 23. Tx FSK Amplitude Ramp Feature ........................................................34
Figure 24. Tx FSK Amplitude Ramp Timing Diagram..................................................35
Table 1. Optional Digital Input Controls ............................................................17
Table 2. Mode Control Logic ....................................................................22
Table 3. Mode Option Logic.....................................................................22
Table 4. Sleep Mode Summary ..................................................................22
Table 5. Temperature Sensor Mode Summary.......................................................23
Table 6. Crystal Divider Programming.............................................................25
Table 7. LO Frequency-Divider Modes.............................................................26
Table 8. Tx FSK Pulse Mode Frequency Multiplier Values..............................................29
LIST OF FIGURES
LIST OF TABLES
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
LIST OF TABLES (continued)
Table 10. Configuration Register Map .............................................................35
Table 11. Group 0: Identification Register (Ident).....................................................37
Table 12. Ident Register (0x00) ..................................................................37
Table 13. Group 1: General Configuration Registers (Conf0, Conf1)......................................37
Table 14. Conf0 Register (0x01)..................................................................37
Table 15. Conf1 Register (0x02)..................................................................38
Table 16. Group 2: GPO, Data Output, and Clock Output Registers (IOConf0, IOConf1, IOConf2)..............38
Table 17. IOConf0 Register (0x03)................................................................39
Table 18. Register IOConf1 (0x04)................................................................40
Table 19. Register IOConf2 (0x05)................................................................41
Table 20. Group 3: Synthesizer Frequency Settings (FBase0, FBase1, FBase2, FLoad) ......................41
Table 21. Synthesizer Divider Settings.............................................................41
Table 22. Synthesizer Programming Values.........................................................42
Table 23. Frequency Ranges ...................................................................42
Table 24. FBase0 Register (0x08) ................................................................42
Table 25. FBase1 Register (0x09) ................................................................42
Table 26. FBase2 Register (0x0A) ................................................................42
Table 27. FLoad (0x0B) ........................................................................42
Table 28. Group 4: Transmiter Amplitude and Timing Parameters (TxConf0, TxConf1, TxTstep).................43
Table 29. TxConf0 Register (0x0C) ...............................................................43
Table 30. TxConf1 Register (0x0D) ...............................................................43
Table 31. TxTstep Register (0x0E) ................................................................43
Table 32. Group 5: Transmitter Shaping Registers (Shape00–Shape18)...................................44
Table 33. Shape00 Register (0x0F)...............................................................44
Table 34. Shape01–Shape18 Registers (0x10–0x21) .................................................45
Table 35. Group 6: Control Registers (TestMux, Datain, EnableReg) .....................................45
Table 36. TestMux Register (0x3C) ...............................................................45
Table 37. Datain Register (0x3D) .................................................................46
Table 38. EnableReg Register (0x3E) .............................................................46
Table 39. Group 7: Read-Only Status Registers (TestBus0, TestBus1, Status0, Status1) ......................46
Table 40. TestBus0 Register (0x40)...............................................................46
Table 41. Test Bus Signals (tbus[15:8]).............................................................47
Table 42. TestBus1 Register (0x41) ...............................................................47
Table 43. Test Bus Signals (tbus[7:0]) .............................................................48
Table 44. Status0 Register (0x42) ................................................................49
Table 45. Status1 Register (0x43) ................................................................49
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
PAVDD, LOVDD, VCOVDD, CPVDD, PLLVDD,
XOVDD, DVDD, and AVDD to EP ....................-0.3V to +3.6V
ENABLE, DATAIN, SDI, SDO, CS, SCLK,
GPO1, GPO2, HOP, and SHDN to EP .-0.3V to (VDD + 0.3V)
All Other Pins to EP ..................................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70NC)
TQFN (single-layer board)
(derate 21.3mW/NC above +70NC) .........................1702.1mW
Operating Temperature Range ........................-40NC to +125NC
Storage Temperature Range ............................-65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
CAUTION! ESD SENSITIVE DEVICEPARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply Voltage VDD
PAVDD, LOVDD, VCOVDD, CPVDD,
PLLVDD, XOVDD, DVDD, and AVDD
connected to power supply
2.13.03.6V
Operating CurrentIDD
PA off
fRF = 315MHz11.2
fRF = 434MHz10.4
fRF = 863MHz to 945MHz10.2
PA off,
PA predriver at
high current
setting
fRF = 315MHz13.2
fRF = 434MHz12.4
fRF = 863MHz to 945MHz12.2
POUT = +15dBm
868MHz +15dBm
matching network with
harmonic filter
POUT = +10dBm
868MHz +10dBm
matching network with
harmonic filter
Shutdown Current
TA = +25NC, Sleep mode350
TA = +85NC, Sleep mode600
TA = +125NC, Sleep mode17004000
TA = +25NC, Shutdown mode (registers reset)50
TA = +85NC, Shutdown mode (registers reset)200
TA = +125NC, Shutdown mode
(registers reset)13003500
Input Low VoltageVIL0.2 x VDDV
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
DC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Pulldown Sink Current 12.5Pullup Source Current 12.5
Output Low Voltage VOL
In buffer mode, GPO1 250FA sink current,
SDO 1mA sink current, and GPO2 4mA
sink current
Output High VoltageVOH
In buffer mode, GPO1 250FA source current,
SDO 1mA source current, and GPO2 4mA
source current
VDD - 0.225
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICS
Operating Frequency
Divide-by-1 LO divider setting863945
MHzDivide-by-2 LO divider setting431.5472.5
Divide-by-3 LO divider setting287.7315
Maximum Data RateManchester encoded100kbpsNRZ encoded200
Maximum Frequency Deviation100kHz synthesizer loop bandwidth Q150kHz
Frequency Settling TimetON
From Enable low-to-high transition to LO
within 5kHz of final value, 100kHz synthesizer
loop bandwidth
From Enable low-to-high transition to LO
within 1kHz of final value, 100kHz synthesizer
loop bandwidth
POWER AMPLIFIER
Maximum Output Power PMAXMatch to 50I, including harmonic filter+15dBm
Programmable PA Bias Current
Step
With Q1% 56.2kI external PA reference
current setting resistor0.5mA
Programmable PA Power
Dynamic Range
Power range from decimal 1 to decimal 63
on digital PA bias current36dB
Modulation DepthWith respect to +10dBm output power57dB
Maximum Carrier HarmonicsWith output matching network-50dBc
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
AC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
FRACTIONAL-N SYNTHESIZER
VCO Gain KVCOReferenced to 863MHz to 945MHz LO108MHz/V
Close-In Phase Noise10kHz offset, 100kHz loop BW -101dBc/Hz
VCO Phase Noise1MHz offset, 863MHz to 945MHz-126dBc/Hz
Charge-Pump CurrentICPVOUT = VCPVDD/2, low setting (icont bit = 0)204FA
VOUT = VCPVDD/2, high setting (icont bit = 1)407FA
LO Divider Settings
Minimum Synthesizer Frequency
Step
Referenced to 863MHz to 945MHz LO or
carrier frequency bandfXTAL/216Hz
Reference Spur-71dBc
Frequency Switching Time26MHz frequency step, 902MHz to 928MHz
band, 100kHz synthesizer loop bandwidth48Fs
Reference Frequency Input
Level1VP-P
ADC
Resolution7Bits
LSB Bit Width7.25mV
CRYSTAL OSCILLATOR
Crystal FrequencyfXTAL16 to 22.4MHz
Frequency Pulling by VDD0.5ppm/V
Recommended Crystal Load
Capacitance10Maximum Crystal Load
Capacitance20
TEMPERATURE SENSOR
Range-40 to +125NC
Digital Code Slope2NC/LSB
SPI TIMING CHARACTERISTICS (Figure 1)
Minimum SCLK Low to Falling
Edge of CS Setup TimetSC20ns
Minimum CS Low to Rising Edge
of SCLK Setup TimetCSS30ns
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
AC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
Figure 1. SPI Timing Diagram
tCSH
tSC
SCLK
SDI
SDO
tHCStCSS
tDS
tDH
tCL
tCH
tCSGtCG
tHS
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Minimum SCLK Low to Rising
Edge of CS Setup TimetHCS30ns
Minimum SCLK Low after Rising
Edge of CS Hold TimetHS20ns
Minimum Data Valid to SCLK
Rising-Edge Setup TimetDS15ns
Minimum Data Valid to SCLK
Rising-Edge Hold TimetDH10ns
Minimum SCLK High Pulse
WidthtCH30ns
Minimum SCLK Low Pulse WidthtCL30ns
Minimum CS High Pulse WidthtCSH30ns
Maximum Transition Time from
Falling Edge of CS to Valid SDOtCSGCL = 10pF load capacitance from
SDO to GND20ns
Maximum Transition Time from
Falling Edge of SCLK to
Valid SDO
tCGCL = 10pF load capacitance from
SDO to GND20ns
Typical Operating Characteristics
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Typical Operating Characteristics
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
SHUTDOWN MODE CURRENT
vs. TEMPERATURE
MAX7049 toc01
TEMPERATURE (°C)
SHUTDOWN MODE CURRENT (µA)
VDD = 2.1V
VDD = 2.7V
VDD = 3.6V
VDD = 3.0V
VCO TUNING CHARACTERISTIC
(IN 900MHz BAND) vs. CONTROL VOLTAGE
MAX7049 toc04
CONTROL VOLTAGE WITH RESPECT TO SUPPLY (V)
TRANSMIT FREQUENCY (MHz)
TA = +25˚C
TA = -40˚C
TA = +125˚C
TA = +85˚C
SLEEP MODE CURRENT
vs. TEMPERATURE
MAX7049 toc02
TEMPERATURE (°C)
SLEEP MODE CURRENT (µA)
VDD = 2.1V
VDD = 2.7V
VDD = 3.0V
VDD = 3.6V
FREQUENCY SETTLING
AFTER POWER-UP
MAX7049 toc05
868.62MHz
868.60MHz
868.58MHz
100.0µs/div
0.00s500.0µs1.000ms
TEMPERATURE SENSOR CODE
vs. TEMPERATURE
MAX7049 toc03
TEMPERATURE (°C)
TEMPERATURE SENSOR CODE (DECIMAL)
CHARGE-PUMP CURRENT
vs. CONTROL VOLTAGE
(LOW CURRENT SETTING, 2.1V SUPPLY)
MAX7049 toc06
CHARGE-PUMP CURRENT (µ
CONTROL VOLTAGE WITH RESPECT TO GROUND (V)0.20.40.60.81.01.21.41.61.82.0DOWN
+25˚C
+85˚C
+125˚C
-40˚C-40˚C
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Typical Operating Characteristics (continued)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
PHASE NOISE (VCO DOMINATED)
vs. OFFSET FREQUENCY
(CL = 0.1µF, CS = 0.01µF,
R = 200I, RP = CP = 0)
MAX7049 toc07
OFFSET FREQUENCY (kHz)
PHASE NOISE (dBc/Hz)
-14010,000
927MHz, ibsel = 1
868MHz, ibsel = 0
927MHz, ibsel = 0
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
16MHz CRYSTAL, ibsel = 0, icont = 0)
MAX7049 toc10
FREQUENCY (MHz)
(dBc
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
22.4MHz CRYSTAL, ibsel = 0, icont = 0)
MAX7049 toc08
FREQUENCY (MHz)
(dBc
UNMODULATED SPECTRUM
(palopwr = 0, 100% DUTY CYCLE,
+10dBm, 868MHz,
WITH +10dBm AT 3V MATCH)
MAX7049 toc11
FREQUENCY (MHz)
POWER (dBc)
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
22.4MHz CRYSTAL, ibsel = 0, icont = 0)
MAX7049 toc09
FREQUENCY (MHz)
(dBc
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+10dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
MAX7049 toc12
POWER (dBc)
GAUSSIAN
UNSHAPED
FREQUENCY (MHz)
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Typical Operating Characteristics (continued)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+9dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
MAX7049 toc13
POWER (dBc)
-80GAUSSIAN
UNSHAPED
FREQUENCY (MHz)
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
MAX7049 toc16
POWER (dBc)
FREQUENCY (MHz)
GAUSSIAN
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
MAX7049 toc17
POWER (dBc)
FREQUENCY (MHz)
UNSHAPED
FSK MODULATION SPECTRUM (1kHz RBW,
4kHz SQUARE-WAVE MODULATION,
±4kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
MAX7049 toc14
POWER (dBc)
FREQUENCY (MHz)
GAUSSIAN
FSK MODULATION SPECTRUM
(1kHz RBW, 4kHz SQUARE-WAVEMODULATION,
±4kHz DEVIATION, +10dBm OUTPUT POWER,
WITH +10dBm AT 3V MATCH)
MAX7049 toc15
POWER (dBc)
UNSHAPED
FREQUENCY (MHz)
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Typical Operating Characteristics (continued)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
Tx CURRENT vs. TEMPERATURE
(PA OFF, 900MHz BAND, palopwr = 1)
MAX7049 toc18
TEMPERATURE (°C)
Tx CURRENT (mA)
VDD = 3.6V
VDD = 2.7V
VDD = 3.0V
VDD = 2.1V
PA POWER vs. PA CODE
(palopwr = 1, 100% DUTY CYCLE, 868MHz,
WITH +10dBm AT 3V MATCH)
MAX7049 toc21
PA CODE (DECIMAL)48403224168
OUT
(dBm)2.1V
2.4V2.7V3.0V3.3V3.6V
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 868MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc22
TEMPERATURE (°C)
OUT
(dBm)
PA CODE 39
PA CODE 19
PA CODE 10
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 915MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc19
PA CODE (DECIMAL)
OUT
(dBm)48403224168
3.0V
2.1V
3.6V
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 868MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc20
PA CODE (DECIMAL)
OUT
(dBm)48403224168
3.0V
2.1V
3.6V
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Pin Configuration
Pin Description
MAX7049
TQFN(5mm x 5mm)
TOP VIEW
REXTPA
LOVDD
VCOVDD
CTRL
CPVDD
PAVDDSCLKENABLEGPO2DATAINSDO
SHDN672119171615
AVDD
PA+
XTALC
XOVDD
N.C.
PLLVDD
N.C.
SDI8PA-CPOUT+
GPO113XTALBHOP14N.C.DVDD
PINNAMEFUNCTIONPAVDDPower Amplifier Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible to the pin.REXTPA
External PA Bias Current Setting Resistor Connection. Couple to ground through a Q1% tolerance low-
temperature coefficient resistor. A resistor of 56.2kI is recommended for a 0.5mA nominal PA bias
current DAC LSB value.
3, 10, N.C.No Connection. Leave unconnected.LOVDDLocal Oscillator (LO) Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible
to the pin.VCOVDDVoltage-Controlled Oscillator (VCO) Supply Voltage. Bypass to ground with 1FF capacitor as close as
possible to the pin.CTRLControl (Tuning) Voltage for VCO Input. Referenced to VCOVDD pin. Connect through passive loop filter to
CPOUT.CPVDDCharge-Pump Supply Voltage Input. Bypass to ground with 0.01FF capacitor as close as possible to the pin.CPOUTCharge-Pump Output. Connect through passive loop filter to CTRL.PLLVDDSynthesizer Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible to the pin.XOVDDCrystal Oscillator Supply Voltage Input. Bypass to ground with 0.1FF capacitor as close as possible to
the pin.
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Pin Description (continued)
PINNAMEFUNCTIONXTALC
Collector Crystal Input. Connect to crystal either directly or through an AC-coupling capacitor. A shunt
capacitance to ground might be needed depending on the specified load capacitance of the crystal and
PCB stray capacitances. Can be driven by an AC-coupled external reference with a signal swing of
0.8VP-P to 1.2VP-P.XTALB
Base Crystal Input. Connect to crystal either directly or through an AC-coupling capacitor. A shunt
capacitance to ground might be needed depending on the specified load capacitance of the crystal and
PCB stray capacitances. Must be DC shorted to ground if XTALC is driven by external reference.SDOSerial Peripheral Interface (SPI) Data Output. It can also be configured as a general-purpose digital output.DATAINTransmitter Data Input. The Datain function can also be controlled by SPI. Internally pulled to ground.ENABLEEnable. Drive high for active operation. Drive low or leave unconnected to put the device into Sleep mode.
The enable function can also be controlled by SPI. Internally pulled to ground.SCLKSPI Clock. Internally pulled to ground.SDISPI Data Input. Internally pulled to ground.CSSPI Active-Low Chip Select. Internally pulled to supply.GPO2General-Purpose Output 2. High drive strength digital general-purpose output.DVDDDigital Supply Voltage Input. Bypass to ground with 0.1FF capacitor as close as possible to the pin.HOPFrequency Hop Pin. Transfers the base[20:0] bits to the fractional-N divider. See the Fractional-N Synthesizer
section. The hop function can also be controlled by SPI. Internally pulled to ground. GPO1General-Purpose Output 1. Low drive strength digital general-purpose output.SHDN
Shutdown Digital Input. Turns off internal power-on-reset (POR) circuit when driven high. Register contents
are set to the initial state when driven high. Must be driven low for normal operation. Not internally pulled to
supply or ground. AVDDAnalog Supply Voltage Input. Bypass to ground with a 1FF capacitor as close as possible to the pin.PA+Power Amplifier (PA) Positive Output. Requires DC current path to supply voltage through an inductive path.
The DC current path can be part of the output impedance matching and harmonic filter network. PA-Power Amplifier (PA) Negative Output. Requires DC current path to supply voltage through an inductive path.
The DC current path can be part of the output impedance matching and harmonic filter network. EPExposed Pad. This is the only ground connection. Solder evenly to the PCB ground plane for proper
operation. Multiple vias from the solder pad to the PCB ground plane are recommended.
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Functional Diagram
Detailed Description
Architectural Overview and
Applications Circuit
The MAX7049 includes a single precision local oscillator
fractional-N synthesizer with an integrated VCO, fraction-
al-N divider, phase/frequency detector, charge pump,
LO divider, and lock detector. The loop filter is located
off-chip to allow the user to optimize the synthesizer noise
and transient characteristics for a particular application.
In FSK transmit mode, the synthesizer transitions between
the mark and the space frequency based on the state
of the DATAIN pin or datain bit (Datain register, 0x3D,
bit 6). A user-programmable frequency-shaping function
enables the user to precisely define the transition from the
mark frequency to the space frequency and vice versa to
minimize spectral width of the modulated Tx waveform.
The IC utilizes a differential emitter-coupled, dual-open-
The bias current of the output stage is set with a combi-
nation of an external resistor and an internal amplitude-
shaping function. The programmable shaping func-
tion enables the user to precisely define the transition
between carrier on and carrier off and vice versa based
on the state of the DATAIN pin or datain bit so as to
minimize the spectral width of the modulated Tx signal.
Linear amplitude ramping is used in FSK mode as the PA
is enabled at the beginning of a data burst and disabled
at the end of a data burst for spectral control.complete transmitter system can be built using a
low-end MCU, the IC, a crystal, and a small number of
passive components for power-supply bypassing and for
RF matching, as illustrated in Figure 2.
Communication between the MCU and the IC is accom-
plished through a 4-pin SPI bus and a number of optional
digital inputs and outputs.ENABLE*DATAIN*SDO*
DIGITAL
CONTROL
AND MCU
INTERFACE
PA+28
PA-
CPOUT
REXTPA
GROUNDED
PAD (EP)
VCO
CTRL6
/1, /2, OR /3
FRACTIONAL-N
DIVIDERPFD
TEMPERATURE
SENSOR
ADC
* OPTIONAL I/Os FROM/TO MCU.13
XTALCXTALB
XTAL OSCILLATOR
SHDN*25
GPO1*24
HOP*23
GPO2*2120
SDI19
SCLK18
CHARGE
PUMP
MAX7049
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Figure 2. Typical Operating Circuit 810
LOVDD
VCOVDD
CTRL
CPVDD
PAVDD
REXTPA
SCLK
SDI
DATAIN
SDO
GPO2
DVDDHOPGPO1
XTAL
XTAL
N.C.
VDD
ENABLE
SHDN
XOVD
AVDDPA+PA-
N.C.N.C.
PLLVDD
CPOUT
DASHED LINES DENOTE OPTIONAL CONNECTIONS14282625242322C6
C11
C20
C13
C14L2
GROUNDED
PAD (EP)
MAX7049C10
C12
C16C15L3
C17
50I
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Digital Inputs and Outputs
Digital Inputs
The IC’s SPI inputs are the CS, SCLK, and SDI pins. The
CS pin is active low, so this pin has an internal pullup.
The SCLK and SDI pins have internal pulldowns. In addi-
tion to the SPI inputs, there are also a number of optional
digital inputs to the IC. These inputs are DATAIN,
ENABLE, and HOP. These optional inputs, which have
internal pulldowns, give the user the option to control an
internal signal by either driving the pin to the appropriate
logic level or by setting a control bit to the appropriate
state. This is illustrated in Figure 3.
SPI control minimizes the number of I/Os required
between the IC and the MCU, whereas the pin control
eliminates the configuration overhead associated with
SPI communication.
Digital Outputs
The IC has two dedicated general-purpose outputs
(GPO1 and GPO2), one SPI output (SDO) that can also
serve as a general-purpose output when CS is high. The
GPO1, GPO2, and SDO pins can be configured to output
various internal status signals and clocks, as illustrated
in Figure 4.
The outputs (GPO1 and GPO2) offer a feature where the
pin can operate either as a digital buffer or as a current-
limited source/sink output, as illustrated in Figure 5.
Table 1. Optional Digital Input Controls
Figure 3. Digital Inputs
SPI INPUTS
INPUT = DATAIN, ENABLE, AND HOPINPUT = SCLK AND SDI
DVDD
GROUNDED
PAD (EP)22
INPUTINPUT20INTERNAL
CSB
SIGNAL
DVDD
GROUNDED
PAD (EP)
INTERNAL
INPUT
SIGNAL
DVDD
‘OR’
GROUNDED
PAD (EP)
INTERNAL
INPUT
SIGNAL
INPUTPROGRAMMABLE
CONTROL BIT
PINBIT NAMEREGISTER
NAME
REGISTER
ADDRESS (hex)
BIT LOCATION
(7:0)FUNCTION
DATAINdatainDatain0x3D6Data input to transmitter.
ENABLEenableEnableReg0x3E0Enable input for transmitter.
HOPhopFLoad0x0B0Initiates the transition to the next
frequency as defined by base[20:0].
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Figure 4. Digital Outputs
sdos[3:0]
SDO15SPI READ-ONLY REGISTERS
TestBus0 AND TestBus1 (0x40 AND 0x41)MUX
gp1md[1:0]
GPO124
gp1s[3:0]
INTERNAL SIGNALSMUX
MUX
/1, /2,
/4, OR /8
tmux[3:0]
tbus[15:0]
[15:4]
MUX
/1, /2,
/4, OR /8/16
/1, /2,
/4, OR /8
/5, /6,
/7, OR /8
gp2md[2:0]ckdiv[1:0]
clksht
xtal
gp2isht
GPO221
gp1isht
gp2s[3:0]
XTALC
XTALBxtal[1:0]
mclk
MAX7049plllock
DVDD
INTERNAL
SIGNAL
GROUNDED
PAD (EP)
GROUNDED
PAD (EP)
INTERNAL
SIGNAL
ISINK
ISOURCE
OUTPUT
DVDD
OUTPUT
BUFFER MODECURRENT MODE
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
The current mode of operation can reduce digital noise
associated with large supply current spikes. The GPO1
pin has a relatively small current drive capability (80µA
or 160µA). The IOConf2 register (0x05) (gp1md[1:0] bits)
control the current settings:
gp1md[1:0] Mode
0x Buffer mode
10 80µA sink/source capability
11 160µA sink/source capability
GPO2 has a much larger current drive capability (up to
4mA), as this GPO can be the source of output clock
signals. The IOConf2 register (0x05) (gp2md[2:0] bits)
control the current settings:
gp2md[2:0] Mode
0xx Buffer mode
100 1.0mA sink/source capability
101 2.0mA sink/source capability
110 3.0mA sink/source capability
111 4.0mA sink/source capability
Two other bits also control the operation of GPO1 and
GPO2. The IOConf0 register (0x03) (gp1isht and gp2isht
bits) allows the current mode operation to continue even
if the IC is disabled (Sleep mode).
The GPO2 pin is designated as the primary output for
driving a clock, as it has the strongest buffer and highest
current output capabilities.
The GPO2 clock signal can be selected by the gp2s[3:0]
and ckdiv[1:0] bits (IOConf0 register, 0x03).
gp2s[3:0] GPO2 Output
0000 plllock
0001 mclk/(ckdiv divider)
0010 xtal/(ckdiv divider)
0011 xtal/16/(ckdiv divider)
where the ckdiv divider is given by:
ckdiv[1:0] Divide by
00 1
01 2
10 4
11 8
and xtal is the crystal frequency, and mclk is the master
digital clock. The master digital clock is the divided crystal
frequency given by the xtal[1:0] bits (Conf0 register, 0x01),
according to:
xtal[1:0] Divide by
00 5
01 6
10 7
11 8
If a clock output on GPO2 is required even when the IC
is in Sleep mode (ENABLE pin and enable bit reset to 0),
the SHDN pin is reset to 0, and the clksht bit (IOConf2
register, 0x05, bit 3) must be set to 1.
A very useful function of the GPOs is to output status
signals that reflect the state of the transmitter at any
particular instance in time. See the Register Details
section for an in-depth description of the status signals
available for the TestBus0 and TestBus1 registers.
Serial Peripheral Interface (SPI)
The IC utilizes a 4-wire SPI protocol for programming its
registers, configuring and controlling the operation of the
whole transmitter.
The following digital pins control the operation of the SPI:
CS: Active-low SPI chip select
SDI: SPI data input
SCLK: SPI serial clock
SDO: SPI data output
The SPI operates on a byte format, as shown in Figure 6.
Any number of 8-bit data bursts (Data 1, Data 2, … Data
N) can be sent within one low cycle of CS, to allow for
burst-write or burst-read operations. The SDO pin acts
as another general-purpose output (GPO) when the CS
pin is high.
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
SPI Commands
The following commands are implemented in the IC:
Write: Within the same CS cycle, a write command is implemented as follows:
SDI: <0x01>
…
With this command, Data 1 is written to the address given by , Data 2 is written to 1>, and so on.
Read: Within the same CS cycle, a read command is implemented as follows:
SDI: <0x02> … <0x00>
SDO: <0xXX> <0xXX> …
With this command, all the registers can be read within the same cycle of CS. The addresses can be given in any order.
Read All: With two CS cycles, the Read All command is implemented as follows: CS Cycle 1 CS Cycle 2
SDI: <0x03> <0x00> <0x00> <0x00> … <0x00>
SDO: …
Reset: A SPI reset command is implemented as follows:
SDI: <0x04>
An internal active-low master resetb signal is generated, from the falling edge of the last SCLK signal to the falling edge
of the following CS signal (tHCS + tCSH).
Figure 6. SPI Format
DI7DI6DI5DI4DI3DI2DI1DI0
DO7DO6DO5DO4DO3DO2DO1DO0
DATA 1DATA N
DO7DO6DO5DO4DO3DO2DO1DO0
SCLK
SDI
SDO
DI7DI6DI5DI4DI3DI2DI1DI0
WRITE COMMAND (0x01)A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0D7D0
INITIAL ADDRESS (A[7:0])DATA 1DATA N
SCLK
SDI
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Operating Mode Overview
The IC offers several modes of operation that allow the
user to optimize the transmitter’s power consumption for
a particular application. The primary operating modes
are Initial, Sleep, Temperature Sensor, and Tx, as illus-
When the SHDN pin is high, the IC is in Shutdown mode.
In Shutdown mode, the POR circuit internal to the IC is
disabled and draws virtually no current. In Shutdown
mode, all internal data registers are reset to the initial
states and must be rewritten for desired transmitter
Figure 9. SPI Read-All Command Format
Figure 10. SPI Reset Command FormatFigure 11. Operating Modes
Figure 8. SPI Read Command FormatA6A5A4A3A2A1A0
DATA 1DATA 2DATA N
READ COMMAND (0x02)ADDRESS 1ADDRESS 2ADDRESS N0x00A0A7A6A5A4A3A2A1D6D5D4D3D2D1D0D7D0D0D7
SCLK
SDI
SDO
DATA N + 1DATA NDATA N + n
READ-ALL COMMAND (0x03)A6A5A4A3A2A1A0D6D5D4D3D2D1D0D7D0D0D7
SCLK
SDI
SDO
ADDRESS N
SCLK
SDI
resetb
RESET COMMAND (0x04)
INITIAL
SHUTDOWN
SLEEP
SLEEP
XTAL ON
SPI
CONFIGURATION
FSK
ASK
TEMPERATURE
SENSOR
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
When the SHDN pin is low, the POR circuit is active and
holds the internal data registers in the initial state until the
power supply is above 2.1V and the IC enters the Initial
mode. From the Initial mode, the IC can be configured
for operation in Sleep mode, Temperature Sensor mode,
or Tx mode. In Sleep mode, there are two options avail-
able: Sleep and XTAL ON. In Sleep mode, the current
drain is typically 350nA. All register states are retained in
Sleep mode. In XTAL ON mode, controlled by the clksht
bit (IOConf2 register, 0x05, bit 3), the crystal oscillator is
enabled and the divided output of the crystal oscillator
(/1, /2, /4, /8, as set by the ckdiv[1:0] bits (IOConf0 regis-
ter, 0x03, bits [5:4]) can be directed to GPO2. The XTAL
ON mode is designed so an accurate high-speed clock
is always available to the MCU.
In Temperature Sensor mode, the internal temperature
sensor function can be executed.
In Tx mode, the transmitter can be configured to transmit
ASK data or FSK data.
The Tx mode is determined by the logic states of the
SHDN pin, ENABLE pin, and the enable bit (EnableReg
register, 0x3E, bit 0). The transmitter is enabled if the
SHDN pin is driven low and the ENABLE pin is driven
high, or the enable bit is set. This logic is summarized
in Table 2.
The mode options are selected by the mode SPI bit
(Conf0 register, 0x01, bit 4) and these options are
summarized in Table 3.
Sleep Mode
From the Initial mode, the transmitter directly enters
Sleep mode. In XTAL ON mode, the crystal oscillator is
enabled and the divided output of the crystal oscillator
can be directed to GPO2. This mode is enabled when
the RF functions are disabled and the clksht bit is set.
The current drain in this mode is highly dependent on the
frequency of the output signal and the load capacitance
on the GPO2 pin. The current drain is typically 750µA
when the output signal is 3.2MHz and the load capaci-
tance is 10pF. See the Digital Outputs section for more
details. Table 4 summarizes the Sleep mode functions.
Table 2. Mode Control Logic
Table 3. Mode Option Logic
*Dependent on GPO2 load capacitance and output clock
frequency.
Table 4. Sleep Mode Summary
SHDN PINENABLE PINenable BITTRANSMITTER
MODE00Sleep01Tx10Tx11Tx00Shutdown01Shutdown10Shutdown11Shutdown
mode BITMODE OPTIONASKFSK
SLEEP
MODESETTINGS
TYPICAL
CURRENT
DRAIN
COMMENTS
SleepEnable = 0350nA All register contents
are retained.
XTAL clksht = 1 750FA*
Divided XTAL
oscillator signal can
be directed to GPO2.
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Temperature Sensor Mode
The user must initiate the temperature sensor from Sleep
mode, and the transmitter automatically returns to sleep
when the measurement sequence is completed.
The on-chip temperature sensor is enabled when the
tsensor bit (EnableReg register, 0x3E, bit 3) is set. Once
the internal analog temperature sensor circuit has settled,
an A/D conversion is performed and the resultant ADC
value is stored in the tsadc[6:0] bits that are accessed
through the TestBus1 register (0x41, bits 6:0) when the
digital test mux bits tmux[3:0] (TestMux register, 0x3C,
bits 3:0) are set to 0. The tsensor bit is a self-reset bit,
so it returns to a zero state once the temperature sensor
measurement is completed. The tsdone status bit (Status1
register, 0x43, bit 4) is also set when the measurement
is completed. The current drain in Temperature Sensor
mode is less than 1mA and the sensor settling time plus
the ADC conversion time is less than 2ms. The pertinent
features of the Temperature Sensor mode are summa-
rized in Table 5.
Tx Mode
There are two subsets of the Tx mode. These subsets
include FSK and ASK.
The transmitter output signal is generated by the fractional-N
synthesizer, then buffered, and amplified by the power
amplifier (PA) to the programmed output power level. There
is a finite warmup time for the transmitter. Upon entering Tx
mode from Sleep mode, the following sequence occurs:
1) The crystal oscillator is enabled and settles to a steady
state. The rising edge of the internal ckalive status sig-
nal indicates that the crystal oscillator has settled and
an accurate time base is available. All other Tx modules
are enabled except the PA. The synthesizer settles to
the desired LO frequency at the same time the other
modules settle to their desired operating points.
A rising edge of the lockdet status signal indicates
that the synthesizer has locked. In some narrow-
band applications, the lockdet signal can effectively
be delayed with the plldl[2:0] bits (Conf1 register,
0x02, bits 5:3) to ensure that the synthesizer has
settled to within the desired accuracy. This delayed
signal is called plllock. The rising edge of the txready
status signal is coincident with the rising edge of the
plllock signal.
2) In ASK mode, the power amplifier ramp-up sequence
begins on the rising edge of either the DATAIN pin
or the datain bit after the internal txready signal
transitions high. In FSK mode, the power amplifier
linear ramp-up sequence begins on the rising edge
of the txready signal.
Figure 12 illustrates this warmup sequence.
In an ASK application, the output of the synthesizer
is fixed at the carrier frequency. The output power is
alternated between fully off when both the DATAIN
pin is logic 0 and the datain bit is cleared, and the
programmed output power level when either the DATAIN
Table 5. Temperature Sensor Mode
Summary
ckalive
lockdet
105µs
(typ)
95µs
(typ)
plllock
txready
datain
‘OR’
DATAIN
PAQ*
USER-DEFINED PA RAMP
plldel
INTERVAL
enable
‘OR’
ENABLE
(*PA RAMP BEGINS ON THE RISING EDGE OF DATAIN IN ASK MODE
AND ON THE RISING EDGE OF txready IN FSK MODE.)
BITEXECUTION
TIME (ms)
TYPICAL
CURRENT
DRAIN (mA)
COMMENTS
tsensor< 2< 1
The tsdone status
bit is set when the
measurement is
completed. The
results are stored in
tsadc[6:0].
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
pin is logic 1 or the datain bit is set. The output signal
can be waveshaped in amplitude to reduce the spectral
width of the transmission. See the Power Amplifier section
for more information regarding amplitude waveshaping.
The PA power is determined by the 6-bit amplitude word
that linearly controls the PA output bias current. The LSB
current amplitude is set by an off-chip resistor placed
between the REXTPA pin and ground. The LSB current is
nominally 0.5mA for a 56.2kI resistor and allows for very
tight transmitter power control with a low-temperature
coefficient ±1% tolerance resistor.
In an FSK application, the output of the synthesizer
alternates between the space frequency when both the
DATAIN pin is logic 0 and the datain bit is cleared, and
the mark frequency when either the DATAIN pin is logic 1
or the datain bit is set. The output signal can be wave-
shaped in frequency to reduce the spectral width of the
transmission. See the Fractional-N Synthesizer section
for more information regarding frequency waveshaping.
The PA power is determined by the 6-bit amplitude word.
The PA output power linearly ramps between fully off and
the programmed power when the transmitter is enabled
or disabled. The ramp slope is also programmable. To
transmit the entire message at the desired power level,
the user should wait until the PA ramp is completed
before initiating the data sequence.
The typical current drain in Tx mode is 10.2mA (low-pow-
er buffer mode) or 12.2mA (high-power buffer mode) plus
the programmable PA output current. The buffer power
mode is controlled by the palopwr bit (TxConf0 register,
0x0C, bit 7) and is in low-power mode when the bit is set.
Frequency-Hopping Spread-
Spectrum (FHSS) Operation
The IC is fully capable of FHSS operation. The fast-
settling fractional-N synthesizer and amplitude-shaping
PA work in concert to allow clean, time efficient, and
easy-to-implement frequency hopping under the control
of a low-end MCU.
Figure 13 shows the recommended sequence during
FHSS operation.
Use of the hop bit is preferred during initial configuration.
Use of the HOP pin is preferred over the hop bit during
active transmitter operation. This eliminates the possibility
of SPI activity during active transmitter operation and
allows for exact control of transmitter timing.
Figure 13. Frequency-Hopping Spread-Spectrum (FHSS)
CONFIGUREYES
HOP
INITIAL STATESET fska
TO ZERO
ENABLESLEEP STATEDISABLE
LOAD FIRST
CHANNEL
(FBase)
LOAD SECOND
CHANNEL
(FBase)
SET fska TO
DESIRED VALUE
IF FSK MODE
ENABLE
WARMUPTRANSMITTER
ACTIVITYHOP
RAMPED
DOWN
SYNTHESIZER
FREQUENCY
CHANGED
PA RAMPED
FSK MODE
SYNTHESIZER
FORCED OUT
OF LOCK
**CAN BE COMPLETED IN A SINGLE SPI BURST**
ckalive
TRANSITIONS
HIGH
YES
YES
YES
YES
END
TRANSMITTER
ACTIVITY
LOAD NEXT
CHANNEL
(FBase)
SYNTHESIZER
ACQUIRES LOCK
HOP PIN
HELD
LOGIC 1
FSK
TRANSMITTER
MODE
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
Functional Descriptions
Crystal Oscillator
The IC’s crystal oscillator circuitry is designed to operate
in conjunction with a parallel resonant crystal to generate
the fractional-N synthesizer reference frequency and the
clock signal for the digital control block. Only the crystal,
attached between pins XTALB and XTALC, and two
optional loading capacitors are typically required.
The oscillator typically presents a load capacitance of
approximately 8pF between the pins of the crystal when
PCB stray capacitance is considered. Capacitance
must be added equally from pin XTALC to ground
and pin XTALB to ground to operate the crystal at the
specified crystal load capacitance. If the crystal is
operated at a load capacitance different from the
specified load capacitance, the oscillation frequency
is pulled away from the specified operating frequency,
introducing an error in the fractional-N synthesizer refer-
ence frequency. Crystals specified to operate with higher
load capacitance than the applied load capacitance
oscillate at a higher than specified frequency.
Frequency pulling from the specified operating frequency
can be calculated if the electrical parameters of the crystal
are known. The frequency pulling is given by:MPCASELOADCASESPEC11f102CCCC−=×++
where:
fP is the amount the crystal frequency is pulled in
ppm.
CM is the motional capacitance of the crystal.
CCASE is the case capacitance (includes package
capacitance and crystal blank capacitance).
CSPEC is the specified load capacitance.
CLOAD is the applied load capacitance.
When the crystal is loaded as specified (i.e., CLOAD =
CSPEC), the frequency pulling equals zero.
The oscillator circuitry is designed to operate with crystal
load capacitances between 8pF and 20pF. Operation at
an applied load capacitance of 10pF is recommended for
optimal startup times. Operation with applied load capaci-
tances greater than 20pF can prevent oscillator startup.
The operating range of the crystal oscillator is 16.0MHz
to 22.4MHz. To maintain an internal 3.2MHz time base
mclk, the xtal[1:0] (Conf0 register, 0x01, bits 1:0), must
be programmed as shown in Table 6. The 3.2MHz
internal time base is recommended for all data rates
below 80kbps (Manchester coded) or 160kbps (NRZ
coded). For higher data rates (up to 100kbps (Manchester
coded) or 200kbps (NRZ coded)), a 4MHz internal time
base is needed, as shown in Table 6.
The crystal initial tolerance, temperature coefficient,
and aging must be specified so that the cumulative
error between the transmitter and companion receiver
frequencies allows proper operation. The transmitted
signal must be downconverted by the companion receiver
so that all necessary modulation sidebands are within the
Table 6. Crystal Divider Programming
Figure 14. Recommended Crystal Connection to the IC
OPTIONAL
BLOCKING
CAPACITORS
SHORT IF NOT
REQUIRED
LOADING CAPACITORS
(USED ALONG WITH THE IC INTERNAL CAPACITANCE AND PCB STRAY
CAPACITANCE TO APPLY SPECIFIED LOAD CAPACITANCE TO THE CRYSTAL.)
CBLOCKCBLOCK
CLOADCLOAD
XTALCXTALB12
MAX7049
CRYSTAL FREQUENCY
(MHz)CRYSTAL DIVIDER RATIOxtal[1:0] Conf0 REGISTER,
ADDRESS 0x01, BITS 1:0mclk (MHz)
20.05004.0
MAX7049
High-Performance, 288MHz to 945MHz
ASK/FSK ISM Transmitter
passband of the predemodulation filter to operate properly.
For channelized operation, the transmitted signal, includ-
ing modulation sidebands, must be contained within a
given frequency range, placing limits on the crystal initial
tolerance, temperature coefficient, and aging.
The IC provides a temperature sensor and a fine-step
fractional-N synthesizer to ease crystal frequency stabil-
ity requirements. This sensor can be used by the system
MCU along with the crystal temperature coefficient to
calculate the necessary frequency correction and adjust
the fractional-N synthesizer in fXTAL/216Hz steps.
The IC allows for an external reference signal to be
applied in place of a crystal. The external reference
signal should be applied to pin XTALC through an
AC-coupling capacitor at an amplitude between 0.8VP-P
and 1.2VP-P with pin XTALB DC grounded.
Fractional-N Synthesizer
The IC contains a fully integrated fractional-N synthe-
sizer with the exception of a passive off-chip loop filter
for generating the transmitted signal frequency. This
includes an on-chip voltage-controlled oscillator
(VCO), charge pump, phase-frequency detector (PFD),
fractional-N frequency divider, LO frequency divider,
and all necessary support circuitry. The on-chip
crystal oscillator generates the reference frequency for
the fractional-N synthesizer.
The operating range of the fractional-N synthesizer is
863MHz to 945MHz. The LO frequency divider has
three modes: divide by 1, divide by 2, and divide by 3.
This allows for operation at frequencies of 863MHz
to 945MHz, 431.5MHz to 472.5MHz, and 287.7MHz
to 315MHz, respectively. The frequency resolution is
fXTAL/216 in the 863MHz to 945MHz range, and is
smaller at the LO frequency-divider output by the LO
division ratio. The division ratio of the LO frequency
divider is set by the fsel[1:0] bits (Conf0 register, 0x01,
bits 3:2). These division ratios are shown in Table 7.
The VCO operates over the entire specified frequency
range with no calibration required. The typical VCO gain
is 108MHz/V and the typical phase noise is -126dBc/
Hz at 1MHz offset. The phase noise improves by
20 x log10(2) for divide-by-2 LO frequency-divider
operation, and improves by 20 x log10(3) for divide-
by-3 LO frequency divider operation. The VCO control
voltage is applied at the CTRL pin and is referenced
to the VCOVDD pin. The ibsel bit (Conf1 register, 0x02,
bit 6) sets the VCO bias current. The VCO current
increases by 1mA with the ibsel bit set. The VCO phase
noise improves to -128dBc/Hz at 1MHz offset with the
additional current drain.
The charge pump operates within a typical compliance
range of 0.4V to 0.4V below the supply voltage. The
typical charge-pump current is 204FA with the icont bit
(Conf1 register, 0x02, bit 7) reset. It nearly doubles to 407FA
with icont set. The CPOUT pin is the charge-pump output.
Tx ASK Mode
The fractional-N frequency divider is programmed with
a 21-bit divider word. The divider word consists of a
5-bit integer portion and a 16-bit fractional portion as
illustrated in Figure 15.
The parameter D is the fractional-N divider ratio, where:
D = 32 + base[20:0]/216
and therefore, the synthesizer output frequency is given by:
fSYNTH = D x fXTAL
where fXTAL is the reference frequency generated by the
crystal oscillator.
The 21-bit divider word as defined by the contents of the
FBase0, FBase1, and FBase2 registers is latched into the
fractional-N divider on the rising edge of the Hop signal,
which is the logical OR of the HOP input pin and the hop
bit (FLoad register, 0x0B, bit 0), when the IC is enabled.
Table 7. LO Frequency-Divider Modes
fsel[1:0] Conf0 REGISTER, ADDRESS
0x01, BITS 3:2LO DIVISION RATIOTRANSMITTER OPERATING
FREQUENCIES (MHz)3287.7 to 3152431.5 to 472.5Not usedN/A1863 to 945
