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MAX7032ATJ+
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
General DescriptionThe MAX7032 crystal-based, fractional-N transceiver is
designed to transmit and receive ASK/OOK or FSK
data in the 300MHz to 450MHz frequency range with
data rates up to 33kbps (Manchester encoded) or
66kbps (NRZ encoded). This device generates a typi-
cal output power of +10dBm into a 50Ωload, and
exhibits typical sensitivities of -114dBm for ASK data
and -110dBm for FSK data. The MAX7032 features sep-
arate transmit and receive pins (PAOUT and LNAIN)
and provides an internal RF switch that can be used to
connect the transmit and receive pins to a common
antenna.
The MAX7032 transmit frequency is generated by a 16-
bit, fractional-N, phase-locked loop (PLL), while the
receiver’s local oscillator (LO) is generated by an inte-
ger-N PLL. This hybrid architecture eliminates the need
for separate transmit and receive crystal reference
oscillators because the fractional-N PLL allows the
transmit frequency to be set within 2kHz of the receive
frequency. The 12-bit resolution of the fractional-N PLL
allows frequency multiplication of the crystal frequency
in steps of fXTAL/4096. Retaining the fixed-N PLL for the
receiver avoids the higher current drain requirements of
a fractional-N PLL and keeps the receiver current drain
as low as possible.
The fractional-N architecture of the MAX7032 transmit
PLL allows the transmit FSK signal to be programmed for
exact frequency deviations, and completely eliminates
the problems associated with oscillator-pulling FSK sig-
nal generation. All frequency-generation components are
integrated on-chip, and only a crystal, a 10.7MHz IF filter,
and a few discrete components are required to imple-
ment a complete antenna/digital data solution.
The MAX7032 is available in a small 5mm x 5mm, 32-pin,
thin QFN package, and is specified to operate in the
automotive -40°C to +125°C temperature range.
Applications2-Way Remote Keyless Entry
Security Systems
Home Automation
Remote Controls
Remote Sensing
Smoke Alarms
Garage Door Openers
Local Telemetry Systems
Features+2.1V to +3.6V or +4.5V to +5.5V Single-Supply
OperationSingle Crystal TransceiverUser-Adjustable 300MHz to 450MHz Carrier
FrequencyASK/OOK and FSK ModulationUser-Adjustable FSK Frequency Deviation
Through Fractional-N PLL RegisterAgile Transmitter Frequency Synthesizer with
fXTAL/4096 Carrier-Frequency Spacing+10dBm Output Power into 50ΩLoadIntegrated TX/RX SwitchIntegrated Transmit and Receive PLL, VCO, and
Loop Filter> 45dB Image RejectionTypical RF Sensitivity*
ASK: -114dBm
FSK: -110dBmSelectable IF Bandwidth with External FilterRSSI Output with High Dynamic RangeAutopolling Low-Power Management< 12.5mA Transmit-Mode Current< 6.7mA Receive-Mode Current< 23.5µA Polling-Mode Current < 800nA Shutdown CurrentFast-On Startup Feature, < 250µsSmall 32-Pin, Thin QFN Package
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Ordering Information19-3685; Rev 2; 11/10
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX7032ATJ+-40°C to +125°C32 Thin QFN-EP**
*0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW,
average RFpower
+Denotes a lead(Pb)-free/RoHS-compliant package.
**EP = Exposed pad.
Pin Configuration, Typical Application Circuit, and
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
HVIN to GND.........................................................-0.3V to +6.0V
PAVDD, AVDD, DVDD to GND..............................-0.3V to +4.0V
ENABLE, T/R, DATA, CS, DIO, SCLK, CLKOUT to
GND......................................................-0.3V to (HVIN + 0.3V)
All Other Pins to GND...............................-0.3V to (_VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C above +70°C)....1702mW
Operating Temperature Range.........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
DC ELECTRICAL CHARACTERISTICS(Typical Application Circuit, 50Ωsystem impedance, VAVDD= VDVDD= VPAVDD = VHVIN= +2.1V to +3.6V, fRF= 300MHz to 450MHz,= -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= VPAVDD = VHVIN= +2.7V, TA= +25°C, unless
otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply Voltage (3V Mode)VDDHVIN, PAVDD, AVDD, and DVDD connected to
power supply2.12.73.6V
Supply Voltage (5V Mode)HVINPAVDD, AVDD, and DVDD unconnected from
HVIN, but connected together4.55.05.5V
fRF = 315MHz3.55.4Transmit mode, PA off,
VDATA at 0% duty cycle
(ASK) (Note 2)fRF = 434MHz4.36.7
fRF = 315MHz7.612.3Transmit mode, VDATA
at 50% duty cycle
(ASK) (Notes 3, 4)fRF = 434MHz8.413.6
fRF = 315MHz (Note 4)11.619.1Transmit mode, VDATA
at 100% duty cycle
(FSK)fRF = 434MHz (Note 2)12.420.4
Receiver (ASK 315MHz)6.17.9
Receiver (ASK 434MHz)6.48.3
Receiver (FSK 315MHz)6.48.4
Receiver (FSK 434MHz)6.78.7
DRX (3V mode)23.477.3
DRX (5V mode)67.294.4
Deep-sleep (3V mode)0.88.8
TA < +85°C,
typ at +25°C
(Note 4)
Deep-sleep (5V mode)2.410.9
Receiver (ASK 315MHz)6.48.2
Receiver (ASK 434MHz)6.78.4
Receiver (FSK 315MHz)6.88.7
Receiver (FSK 434MHz)7.08.8
DRX (3V mode)33.5103.0
DRX (5V mode)82.3116.1
Deep-sleep (3V mode)8.034.2
Supply CurrentIDD
TA < +125°C,
typ at +125°C
(Note 2)
Deep-sleep (5V mode)14.939.3
Voltage RegulatorVREGVHVIN = 5V, ILOAD = 15mA3.0V
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
DC ELECTRICAL CHARACTERISTICS (continued)(Typical Application Circuit, 50Ωsystem impedance, VAVDD= VDVDD= VPAVDD = VHVIN= +2.1V to +3.6V, fRF= 300MHz to 450MHz,= -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= VPAVDD = VHVIN= +2.7V, TA= +25°C, unless
otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL I/OInput High ThresholdVIH(Note 2)0.9 x VHVINV
Input Low ThresholdVIL(Note 2)0.1 x VHVINV
Pulldown Sink CurrentSCLK, ENABLE, T/R, DATA (VHVIN = 5.5V)20µA
Pullup Source CurrentDIO, CS (VHVIN = 5.5V)20µA
Output-Low VoltageVOLISINK = 500µA0.15V
Output-High VoltageVOHISOURCE = 500µAVHVIN -
0.26V
AC ELECTRICAL CHARACTERISTICS(Typical Application Circuit, 50Ωsystem impedance, VAVDD= VDVDD= VPAVDD= VHVIN= +2.1V to +3.6V, fRF= 300MHz to 450MHz,= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD= VAVDD= VDVDD= VHVIN= +2.7V, TA= +25°C, unless
otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICSFrequency Range300450MHz
Maximum Input LevelPRFIN0dBm
fRF = 315MHz (Note 6)32Transmit Efficiency 100% Duty
CyclefRF = 434MHz (Note 6)30%
fRF = 315MHz (Note 6)24Transmit Efficiency 50% Duty
CyclefRF = 434MHz (Note 6)22%
ENABLE or T/R transition low to high,
transmitter frequency settled to within
50kHz of the desired carrier
ENABLE or T/R transition low to high,
transmitter frequency settled to within 5kHz
of the desired carrier
350Power-On TimetON
ENABLE transition low to high, or T/R
transition high to low receiver startup time
(Note 5)
RECEIVER
ASK (315MHz)-114
ASK (434MHz)-113
FSK (315MHz)-110Sensitivity
0.2% BER, 4kbps
Manchester data rate,
280kHz IF BW, ±50kHz
FSK deviation,
average powerFSK (434MHz)-107
dBm
Image Rejection(Note 8)46dB
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)(Typical Application Circuit, 50Ωsystem impedance, VAVDD= VDVDD= VPAVDD= VHVIN= +2.1V to +3.6V, fRF= 300MHz to 450MHz,= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD= VAVDD= VDVDD= VHVIN= +2.7V, TA= +25°C, unless
otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER AMPLIFIERTA = +25°C (Note 4)4.610.015.5
TA = +125°C, VAVDD = VDVDD = VHVIN =
VPAVDD = +2.1V (Note 2)3.96.7Output PowerPOUT
TA = -40°C, VAVDD = VDVDD = VHVIN =
VPAVDD = +3.6V (Note 4)13.115.8
dBm
Modulation Depth82dB
Maximum Carrier HarmonicsWith output-matching network-40dBc
Reference Spur-50dBc
PHASE-LOCKED LOOPTransmit VCO GainKVCO340MHz/V
10kHz offset, 200kHz loop BW-68Transmit PLL Phase Noise1MHz offset, 200kHz loop BW-98dBc/Hz
Receive VCO Gain340MHz/V
10kHz offset, 500kHz loop BW-80Receive PLL Phase Noise1MHz offset, 500kHz loop BW-90dBc/Hz
Transmit PLL200Loop BandwidthReceive PLL500kHz
Minimum Transmit Frequency
Step
fXTAL/
4096kHz
Reference Frequency Input Level0.5VP-P
Programmable Divider RangeIn transmit mode (Note 4)2027
LOW-NOISE AMPLIFIER/MIXER (Note 9)fRF = 315MHz1 - j4.7LNA Input ImpedanceZINLNANormalized to
50ΩfRF = 434MHz1 - j3.3
fRF = 315MHz50High-gain statefRF = 434MHz45
fRF = 315MHz13Voltage-Conversion Gain
Low-gain statefRF = 434MHz9
High-gain state-42Input-Referred 3rd-Order
Intercept PointIIP3Low-gain state-6dBm
Mixer Output Impedance330Ω
LO Signal Feedthrough to
Antenna-100dBm
RSSIInput Impedance330Ω
Operating FrequencyfIF10.7MHz
3dB Bandwidth10MHz
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)(Typical Application Circuit, 50Ωsystem impedance, VAVDD= VDVDD= VPAVDD= VHVIN= +2.1V to +3.6V, fRF= 300MHz to 450MHz,= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD= VAVDD= VDVDD= VHVIN= +2.7V, TA= +25°C, unless
otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSGain15mV/dB
FSK DEMODULATORConversion Gain2.0mV/kHz
ANALOG BASEBANDMaximum Data Filter Bandwidth50kHz
Maximum Data Slicer Bandwidth100kHz
Maximum Peak Detector
Bandwidth50kHz
Manchester coded33Maximum Data RateNRZ66kbps
CRYSTAL OSCILLATORCrystal FrequencyfXTAL(fRF - 10.7)/24MHz
Frequency Pulling by VDD2ppm/V
Crystal Load Capacitance(Note 7)4.5pF
SERIAL INTERFACE TIMING CHARACTERISTICS (see Figure 7)Minimum SCLK Setup to Falling
Edge of CStSC30ns
Minimum CS Falling Edge to
SCLK Rising-Edge Setup TimetCSS30ns
Minimum CS Idle TimetCSI125ns
Minimum CS PeriodtCS2.125µs
Maximum SCLK Falling Edge to
Data Valid DelaytDO80ns
Minimum Data Valid to SCLK
Rising-Edge Setup TimetDS30ns
Minimum Data Valid to SCLK
Rising-Edge Hold TimetDH30ns
Minimum SCLK High Pulse WidthtCH100ns
Minimum SCLK Low Pulse WidthtCL100ns
Minimum CS Rising Edge to
SCLK Rising-Edge Hold TimetCSH30ns
Maximum CS Falling Edge to
Output Enable TimetDV25ns
Maximum CS Rising Edge to
Output Disable TimetTR25ns
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)(Typical Application Circuit, 50Ωsystem impedance, VAVDD= VDVDD= VPAVDD= VHVIN= +2.1V to +3.6V, fRF= 300MHz to 450MHz,= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD= VAVDD= VDVDD= VHVIN= +2.7V, TA= +25°C, unless
otherwise noted.) (Note 1)
Note 1:Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match.
Note 2:100% tested at TA= +125°C. Guaranteed by design and characterization overtemperature.
Note 3:50% duty cycle at 10kHz ASK data (Manchester coded).
Note 4:Guaranteed by design and characterization. Not production tested.
Note 5:Time for final signal detection; does not include baseband filter settling.
Note 6:Efficiency = POUT/(VDDx IDD).
Note 7:Dependent on PCB trace capacitance.
Note 8:The oscillator register (0x05) is set to the nearest integer result of fXTAL/100kHz (see the Oscillator Frequency Register
(Address 0x05)section).
Note 9:Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degenera-
tion from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the
LNA source to ground. The equivalent input circuit is approximately 50Ωin series with ~ 2.2pF. The voltage conversion is
measured with the LNA input matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not
include the IF filter insertion loss.
Typical Operating Characteristics(Typical Application Circuit, VPAVDD= VAVDD= VDVDD= VHVIN= +3.0V, fRF= 433.92MHz, TA= +25°C, IF BW = 280kHz, data rate
= 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2% average RF power, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(ASK MODE)MAX7032 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
SUPPLY CURRENT vs. RF FREQUENCY
(ASK MODE)MAX7032 toc02a
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
SUPPLY CURRENT vs. RF FREQUENCY
(FSK MODE)MAX7032 toc02b
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
RECEIVER
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
DEEP-SLEEP CURRENT vs. TEMPERATUREMAX7032 toc03
TEMPERATURE (°C)
DEEP-SLEEP CURRENT (
VCC = +3.6V
VCC = +3.0V
VCC = +2.1V
BIT-ERROR RATE
vs. AVERAGE INPUT POWER (ASK DATA)MAX7030 toc04
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE (%)
fRF = 434MHz
fRF = 315MHz
0.2% BER
BIT-ERROR RATE
vs. AVERAGE INPUT POWER (FSK DATA)MAX7032 toc05
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE (%)
fRF = 434MHz
0.2% BER
fRF = 315MHz
SENSITIVITY (dBm)
SENSITIVITY vs. TEMPERATURE
(ASK DATA)
MAX7032 toc06
TEMPERATURE (°C)
fRF = 434MHz
fRF = 315MHz
SENSITIVITY (dBm)
SENSITIVITY vs. TEMPERATURE
(FSK DATA)
MAX7032 toc07
TEMPERATURE (°C)
fRF = 434MHz
fRF = 315MHz
SENSITIVITY vs. FREQUENCY DEVIATION
(FSK DATA)MAX7032 toc08
FREQUENCY DEVIATION (kHz)
SENSITIVITY (dBm)
RSSI vs. RF INPUT POWER
MAX7032 toc09
RF INPUT POWER (dBm)
RSSI (V)
LOW-GAIN MODE
HIGH-GAIN MODE
AGC SWITCH
POINT
AGC HYSTERESIS: 3dB
RSSI AND DELTA vs. IF INPUT POWERMAX7032 toc10
IF INPUT POWER (dBm)
RSSI (V)
DELTA (%)
RSSI
DELTA
Typical Operating Characteristics (continued)(Typical Application Circuit, VPAVDD= VAVDD= VDVDD= VHVIN= +3.0V, fRF= 433.92MHz, TA= +25°C, IF BW = 280kHz, data rate
= 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2% average RF power, unless otherwise noted.)
RECEIVER
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
FSK DEMODULATOR OUTPUT
vs. IF FREQUENCYMAX7032 toc11
IF FREQUENCY (MHz)
FSK DEMODULATOR OUTPUT (V)
SYSTEM GAIN vs. IF FREQUENCY
MAX7032 toc12
IF FREQUENCY (MHz)
SYSTEM GAIN (dBm)2015105
LOWER SIDEBAND
UPPER SIDEBAND
FROM RFIN
TO MIXOUT
fRF = 434MHz
48dB IMAGE
REJECTION
IMAGE REJECTION vs. TEMPERATUREMAX7032 toc13
IMAGE REJECTION (dB)44
TEMPERATURE (°C)
fRF = 434MHz
fRF = 315MHz
NORMALIZED IF GAIN vs. IF FREQUENCYMAX7032 toc14
IF FREQUENCY (MHz)
NORMALIZED IF GAIN (dB)
S11 vs. RF FREQUENCY
MAX7032 toc15
RF FREQUENCY (MHz)
S11 (dB)
433.92MHz
S11 SMITH PLOT OF RFINMAX7032 toc16
434MHz
500MHz400MHz
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATIONMAX7032 toc17
INDUCTIVE DEGENERATION (nH)
REAL IMPEDANCE (
IMAGINARY IMPEDANCE (
fRF = 315MHz
IMAGINARY
IMPEDANCE
REAL IMPEDANCE
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATIONMAX7032 toc18
INDUCTIVE DEGENERATION (nH)
REAL IMPEDANCE (
IMAGINARY IMPEDANCE (
fRF = 434MHz
IMAGINARY
IMPEDANCE
REAL IMPEDANCE
Typical Operating Characteristics (continued)(Typical Application Circuit, VPAVDD= VAVDD= VDVDD= VHVIN= +3.0V, fRF= 433.92MHz, TA= +25°C, IF BW = 280kHz, data rate
= 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2% average RF power, unless otherwise noted.)
RECEIVER
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
PHASE NOISE vs. OFFSET FREQUENCYMAX7032 toc19
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)100k10k1k
10010M
fRF = 315MHz
PHASE NOISE vs. OFFSET FREQUENCYMAX7032 toc20
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)100k10k1k
10010M
fRF = 434MHz
SUPPLY CURRENT vs. SUPPLY VOLTAGEMAX7032 toc21
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
fRF = 315MHz
PA ON
WITHOUT ENVELOPE SHAPING
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7032 toc22
SUPPLY VOLTAGE (V)
fRF = 315MHz
PA OFF
TA = +85°C
TA = +125°C
TA = -40°CTA = +25°C
SUPPLY CURRENT vs. SUPPLY VOLTAGEMAX7032 toc23
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
fRF = 434MHz
PA ON
WITHOUT ENVELOPE SHAPING
TA = +85°C
TA = +125°CTA = -40°C
TA = +25°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7032 toc24
fRF = 434MHz
PA OFF
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
SUPPLY CURRENT vs. OUTPUT POWERMAX7032 toc25
SUPPLY CURRENT (mA)2-10-6-2
fRF = 315MHz
ENVELOPE SHAPING ENABLED
PA ON
50% DUTY CYCLE
SUPPLY CURRENT vs. OUTPUT POWERMAX7032 toc26
SUPPLY CURRENT (mA)2-2-6-10
fRF = 434MHz
ENVELOPE SHAPING ENABLED
PA ON
50% DUTY CYCLE
Typical Operating Characteristics (continued)(Typical Application Circuit, VPAVDD= VAVDD= VDVDD= VHVIN= +3.0V, fRF= 433.92MHz, TA= +25°C, IF BW = 280kHz, data rate
= 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2% average RF power, unless otherwise noted.)
RECEIVER
TRANSMITTER
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
SUPPLY CURRENT AND OUTPUT POWER
vs. EXTERNAL RESISTORMAX7032 toc27-1
EXTERNAL RESISTOR (Ω)
SUPPLY CURRENT (mA)100110
0.110k
OUTPUT POWER (dBm)
fRF = 315MHz
PA ON
POWER
CURRENT
SUPPLY CURRENT AND OUTPUT POWER
vs. EXTERNAL RESISTORMAX7032 toc27-2
EXTERNAL RESISTOR (Ω)
SUPPLY CURRENT (mA)100110
0.110k
OUTPUT POWER (dBm)
fRF = 434MHz
PA ON
POWER
CURRENT
OUTPUT POWER vs. SUPPLY VOLTAGEMAX7032 28-1
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
fRF = 315MHz
PA ON
ENVELOPE SHAPING DISABLED
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
OUTPUT POWER vs. SUPPLY VOLTAGEMAX7032 28-2
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
fRF = 315MHz
PA ON
ENVELOPE SHAPING ENABLED
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
OUTPUT POWER vs. SUPPLY VOLTAGEMAX7032 29-1
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
fRF = 434MHz
PA ON
ENVELOPE SHAPING DISABLED
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
OUTPUT POWER vs. SUPPLY VOLTAGEMAX7032 29-2
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
fRF = 434MHz
PA ON
ENVELOPE SHAPING ENABLED
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
EFFICIENCY vs. SUPPLY VOLTAGEMAX7032 toc30
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°CfRF = 315MHz
PA ON
EFFICIENCY vs. SUPPLY VOLTAGEMAX7032 toc31
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
fRF = 434MHz
PA ON
Typical Operating Characteristics (continued)(Typical Application Circuit, VPAVDD= VAVDD= VDVDD= VHVIN= +3.0V, fRF= 433.92MHz, TA= +25°C, IF BW = 280kHz, data rate
= 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2% average RF power, unless otherwise noted.)
TRANSMITTER
MAX7032
CLKOUT SPUR MAGNITUDE
vs. SUPPLY VOLTAGEMAX7032 toc38
SUPPLY VOLTAGE (V)
CLKOUT SPUR MAGNITUDE (dBc)
fCLKOUT = fXTAL/8
fCLKOUT = fXTAL/2
fCLKOUT = fXTAL/4
fRF = 434MHz
CLKOUT SPUR = fRF ± fCLKOUT
10pF LOAD CAPACITANCE
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
EFFICIENCY vs. SUPPLY VOLTAGEMAX7032 toc32
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
fRF = 315MHz
50% DUTY CYCLE
EFFICIENCY vs. SUPPLY VOLTAGEMAX7032 toc33
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
fRF = 434MHz
50% DUTY CYCLE
PHASE NOISE vs. OFFSET FREQUENCYMAX7032 toc34
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)100k10k1k
10010M
fRF = 315MHz
PHASE NOISE
vs. OFFSET FREQUENCYMAX7032 toc35
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)100k10k1k
10010M
fRF = 434MHz
REFERENCE SPUR MAGNITUDE
vs. SUPPLY VOLTAGEMAX7032 toc36
SUPPLY VOLTAGE (V)
REFERENCE SPUR MAGNITUDE (dBc)
433.92MHz
315MHz
FREQUENCY STABILITY
vs. SUPPLY VOLTAGEMAX7032 toc37
FREQUENCY STABILITY (ppm)
fRF = 315MHz
fRF = 434MHz
Typical Operating Characteristics (continued)(Typical Application Circuit, VPAVDD= VAVDD= VDVDD= VHVIN= +3.0V, fRF= 433.92MHz, TA= +25°C, IF BW = 280kHz, data rate
= 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2% average RF power, unless otherwise noted.)
TRANSMITTER
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Pin Description
PINNAMEFUNCTIONPAVDDPower-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close
as possible to the pin.ROUT
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close as possible to the inductor with 680pF and 220pF capacitors as shown in the Typical
Application Circuit.TX/RX1Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.TX/RX2Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.PAOUTPower-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which may be part of the output-matching network to an antenna.AVDDAnalog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AVDD to GND with 0.1µF and 220pF capacitors placed as close as possible to the pin.LNAINLow-Noise Amplifier Input. Must be AC-coupled.LNASRCLow-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.LNAOUTLow-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple
to MIXIN+.MIXIN+Noninverting Mixer Input. Must be AC-coupled to the LNA output.MIXIN-Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to LNA LC tank filter.MIXOUT330Ω Mixer Output. Connect to the input of the 10.7MHz filter.IFIN-Inverting 330Ω IF Limiter Amplifier Input. Bypass to GND with a capacitor.IFIN+Noninverting 330Ω IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.PDMINMinimum-Level Peak Detector for Demodulator OutputPDMAXMaximum-Level Peak Detector for Demodulator OutputDS-Inverting Data Slicer InputDS+Noninverting Data Slicer InputOP+Noninverting Op Amp Input for the Sallen-Key Data FilterDFData Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.RSSIBuffered Received-Signal-Strength Indicator OutputT/R
Transmit/ Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down. This function is also controlled by a
configuration register.ENABLEEnable. Drive high for normal operation. Drive low or leave unconnected to put the device into
shutdown mode.DATAReceiver Data Output/Transmitter Data InputCLKOUTDivided Crystal Clock Buffered OutputDVDDDigital Power-Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close as
possible to the pin.
Detailed DescriptionThe MAX7032 300MHz to 450MHz CMOS transceiver
and a few external components provide a complete
transmit and receive chain from the antenna to the digi-
tal data interface. This device is designed for transmit-
ting and receiving ASK and FSK data. All transmit
frequencies are generated by a fractional-N-based syn-
thesizer, allowing for very fine frequency steps in incre-
ments of fXTAL/4096. The receive LO is generated by a
traditional integer-N-based synthesizer. Depending on
component selection, data rates as high as 33kbps
(Manchester encoded) or 66kbps (NRZ encoded) can
be achieved.
Receiver
Low-Noise Amplifier (LNA)The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 30dB of volt-
age gain that is dependent on both the antenna match-
ing network at the LNA input and the LC tank network
between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to GND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible match for low-input
impedance such as a PCB trace antenna. A nominal
value for this inductor with a 50Ωinput impedance is
12nH at 315MHz and 10nH at 434MHz, but the induc-
tance is affected by PCB trace length. LNASRC can be
shorted to ground to increase sensitivity by approxi-
mately 1dB, but the input match must then be reopti-
mized.
The LC tank filter connected to LNAOUT consists of L5
and C9 (see the Typical Application Circuit). Select L5
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where LTOTAL= L5 + LPARASITICSand CTOTAL= C9 +
CPARASITICS.
LPARASITICSand CPARASITICSinclude inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. These
parasitics at high frequencies cannot be ignored and
can have a dramatic effect on the tank filter center fre-
quency. Lab experimentation must be done to optimize
the center frequency of the tank. The total parasitic
capacitance is generally between 5pF and 7pF.
Automatic Gain Control (AGC)When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre-
sponds to an RF input level of approximately -55dBm,
the AGC switches on the LNA gain-reduction attenua-
tor. The attenuator reduces the LNA gain by 36dB,
thereby reducing the RSSI output by about 540mV to
740mV. The LNA resumes high-gain mode when the
RSSI output level drops back below 680mV (approxi-
mately -59dBm at the RF input) for a programmable
interval called the AGC dwell time. The AGC has a hys-
teresis of approximately 4dB. With the AGC function,
the RSSI dynamic range is increased, allowing the
MAX7032 to reliably produce an ASK output for RF
input levels up to 0dBm with a modulation depth of
18dB. AGC is not required and can be disabled in
either ASK or FSK mode. AGC is not necessary for FSK
mode because large received signal levels do not
affect FSK performance.LCTOTALTOTAL
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Pin Description (continued)
PINNAMEFUNCTIONHVIN
High-Voltage Supply Input. For 3V operation, connect HVIN to PAVDD, AVDD, and DVDD. For 5V
operation, connect only HVIN to 5V. Bypass HVIN to GND with 0.01µF and 220pF capacitors placed
as close as possible to the pin.CSSerial Interface Active-Low Chip SelectDIOSerial Interface Serial Data Input/OutputSCLKSerial Interface Clock InputXTAL1Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.XTAL2Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference.EPExposed Pad. Solder evenly to the board’s ground plane for proper operation.
MixerA unique feature of the MAX7032 is the integrated
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., fLO= fRF- fIF). The image-rejection circuit
then combines these signals to achieve a typical 46dB
of image rejection over the full temperature range. Low-
side injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF out-
put is driven by a source follower, biased to create a
driving impedance of 330Ωto interface with an off-chip
330Ωceramic IF filter. The voltage-conversion gain dri-
ving a 330Ωload is approximately 20dB. Note that the
MIXIN+ and MIXIN- inputs are functionally identical.
Integer-N Phase-Locked Loop (PLL)The MAX7032 utilizes a fixed integer-N PLL to generate
the receive LO. All PLL components, including the loop fil-
ter, VCO, charge pump, asynchronous 24x divider, and
phase-frequency detector are integrated on-chip. The
loop bandwidth is approximately 500kHz. The relationship
between RF, IF, and reference frequencies is given by:
fREF = (fRF – fIF)/24
Intermediate Frequency (IF)The IF section presents a differential 330Ωload to pro-
vide matching for the off-chip ceramic filter. The inter-
nal six AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass fil-
ter type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
For ASK data, the RSSI circuit demodulates the IF to
baseband by producing a DC output proportional to
the log of the IF signal level with a slope of approxi-
mately 15mV/dB. For FSK, the limiter output is fed into a
PLL to demodulate the IF. The FSK demodulation slope
is approximately 2.0mV/kHz.
FSK DemodulatorThe FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and converts the fre-
quency deviation into a voltage difference. The PLL is
illustrated in Figure 1. The input to the PLL comes from
the output of the IF limiting amplifiers. The PLL control
voltage responds to changes in the frequency of the
input signal with a nominal gain of 2.0mV/kHz. For exam-
ple, an FSK peak-to-peak deviation of 50kHz generates
a 100mVP-P signal on the control line. This control volt-
age is then filtered and sliced by the baseband circuitry.
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
For more information on calibrating the FSK demodula-
tor, see the Calibrationsection. The maximum calibra-
tion time is 150µs. In discontinuous receive (DRX)
mode, the FSK demodulator calibration occurs auto-
matically just after the IC exits sleep mode, as long as
the ACAL bit is set to 1.
Data FilterThe data filter for the demodulated data is implemented
as a 2nd-order lowpass Sallen-Key filter. The pole loca-
tions are set by the combination of two on-chip resistors
and two external capacitors. Adjusting the value of the
external capacitors changes the corner frequency to
optimize for different data rates. The corner frequency in
kHz should be set to approximately 3 times the fastest
expected Manchester data rate in kbps from the trans-
mitter (1.5 times the fastest expected NRZ data rate) for
ASK. For FSK, the corner frequency should be set to
approximately 2 times the fastest expected Manchester
data rate in kbps from the transmitter (1 times the fastest
expected NRZ data rate). Keeping the corner frequency
near the data rate rejects any noise at higher frequen-
cies, resulting in an increase in receiver sensitivity.
Table 1 lists coefficients to calculate CF1and CF2.
FILTER TYPEabButterworth
(Q = 0.707)1.4141.000
Bessel
(Q = 0.577)1.36170.618
Table 1. Coefficients to Calculate CF1and
CF2
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLLLOOP
FILTER
PHASE
DETECTOR
LIMITING
AMPS
TO FSK BASEBAND FILTER
AND DATA SLICER
10.7MHz VCO
2.0mV/kHz
CHARGE
PUMP
Figure 1. FSK Demodulator PLL Block Diagram
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLLThe configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 1:
where fCis the desired 3dB corner frequency.
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
Choosing standard capacitor values changes CF1to
470pF and CF2to 220pF. In the Typical Application Circuit,
CF1and CF2are named C16 and C17, respectively.
Data SlicerThe data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega-
tive input of the data-slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
3 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
With this configuration, a long string of NRZ zeros or ones
can cause the threshold to drift. This configuration works
best if a coding scheme, such as Manchester coding,
which has an equal number of zeros and ones, is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Peak DetectorsThe maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 4, create DC output voltages equal to
the high and low peak values of the filtered ASK or FSK
demodulated signals. The resistors provide a path for
the capacitors to discharge, allowing the peak detec-
tors to dynamically follow peak changes of the data fil-
ter output voltages.kkHzpFkkHzpF00041410031454504141003145225≈≈.)()(.)())()(.)()bfaC
()()()
()()()
MAX7032
DS-DS+
DATA
SLICER
DATA
Figure 3. Generating Data Slicer Threshold Using a Lowpass
Filter
MAX7032RSSI OR
FSK DEMOD
100kΩ
CF2CF1
100kΩOP+DS+
Figure 2. Sallen-Key Lowpass Data Filter
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLLThe maximum and minimum peak detectors can be
used together to form a data slicer threshold voltage at
a value midway between the maximum and minimum
voltage levels of the data stream (see the Data Slicer
section and Figure 4). The RC time constant of the
peak-detector combining network should be set to at
least 5 times the data period.
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX7032 has a fea-
ture called peak-detector track enable (TRK_EN),
where the peak-detector outputs can be reset (see
Figure 5). If TRK_EN is set (logic 1), both the maximum
and minimum peak detectors follow the input signal.
When TRK_EN is cleared (logic 0), the peak detectors
revert to their normal operating mode. The TRK_EN
function is automatically enabled for a short time when-
ever the IC is first powered up, or transitions from trans-
mit to receive mode, or recovers from the sleep portion
of DRX mode, or when an AGC gain switch occurs
regardless of the bit setting. Since the peak detectors
exhibit a fast-attack/slow-decay response, this feature
allows for an extremely fast startup or AGC recovery.
See Figure 6 for an illustration of a fast-recovery
sequence. In addition to the automatic control of this
function, the TRK_EN bits can be controlled through the
serial interface (see the Serial Control Interfacesection).
Transmitter
Power Amplifier (PA)The PA of the MAX7032 is a high-efficiency, open-
output-matching network can drive a wide range of
antenna impedances, which includes a small-loop PCB
trace and a 50Ωantenna. The output-matching network
for a 50Ωantenna is shown in the Typical Application
Circuit. The output-matching network suppresses the
carrier harmonics and transforms the antenna imped-
ance to an optimal impedance at PAOUT (pin 5). The
optimal impedance at PAOUT is 250Ω.
When the output-matching network is properly tuned,
the PA transmits power with a high overall efficiency of
up to 32%. The efficiency of the PA itself is more than
46%. The output power is set by an external resistor at
PAOUT and is also dependent on the external antenna
and antenna-matching network at the PA output.
MAX7032
PDMIN
TO SLICER
INPUTBASEBAND
FILTER
MINIMUM PEAK
DETECTOR
MAXIMUM PEAK
DETECTOR
PDMAX
TRK_EN = 1
TRK_EN = 1
Figure 5. Peak-Detector Track Enable
Figure 6. Fast Receiver Recovery in FSK Mode Utilizing Peak
Detectors
200mV/div
DATA OUTPUT
2V/div
MIN PEAK DETECTOR
MAX PEAK DETECTOR
RECEIVER ENABLED, TRK_EN SET
TRK_EN CLEARED
FILTER OUTPUT
DATA OUTPUT
100μs/div
MAX7032
PDMAXPDMIN
DATA
SLICER
DATA
PEAK
DET
PEAK
DET
Figure 4. Generating Data Slicer Threshold Using the Peak
Detectors
