MAX691A-MAX800M Fast Delivery |IC PHOENIX CO.,LIMITED

MAX691A ,Microprocessor Supervisory CircuitsFeaturesThe MAX691A/MAX693A/MAX800L/MAX800M micro- ● 200ms Power-OK/Reset Timeout Periodprocessor ( ..
MAX691A ,Microprocessor Supervisory CircuitsElectrical Characteristics(MAX691A, MAX800L: V = +4.75V to +5.5V; MAX693A, MAX800M: V = +4.5V to +5 ..
MAX691A ,Microprocessor Supervisory CircuitsApplications● ComputersPIN- PART TEMP RANGEPACKAGE● ControllersMAX691ACUE -0°C to +70°C 16 TSSOP● I ..
MAX691AC ,Microprocessor Supervisory CircuitsFeaturesThe MAX691A/MAX693A/MAX800L/MAX800M micro-' 200ms Power-OK/Reset Timeout Periodprocessor (µ ..
MAX691ACPE ,Microprocessor Supervisory CircuitsMAX691A/MAX693A/MAX800L/MAX800M19-0094; Rev 7a; 12/96Microprocessor Supervisory Circuits___________ ..
MAX691ACPE+ ,Microprocessor Supervisory CircuitsElectrical Characteristics(MAX691A, MAX800L: V = +4.75V to +5.5V; MAX693A, MAX800M: V = +4.5V to +5 ..
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MB3832A ,DC/DC Converter IC for ChargingFUJITSU SEMICONDUCTORDS04-27701-2EDATA SHEETASSP For Power Management

MAX691A-MAX800M
Microprocessor Supervisory Circuits
General Description
The MAX691A/MAX693A/MAX800L/MAX800M micro-processor (μP) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30μA supply current, 200ms typ reset active delay on power-up, and 6ns chip-enable propagation delay. Features include write protection of CMOS RAM or EEPROM, separate watchdog out-puts, backup-battery switchover, and a RESET output that is valid with VCC down to 1V. The MAX691A/MAX800L have a 4.65V typical reset-threshold voltage, and the MAX693A/MAX800Ms’ reset threshold is 4.4V typical. The MAX800L/MAX800M guarantee power-fail accuracies to ±2%.
Applications●Computers●Controllers●Intelligent Instruments●Critical μP Power Monitoring
Features●200ms Power-OK/Reset Timeout Period●1μA Standby Current, 30μA Operating Current●On-Board Gating of Chip-Enable Signals, 10ns max Delay●MaxCap® or SuperCap Compatible●Guaranteed RESET Assertion to VCC = +1V●Voltage Monitor for Power-Fail or Low-Battery Warning●Power-Fail Accuracy Guaranteed to ±2% (MAX800L/M)●Available in 16-Pin Narrow SO, Plastic DIP, and TSSOP Packages
Ordering Information continued at end of data sheet.
MaxCap is a registered trademark of Kanthal Globar, Inc.
*Dice are specified at TA = +25°C, DC parameters only.
Devices in PDIP, SO, and TSSOP packages are available in
both leaded and lead-free packaging. Specify lead free by add-
ing the + symbol at the end of the part number when ordering.
Lead free not available for CERDIP package.
PARTTEMP RANGEPIN-
PACKAGE
MAX691ACUE-0°C to +70°C16 TSSOPMAX691ACSE-0°C to +70°C16 Narrow SO
MAX691ACWE-0°C to +70°C16 Wide SOMAX691ACPE-0°C to +70°C16 Plastic DIPMAX691AC/D-0°C to +70°CDice*MAX691AEUE-0°C to +70°C16 TSSOPMAX691AESE-40°C to +85°C16 Narrow SOMAX691AEWE-40°C to +85°C16 Wide SO
MAX691AEPE-40°C to +85°C16 Plastic DIP
MAX691A
MAX693A
MAX800L
MAX800M
VOUTVCCBATT ON
CE OUT
CE IN
WDI
PFO
RESET
VBATT
PFI
GND
OSC IN
OSC SEL
ADDRESS
DECODE
AUDIBLEALARM
REGULATOR+8V
0.1µF
CMOS RAM3
A0-A15
I/O
NMI
RESET
LOW LINEWDO
SYSTEM STATUS INDICATORS
CONNECTION
0.47F*
1N4148
*MaxCap14
RESET
RESET
WDO
CE INGND
VCC
VOUT
VBATT
TOP VIEW
MAX691A
MAX693A
MAX800L
MAX800MCE OUT
WDI
PFO
PFIOSC SEL
OSC IN
LOW LINE
BATT ON
DIP/SO/TSSOP
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Ordering Information
Typical Operating Circuit
Pin Coniguration
Terminal Voltage (with respect to GND) VCC......................................................................-0.3V to +6V VVBATT.................................................................-0.3V to +6V All Other Inputs....................................-0.3V to (VOUT + 0.3V)Input Current VCC Peak..........................................................................1.0A VCC Continuous............................................................250mA VBATT Peak..................................................................250mAVBATT Continuous..........................................................25mAGND, BATT ON.............................................................100mAAll Other Outputs ............................................................25mA
Continuous Power Dissipation (TA = +70°C) TSSOP (derate 6.70mW/°C above +70°C)..................533mWNarrow SO (derate 8.70mW/°C above +70°C) ...........696mW Wide SO (derate 9.52mW/°C above +70°C)...............762mW Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW CERDIP (derate 10.00mW/°C above +70°C)..............800mWOperating Temperature Ranges MAX69_AC_ _/MAX800_C_ _............................0°C to +70°C MAX69_AE_ _/MAX800_E_ _.........................-40°C to +85°C MAX69_AMJE................................................-55°C to +125°CStorage Temperature Range .............................-65°C to +160°CLead Temperature (soldering, 10s) .................................+300°C
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXUNITS
Operating Voltage Range, VCC, VVBATT (Note 1)05.5V
VOUT OutputVCC = 4.5V
IOUT = 25mAVCC - 0.02VCC - 0.05IOUT = 250mA
MAX69_ACVCC - 0.2VCC - 0.3
MAX69_AE, MAX800_C/EVCC - 0.2VCC - 0.35
MAX69_A/MVCC - 0.40
IOUT = 210mAMAX69_AC/AE, MAX800_C/EVCC - 0.17VCC - 0.3V
VCC-to-VOUT On-ResistanceVCC = 4.5V
MAX69_AC, MAX800_C0.81.2MAX69_AE, MAX800_E0.81.4
MAX69_A/M0.81.6
VOUT in Battery-BackupMode
VVBATT = 4.5V, IOUT = 20mAVVBATT - 0.3VVBATT = 2.8V, IOUT = 10mAVVBATT - 0.25
VVBATT = 2.0V, IOUT = 5mAVVBATT - 0.15
VBATT-to-VOUTOn-Resistance
VVBATT = 4.5V15VVBATT = 2.8V25
VVBATT = 2.0V30
Supply Current in Normal Operating Mode (excludes
IOUT)VCC > VVBATT - 1V30100µA
Supply Current in Battery-Backup Mode (excludes
IOUT) (Note 2)
VCC < VVBATT - 1.2V, VVBATT = 2.8V
TA = +25°C0.041
TA = TMIN + TMIN5
VBATT Standby Current(Note 3)VVBATT + 0.2V ≤ VCC
TA = +25°C-0.10.02µATA = TMIN + TMIN-1.00.02
Battery Switchover
Power-upVVBATT + 0.3
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXUNITS
Battery Switchover Hysteresis60mV
BATT ON Output Low Voltage
ISINK = 3.2mA0.10.4VISINK = 25mA0.71.5
BATT ON Output Short-Circuit CurrentSink current60100mA
Source current115100µA
RESET AND WATCHDOG TIMER
Reset Threshold Voltage
MAX691A, MAX800L4.504.654.75MAX693A, MAX800M4.254.404.50
MAX800L, TA = +25°C, VCC falling4.554.70
MAX800M, TA = +25°C, VCC falling4.304.45
Reset Threshold Hysteresis15mV
VCC to RESET DelayPower-down80µs
LOW LINE-to-RESET Delay800ns
Reset Active Timeout Period, Internal OscillatorPower-up140200280ms
Reset Active Timeout Period, External Clock (Note 4)Power-up2048Clock Cycles
Watchdog Timeout Period,Internal Oscillator
Long period1.01.62.25sec
Short period70100140ms
Watchdog Timeout Period,External Clock (Note 4)
Long period4096Clock CyclesShort period1024
Minimum Watchdog InputPulse WidthVIL = 0.8V, VIH = 0.75 x VCC100ns
RESET Output Voltage
ISINK = 50μA, VCC = 1V, VBATT = 0V, VCC falling0.0040.3ISINK = 3.2mA, VCC = 4.25V0.10.4
ISOURCE = 1.6mA, VCC = 5V3.5
RESET Output Short-Circuit CurrentOutput source current720mA
RESET Output Voltage Low (Note 5)ISINK = 3.2mA0.10.4V
LOW LINE Output VoltageISINK = 3.2mA, VCC = 4.25V0.4VISOURCE = 1μA, VCC = 5V3.5
LOW LINE OutputShort-Circuit CurrentOutput source current115100µA
WDO Output VoltageISINK = 3.2mA0.4
ISOURCE = 500μA, VCC = 5V3.5
WDO OutputShort-Circuit CurrentOutput source current310mA
WDI Threshold Voltage(Note 6)
VIH0.75 x VCCVVIL0.8
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.
Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V.
Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding IOUT typically goes to 10μA when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region.
Note 3: “+” = battery-discharging current, “--” = battery-charging current.
Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature.
Note 5: RESET is an open-drain output and sinks current only.
Note 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), dis-abling the watchdog function.
Note 7: The chip-enable resistance is tested with VCC = +4.75V for the MAX691A/MAX800L and VCC = +4.5V for the MAX693A/MAX800M. CE IN = CE OUT = VCC/2.
Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
PARAMETERCONDITIONSMINTYPMAXUNITS
POWER-FAIL COMPARATOR
PFI Input ThresholdMAX69_AC/AE/AM, VCC = 5V1.21.251.3VMAX800_C/E, VCC = 5V1.2251.251.275
PFI Leakage Current±0.01±25nA
PFO Output VoltageISINK = 3.2mA0.4VISOURCE = 1μA, VCC = 5V3.5
PFO Output Short-CircuitCurrentOutput source current115100µA
PFI-to-PFO DelayVIN = -20mV, VOD = 15mV25µsVIN = 20mV, VOD = 15mV60
CHIP-ENABLE GATING
CE IN Leakage CurrentDisable mode±0.005±1μA
CE IN-to- CE OUT Resistance (Note 7)Enable mode75150Ω
CE OUT Short-Circuit Current (Reset Active)Disable mode, CE OUT = 0V0.10.752.0mA
CE IN-to- CE OUT Propagation Delay (Note 8)50Ω source impedance driver, CLOAD = 50pF610ns
CE OUT Output-Voltage High (Reset Active)
VCC = 5V, IOUT = -100μA3.5VVCC = 0V, VBATT = 2.8V, IOUT = 1μA2.7
RESET-to-CE OUT DelayPower-down12µs
INTERNAL OSCILLATOR
OSC IN Leakage CurrentOSC SEL = 0V0.10±5µA
OSC IN Input Pullup CurrentOSC SEL = VOUT or loating, OSC IN = 0V10100μA
OSC SEL Input Pullup CurrentOSC SEL = 0V10100μA
OSC IN Frequency RangeOSC SEL = 0V50kHz
OSC IN External OscillatorThreshold Voltage
VIHVOUT - 0.3VOUT - 0.6VVIL3.652.00
OSC IN Frequency withExternal CapacitorOSC SEL = 0V, COSC = 47pF100kHz
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
BATTERY SUPPLY CURRENT
vs. TEMPERATURE
(BATTERY-BACKUP MODE)
MAX691A TOC-02
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT (µA)
VCC = 5V
VBATT = 2.8V
NO LOAD
CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
MAX691A toc03
TEMPERATURE (°C)
CE ON-RESISTANCE (
VCC = 4.75V
VBATT = 2.8V
VCE IN = VCC/2
VBATT to VOUT ON-RESISTANCE
vs. TEMPERATURE
MAX691A toc04
TEMPERATURE (°C)
VBATT-to-V
OUT
ON-RESISTANCE (
VCC = 0V
VBATT = 2.8V
VBATT = 2.0V
VBATT = 4.5V
VCC to VOUT ON-RESISTANCE
vs. TEMPERATURE
MAX691A toc05
TEMPERATURE (°C)
-to-V
OUT
ON-RESISTANCE (
VCC = 5V,
VBATT = 0V
PFI THRESHOLD
vs. TEMPERATURE
MAX691A toc06
TEMPERATURE (°C)
PFI THRESHOLD (V)
VCC = +5V,
VBATT = 0V
NO LOAD ON PFO
RESET THRESHOLD
vs. TEMPERATURE
MAX691A toc07
RESET THRESHOLD (V)
VBATT = 2.8V
MAX691A
MAX800L
MAX693A
MAX800M
VCC SUPPLY CURRENT
vs. TEMPERATURE
(NORMAL OPERATING MODE)
MAX691A toc01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VCC = 5V
VBATT = 2.8V
PFI, CE IN = 0V
RESET OUTPUT RESISTANCE
vs. TEMPERATURE
MAX691A toc08
RESET
OUTPUT RESISTANCE (
VCC = 5V, VBATT = 2.8V
SOURCING CURRENT
VCC = 0V, VBATT = 2.8V
SINKING CURRENT
RESET DELAY
vs. TEMPERATURE
MAX691A toc09
RESET DELAY (ms)
VCC = 0V TO 5V STEP
VBATT = 2.8V
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
BATTERY CURRENT
vs. INPUT SUPPLY VOLTAGE
MAX691A toc10
VCC (V)
IBATT
(µA)25
VBATT = 2.8V
IOUT = 0A
WATCHDOG AND RESET TIMEOUT PERIOD
vs. OSC IN TIMING CAPACITOR (COSC)
MAX691A toc11
COSC (pF)
WATCHDOG AND RESET TIMEOUT PERIOD (sec)
VCC = 5V
VBATT = 2.8V LONG WATCHDOG
TIMEOUT PERIOD
SHORT WATCHDOG
TIMEOUT PERIOD
RESET ACTIVE
TIMEOUT PERIOD300
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
MAX691A toc12
CLOAD (pF)
PROPAGATION DELAY (ns)
VCC = 5V
CE IN = 0V TO 5V
DRIVER SOURCE
VCC TO VOUT vs. OUTPUT CURRENT
(NORMAL OPERATING MODE)
MAX691A toc13
IOUT (mA)
TO V
OUT
(mV)
VCC = 4.5V
VBATT = 0V
SLOPE = 0.8Ω
VBATT TO VOUT vs. OUTPUT CURRENT
(BATTERY-BACKUP MODE)
MAX691A toc14
IOUT (mA)
VBATT to V
OUT
(mV)100
VCC = 0V
VBATT = 4.5V
SLOPE = 8Ω
VCC TO LOW LINE
AND CE OUT DELAY
MAX691A toc15
LOW LINE
VCC RESET
THRESHOLD
CE OUT
RESET
12µs
800ns
80ms
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Typical Operating Characteristics (continued)
Detailed Description
RESET and RESET Outputs
The MAX691A/MAX693A/MAX800L/MAX800M’s RESET and RESET outputs ensure that the μP (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors during power-down or brownout conditions.
The RESET output is active low, and typically sinks 3.2mA
sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to VCC = 1V, and an external 10kΩ pulldown resistor on RESET insures that it will be valid with VCC down to GND (Figure 1). As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10kΩ pulldown resistor insures the parallel combination of switch plus resistor is around 10kΩ and the output
PINNAMEFUNCTIONVBATTBattery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND.VOUT
Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects to VCC. When VCC falls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. Connect VOUT to VCC if no backup battery is used.VCCInput Supply Voltage, 5V Input.GNDGround. 0V reference for all signals.BATT ON
Battery-On Output. When VOUT switches to VBATT, BATT ON goes high. When VOUT switches to VCC, BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current require- ments greater than 250mA.LOW LINELOW LINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold.OSC IN
External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from VOUT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3).OSC SELOscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1). OSC SEL has a 10µA internal pull-up.PFIPower-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V,
PFO goes low. When PFI is not used, connect PFI to GND or VOUT.PFOPower-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry.WDI
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time- out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran- sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and GND, which sets it to mid-supply when left unconnected.CE OUTChip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs irst.CE INChip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or VOUT.WDOWatchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI
is unconnected.RESETRESET Output goes low whenever VCC falls below the reset threshold. RESET will remain low typically for200ms after VCC crosses the reset threshold on power-up.RESETRESET is an active-high output. It is open drain, and the inverse of RESET.
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Pin Description
For battery voltages ≥ 2V connected to VBATT, RESET and RESET remain valid for VCC from 0V to 5.5V.
RESET and RESET are asserted when VCC falls below the reset threshold (4.65V for the MAX691A/MAX800L, 4.4V for the MAX693A/MAX800M) and remain asserted for 200ms typ after VCC rises above the reset threshold on power-up (Figure 5). The devices’ batteryswitchover comparator does not affect reset assertion. However, both reset outputs are asserted in batterybackup mode since VCC must be below the reset threshold to enter this mode.
Watchdog Function
The watchdog monitors μP activity via the Watchdog Input (WDI). If the μP becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or μP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal),
WDO, RESET, and RESET are asserted (see RESET and RESET Outputs section, and the Watchdog Output discussion on this page).
Watchdog Input
A change of state (high to low, low to high, or a minimum 100ns pulse) at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6s.
To disable the watchdog function, leave WDI floating. An internal resistor network (100kΩ equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal com-parators detect this level and disable the watchdog timer. When VCC is below the reset threshold, the watchdog
function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance.
Watchdog Output
The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when VCC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, RESET and RESET are asserted for the reset timeout period (200ms typical).
WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic.
Selecting an Alternative
Watchdog and Reset Timeout Period
The OSC SEL and OSC IN inputs control the watchdog and reset timeout periods. Floating OSC SEL and OSC IN or tying them both to VOUT selects the nominal 1.6s watchdog timeout period and 200ms reset timeout period. Connecting OSC IN to GND and floating or connecting OSC SEL to VOUT selects the 100ms normal watchdog timeout delay and 1.6s delay immediately after reset. The reset timeout delay remains 200ms (Figure 2). Select alter-native timeout periods by connecting OSC SEL to GND and connecting a capacitor between OSC IN and GND, or by externally driving OSC IN (Table 1 and Figure 3). OSC IN is internally connected to a ±100nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watch-
Figure 1. Adding an external pulldown resistor ensures RESET
is valid with VCC down to GND.
Figure 2. Watchdog Timeout Period and Reset Active Time
MAX691A
MAX693A
TO µP RESET
1kΩRESET
WDI
WDO
RESETt1t1
t1 = RESET TIMEOUT PERIOD
t2 = NORMAL WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
dog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications Information section).
Chip-Enable Signal Gating
The MAX691A/MAX693A/MAX800L/MAX800M provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. All these parts use a series transmission gate from CE IN to CE OUT (Figure 4).
The 10ns max CE propagation delay from CE IN to CE OUT enables the parts to be used with most μPs.
Chip-Enable Input
The Chip-Enable Input (CE IN) is high impedance (dis-abled mode) while RESET and RESET are asserted.
During a power-down sequence where VCC falls below the reset threshold or a watchdog fault, CE IN assumes a high-impedance state when the voltage at CE IN goes
high or 15μs after reset is asserted, whichever occurs first (Figure 5).
During a power-up sequence, CE IN remains high imped-ance, regardless of CE IN activity, until reset is deas-serted following the reset timeout period.
In the high-impedance mode, the leakage currents into this terminal are ±1μA max over temperature. In the low-impedance mode, the impedance of CE IN appears as a 75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission gate depends on both the source impedance of the drive to
CE IN and the capacitive loading on the Chip-Enable Output (CE OUT) (see Chip-Enable Propagation Delay vs. CE OUT Load Capacitance in the Typical Operating
Characteristics). The CE propagation delay is production tested from the 50% point of CE IN to the 50% point of
CE OUT using a 50Ω driver and 50pF of load capacitance (Figure 6). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equivalent to 75Ω in series with the source driving CE IN. In the disabled mode, the 75Ω transmission gate is off and
CE OUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled.
LOW LINE Output
LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2mA at 0.1V. For normal operation (VCC above the LOW LINE threshold),
LOW LINE is pulled to VOUT.
Power-Fail Comparator
The power-fail comparator is an uncommitted compara-tor that has no effect on the other functions of the IC. Common uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating
Circuit).
Figure 3. Oscillator Circuits
Table 1. Reset Pulse Width and Watchdog Timeout Selections
OSC SELOSC INWATCHDOG TIMEOUT PERIODRESET TIMEOUT
PERIODNORMALIMMEDIATELY AFTER RESET
LowExternal Clock Input1024 clks4096 clks2048 clks
LowExternal Capacitor(600/47pF x C)ms(2.4/47pF x C)sec(1200/47pF x C)ms
FloatingLow100ms1.6s200ms
FloatingFloating1.6s1.6s200ms
OSC SEL
OSC IN7
EXTERNAL
OSCILLATOR
OSC SEL
OSC IN7
EXTERNAL
CLOCK
OSC SEL
OSC IN7
INTERNAL OSCILLATOR
100ms WATCHDOG
OSC SEL
OSC IN7
INTERNAL OSCILLATOR
1.6s WATCHDOG
MAX691A
MAX693A
MAX800LMAX800M
N.C.N.C.
N.C.
50kHz
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits

Partno	Mfg	Dc	Qty	Available	Descript
MAX691A	MAX	N/a	289	avai	Microprocessor Supervisory Circuits
MAX691A		N/a	460	avai	Microprocessor Supervisory Circuits
MAX691A	MAXIM	N/a	123	avai	Microprocessor Supervisory Circuits
MAX800M		N/a	25	avai	Microprocessor Supervisory Circuits