MAX6902ETA-MAX6902ETA+-MAX6902ETA+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX6902ETA+T ,SPI-Compatible RTC in a TDFNELECTRICAL CHARACTERISTICS(V = +2.0V to +5.5V, T = -40°C to +85°C. Typical values are at V = +3.3V, ..
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MAX6902ETA-MAX6902ETA+-MAX6902ETA+T
SPI-Compatible RTC in a TDFN
General Description
The MAX6902 SPI™-compatible real-time clock con-
tains a real-time clock/calendar and 31 x 8 bits of static
random-access memory (SRAM). The real-time
clock/calendar provides seconds, minutes, hours, day,
date, month, year, and century information. A time/date
programmable polled ALARM is included in the
MAX6902. The end-of-the-month date is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year up to the year 2100. The clock
operates in either the 24hr or 12hr format with an
AM/PM indicator. The MAX6902 operates with a supply
voltage of +2V to +5.5V, is available in the ultra-small
8-pin TDFN package, and works over the -40°C to
+85°C industrial temperature range.
Applications
Point-of-Sale Equipment
Intelligent Instruments
Fax Machines
Battery-Powered Products
Portable Instruments
FeaturesReal-Time Clock Counts Seconds, Minutes, Hours,
Day of Week, Date of Month, Month, Year, and CenturyLeap-Year Compensation Valid up to Year 2100+2V to +5.5V Wide Operating Voltage RangeSPI Interface: 4MHz at 5V; 1MHz at 2V31 x 8-Bit SRAM for Scratchpad Data StorageUses Standard 32.768kHz, 12.5pF Watch CrystalLow Timekeeping Current (400nA at 2V)Single-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
SRAMUltra-Small 8-Pin 3mm x 3mm x 0.8mm TDFN
Package Programmable Time/Date Polled ALARM FunctionNo External Crystal Bias Resistors or Capacitors
Required
MAX6902
SPI-Compatible RTC in a TDFN
Pin Configuration
Ordering Information
Typical Operating Circuit
19-2134; Rev 3; 1/08
PARTTEMP RANGEPIN-
PACKAGE
TOP
MARK
MAX6902ETA+T-40°C to +85°C8 TDFN+AGT
VCCGNDDOUT
DIN
SCLK
TDFN
TOP VIEW
MAX6902
EXPOSED PADDLE
MAX6902
+3.3V
+3.3V
GND
VCC
0.1μF5
SCLK
32.768kHz
CRYSTAL
DOUT
DIN
SPI is a trademark of Motorola, Inc.
PARTSERIAL
INTERFACESRAMALARM
FUNCTION
OUTPUT
FREQUENCY
PIN-
PACKAGE
MAX6900I2C compatible31 ✕ 8——6 TDFN
MAX69013 Wire31 ✕ 8Polled32kHz8 TDFN
MAX6902SPI compatible31 ✕ 8Polled—8 TDFN
Related Real-Time Clock Products
+Denotes lead-free package.
MAX6902
SPI-Compatible RTC in a TDFN
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +2.0V to +5.5V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND..............................................................-0.3V to +6V
All Other Pins to GND ................................-0.3V to (VCC+ 0.3V)
Current into Any Pin..........................................................±20mA
Rate of Rise, VCC............................................................100V/µs
Continuous Power Dissipation (TA= +70°C)
8-Pin TDFN (derate 24.4mW/°C above +70°C)..........1951.0mW
Junction Temperature .....................................................+150°C
Storage Temperature Range…………………… -65°C to +150°C
ESD Protection (all pins, Human Body Model)..................2000V
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Voltage
RangeVCC25.5V
VCC = +2V0.3Active Supply Current
(Note 2)ICCVCC = +5V1.1mA
VCC = +2V0.41.05
VCC = +3.6V0.82.1Timekeeping Supply
Current (Note 3)ITK
VCC = +5V1.34.2
SPI DIGITAL INPUTS (SCLK, DIN, CS)
VCC = +2V1.4Input High VoltageVIHVCC = +5V2.2V
VCC = +2V0.6Input Low VoltageVILVCC = +5V0.8V
Inp ut Leakag e C ur r entIILVIN = 0 to VCC-1010nA
Input Capacitance10pF
SPI DIGITAL OUTPUTS (DOUT)utp ut C ap aci tance15pF
VCC = +2.0V, ISINK = 1.5mA0.4Output Low VoltageVOLVCC = +5.0V, ISINK = 4mA0.4V
VCC = +2.0V, ISOURCE = -0.4mA1.8Output High VoltageVOHVCC = +5.0V, ISOURCE = -1mA4.5V
MAX6902
SPI-Compatible RTC in a TDFN
AC ELECTRICAL CHARACTERISTICS
(VCC= +2.0V to +5.5V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Figure 5,
Notes 1, 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OSCILLATOR
X1 to Ground
Capacitance25pF
X2 to Ground
Capacitance25pF
SPI SERIAL TIMING
Maximum Input Rise
TimetrINDIN, SCLK, CS2μs
Maximum Input Fall
TimetfINDIN, SCLK, CS2μs
Output Rise TimetrOUTDOUT, CLOAD = 100pF10ns
Output Fall TimetfOUTDOUT, CLOAD = 100pF10ns
VCC = +2V1000SCLK PeriodtCPVCC = +5V238ns
SCLK High TimetCH100ns
SCLK Low TimetCL100ns
SCLK Fall to DOUT
ValidtDOCLOAD = 100pF100ns
DIN to SCLK Setup
TimetDS100ns
DIN to SCLK Hold
TimetDH2ns
SCLK Rise to CS
Rise Hold TimetCSH2ns
CS High Pulse WidthtCSW200ns
CS High to DOUT
High ImpedancetCSZ100ns
CS to SCLK Setup
TimetCSS100ns
Note 1:All parameters are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and characterization and
not production tested.
Note 2:ICCis specified with DOUT open, CS= DIN = GND, SCLK = 4MHz at VCC= +5V; SCLK = 1MHz at VCC= +2.0V.
Note 3:Timekeeping current is specified with CS= VCC, SCLK = DIN = GND, DOUT = 100kΩto GND.
Note 4:All values referred to VIHmin and VILmax levels.
Detailed Description
The MAX6902 is a real-time clock/calendar with an SPI-
compatible interface and 31 x 8 bits of SRAM. It pro-
vides seconds, minutes, hours, day of the week, date of
the month, month, and year information, held in seven 8-
bit timekeeping registers (Functional Diagram). An on-
chip 32.768kHz oscillator circuit requires only a single
external crystal to operate. Table 1 specifies the para-
meters for the external crystal, and Figure 1 shows a
functional schematic of the oscillator circuit. The
MAX6902’s register addresses and definitions are
described in Figure 2 and in Table 2. Time and calendar
data are stored in the registers in binary-coded decimal
(BCD) format. A polled alarm function is included for
scheduled timing of user-defined times or intervals.
MAX6902
SPI-Compatible RTC in a TDFN
Pin Description
PINNAMEFUNCTIONSCLKSerial Clock Input. SPI clock for DIN and
DOUT data transfers.DOUTSPI Data OutputDINSPI Data InputGNDGroundCSChip Select Input. Active low for valid data
transfers.
6VCCPower-Supply Pin. Bypass VCC to GND
with a 0.1µF capacitor.X2External 32.768kHz CrystalX1External 32.768kHz Crystal
—EP
Exposed Paddle. Internally connected to
GND. Connect to GND, but do not use as
the sole ground connection point or leave
unconnected.
PARAMETERSYMBOLMINTYPMAXUNITS
Frequencyf32.768kHz
Equivalent
Series
Resistance
(ESR)4060kΩ
Parallel Load
CapacitanceCL11.212.513.7pF
Q FactorQ40,00060,000
MAX6902X2
25pF25pF
EXTERNAL
CRYSTAL
Figure 1. Crystal Oscillator Circuit Schematic
Table 1. Acceptable Quartz Crystal
Parameters
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
MAX6902 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
2.03.54.02.53.04.55.05.5ypical Operating Characteristic
(TA = +25°C, unless otherwise noted.)
MAX6902
SPI-Compatible RTC in a TDFN
Figure 2. Register Address Definition (Sheet 1 of 3)
REGISTER ADDRESSREGISTER DEFINITION
FUNCTIONA7A6A5A4A3A2A1A0VALUED7D6D5D4D3D2D1D0
CLOCK
SECONDSRD000000100-59010 SEC1 SEC*POR STATE00000000
MINUTESRD000001100-59ALM
OUT10 MIN1 MIN*POR STATE00000000
HOURSRD000010100-2312/241001-121/0A/P
0/11 HR
*POR STATE00000000
DATERD0000111
01-28/29
0-31010 DATE1 DATE*POR STATE00000001
MONTHRD000100101-1200010M1 MONTH*POR STATE00000001
DAYRD000101101-0700000WEEK DAY*POR STATE00000001
YEARRD000110100-9910 YEAR1 YEAR*POR STATE01110000
CONTROLRD0001111WP0000000*POR STATE00000000
CENTURYRD001001100-991000 YEAR100 YEAR*POR STATE00011001
Note: *POR STATE d efi nes p ow er - on r eset state of r eg i ster contents.
MAX6902
SPI-Compatible RTC in a TDFN
REGISTER ADDRESSREGISTER DEFINITION
FUNCTIONA7A6A5A4A3A2A1A0VALUED7D6D5D4D3D2D1D0
ALARM
CONFIGRD00101010
YEAR
DAY
MONTH
DATE
HOUR
MINUTE
SECOND*POR STATE00000000
RESERVEDRD001011100000111
Do not write
to this location./W*POR STATE00000111
ALARM
THRESHOLDS
SECONDSRD001100100-59010 SEC1 SEC*POR STATE01111111
MINUTESRD001101100-59010 MIN1 MIN*POR STATE01111111
HOURSRD001110100-2312/241001-121/0A/P
0/1
1 HR
*POR STATE10111111
DATERD0011111
01-28/29
01-31010 DATE1 DATE*POR STATE00111111
MONTHRD010000101-1200010M1 MONTH*POR STATE00011111
DAYRD010001101-0700000WEEK DAY*POR STATE00000111
YEARRD010010100-9910 YEAR1 YEAR*POR STATE11111111
CLOCK
BURSTRD0111111
Figure 2. Register Address Definition (Sheet 2 of 3)
MAX6902
SPI-Compatible RTC in a TDFN
REGISTER ADDRESSREGISTER DEFINITION
FUNCTIONA7A6A5A4A3A2A1A0VALUED7D6D5D4D3D2D1D0
RAM
RAM 0RD1000001RAM DATA 0xxxxxxxx••••••
RAM 30RD1111101RAM DATA 30xxxxxxxx
RAM BURSTRD1111111
Note: *POR STATE defines power-on reset state of register contents.
Figure 2. Register Address Definition (Sheet 3 of 3)
Table 2. Register Address and Description
WRITE (HEX)READ (HEX)DESCRIPTIONPOR CONTENTS (HEX)81Seconds0083Minutes0085Hours0087Date0189Month018BDay018DYear708FControl0093Century1995Alarm Configuration0097Reserved0799Seconds Alarm Threshold7F9BMinutes Alarm Threshold7F9DHours Alarm ThresholdBF9FDate Alarm Threshold3FA1Month Alarm Threshold1FA3Day Alarm Threshold07A5Year Alarm ThresholdFFBFClock BurstNot applicable
MAX6902
SPI-Compatible RTC in a TDFN
Table 2. Register Address and Description (continued)
WRITE (HEX)READ (HEX)DESCRIPTIONPOR CONTENTS (HEX)C1RAM 0IndeterminateC3RAM 1IndeterminateC5RAM 2IndeterminateC7RAM 3IndeterminateC9RAM 4IndeterminateCBRAM 5IndeterminateCDRAM 6IndeterminateCFRAM 7IndeterminateD1RAM 8IndeterminateD3RAM 9IndeterminateD5RAM 10IndeterminateD7RAM 11IndeterminateD9RAM 12IndeterminateDBRAM 13IndeterminateDDRAM 14IndeterminateDFRAM 15IndeterminateE1RAM 16IndeterminateE3RAM 17IndeterminateE5RAM 18IndeterminateE7RAM 19IndeterminateE9RAM 20IndeterminateEBRAM 21IndeterminateEDRAM 22IndeterminateEFRAM 23IndeterminateF1RAM 24IndeterminateF3RAM 25IndeterminateF5RAM 26IndeterminateF7RAM 27IndeterminateF9RAM 28IndeterminateFBRAM 29IndeterminateFDRAM 30IndeterminateFFRAM BurstNot applicable
MAX6902
SPI-Compatible RTC in a TDFN
Command and Control
Address/Command Byte
Each data transfer into or out of the MAX6902 is initiated
by an Address/Command byte. The Address/Command
byte specifies which registers are to be accessed, and
if the access is a read or a write. Figure 2 shows the
Address/Command bytes and their associated regis-
ters, and Table 2 lists the hex codes for all read and
write operations. The Address/Command bytes are
input MSB (bit 7) first. Bit 7 specifies a write (logic 0) or
read (logic 1). Bit 6 specifies register data (logic 0) or
RAM data (logic 1). Bits 5–1 specify the designated reg-
ister to be written or read. The LSB (bit 0) must be logic
1. If the LSB is a zero, writes to the MAX6902 are dis-
abled.
Clock Burst Mode
Sending the Clock Burst Address/Command (3Fh for
Write and BFh for Read), specifies burst-mode opera-
tion. In this mode, multiple bytes are read or written
after a single Address/Command. The first seven
clock/calendar registers (Seconds, Minutes, Hours,
Date, Month, Day, and Year) and the Control register
are consecutively read or written, starting with the MSB
of the Seconds register. When writing to the clock reg-
isters in burst mode, all seven clock/calendar registers
and the Control register must be written in order for the
data to be transferred. See Example: Setting the Clock
with a Burst Write.
RAM Burst Mode
Sending the RAM Burst Address/Command (F7h for
Write, FFh for Read) specifies burst-mode operation. In
this mode, the 31 RAM locations can be consecutively
read or written, starting at 41h for Writes, and C1h for
Reads. A Burst Read outputs all 31 bytes of RAM.
When writing to RAM in burst mode, it is not necessary
to write all 31 bytes for the data to transfer; each com-
plete byte written is transferred to RAM. When reading
from RAM, data are output until all 31 bytes have been
read, or until CSis driven high.
Setting the Clock
Writing to the Timekeeping Registers
The time and date are set by writing to the timekeeping
registers (Seconds, Minutes, Hours, Date, Month, Day,
Year, and Century). During a write operation, an input
buffer accepts the new time data while the timekeeping
registers continue to increment normally, based on the
crystal counter. The buffer also keeps the timekeeping
registers from changing as the result of an incomplete
write operation, and collision-detection circuitry
ensures that a Time Write does not occur coincident
with a Seconds register increment. The updated time
data are loaded into the timekeeping registers after the
rising edge of CS, at the end of the SPI write operation.
An incomplete write operation aborts the update proce-
dure, and the contents of the input buffer are discard-
ed. The timekeeping registers reflect the new time
beginning with the first Seconds register increment
after the rising edge of CS.
Although both Single Writes and Burst Writes are possi-
ble, the best way to write to the timekeeping registers is
with a Burst Write. With a Burst Write, the main time-
keeping registers (Seconds, Minutes, Hours, Date,
Month, Day, Year) and the Control register are written
sequentially following the Address/Command byte.
They must be written as a group of eight registers, with
8 bits each, for proper execution of the Burst Write
function. All seven timekeeping registers are simultane-
ously loaded into the clock counters by the rising edge
of CS, at the end of the SPI write operation. For a nor-
mal burst data transfer, the worst-case error that can
occur between the actual time and the written time
update is 1s.
If single write operations are used to enter data into the
timekeeping registers, error checking is required. If not
writing to the Seconds register, begin by reading the
Seconds register and save it as initial-seconds. Then
write to the required timekeeping registers, and finally
read the Seconds register again (final-seconds). Check
to see that final-seconds is equal to initial-seconds. If
not, repeat the write process. If writing to the Seconds
register, update the Seconds register first, and then
read it back and store its value (initial-seconds).
Update the remaining timekeeping registers and then
read the Seconds register again (final-seconds). Check
to see that final-seconds is equal to initial-seconds. If
not, repeat the write process.
Note:After writing to any time or date register, no read
or write operations are allowed for 45µs.
AM/PM and 12Hr/24Hr Mode
Bit 7 of the Hours register selects 12hr or 24hr mode.
When high, 12hr mode is selected. In 12hr mode, bit 5 is
the AM/PM bit, logic high for PM. In 24hr mode, bit 5 is
the second 10hr bit, logic high for hours 20 through 23.
Write-Protect Bit
Bit 7 of the Control register is the Write-Protect bit.
When high, the Write-Protect bit prevents write opera-
tions to all registers except itself. After initial settings
are written to the timekeeping registers, set the Write-
Protect bit to logic 1 to prevent erroneous data from
entering the registers during power glitches or inter-
rupted serial transfers. The lower 7 bits (bits 0–6) are
MAX6902
SPI-Compatible RTC in a TDFN
unusable, and always read zero. Any data written to
bits 0–6 are ignored. Bit 7 must be set to zero before a
single write to the clock, before a write to RAM, or dur-
ing a Burst Write to the clock.
Example: Setting the Clock
with a Burst Write
To set the clock to 10:11:31PM, Thursday July 4th,
2002 with a burst write operation, write 3Fh as the
Address/Command byte, followed by 8 bytes, 31h, 11h,
B0h, 04h, 07h, 05h, 02h, and 00h (Figure 2). 3Fh is the
Clock Burst Write Address/Command. The first byte,
31h, sets the Seconds register to 31. The second byte,
11h, sets the Minutes register to 11. The third byte,
B0h, sets the Hours register to 12hr mode, and 10PM.
The fourth byte, 04h, sets the Date register (day of the
month) to the 4th. The fifth byte, 07h, sets the Month
register to July. The sixth byte, 05h, sets the Day regis-
ter (day of the week) to Thursday. The seventh byte,
02h, sets the Year register to 02. The eighth byte, 00h,
clears the Write-Protect bit of the Control register to
allow writing to the MAX6902. The Century register is
not accessed with a Burst Write and therefore must be
written to separately to set the century to 20. Note the
Century register corresponds to the thousand and hun-
dred digits of the current year and defaults to 19.
Reading the Clock
Reading the Timekeeping Registers
The main timekeeping registers (Seconds, Minutes,
Hours, Date, Month, Day, Year) can be read with either
Single Reads or a Burst Read. In the MAX6902, a latch
buffers each clock counter’s data. Clock counter data
are latched by the SPI Read Command (on the falling
edge of SCLK, after the Address/Command byte has
been sent by the master to read a timekeeping regis-
ter). Collision-detection circuitry ensures that this does
not happen coincident with a Seconds counter incre-
ment to ensure accurate time data are being read. The
clock counters continue to count and keep accurate
time during the read operation.
The simplest way to read the timekeeping registers is to
use a Burst Read. In a Burst Read, the main timekeep-
ing registers (Seconds, Minutes, Hours, Date, Month,
Day, Year), and the Control register are read sequen-
tially, in the order listed with the Seconds register first.
They are read out as a group of eight registers, with 8
bits each. All timekeeping registers (except Century)
are latched upon the receipt of the Burst Read com-
mand. The worst-case error between the “actual” time
and the “read” time is 1s for a normal data transfer.
The timekeeping registers may also be read using
Single Reads. If Single Reads are used, it is necessary
to do some error checking on the receiving end,
because it is possible that the clock counters could
change during the Read operations, and report inaccu-
rate time data. The potential for error is when the
Seconds register increments before all the registers are
read. For example, suppose a carry of 13:59:59 to
14:00:00 occurs during single read operations. The net
data read could be 14:59:59, which is erroneous. To
prevent errors from occurring with single read opera-
tions, read the Seconds register first (initial-seconds)
and store this value for future comparison. After the
remaining timekeeping registers have been read,
reread the Seconds register (final-seconds). Check that
the final-seconds value equals the initial-seconds
value. If not, repeat the entire Single Read process.
Using Single Reads at a 100kHz serial speed, it takes
under 2.5ms to read all seven of the timekeeping regis-
ters, including two reads of the Seconds register.
Example: Reading the Clock
with a Burst Read
To read the time with a Burst Read, send BFh as the
Address/Command byte. Then clock out 8 bytes,
Seconds, Minutes, Hours, Date of the month, Month,
Day of the week, Year, and finally the Control byte. All
data are output MSB first. Decode the required informa-
tion based on the register definitions listed in Figure 2.
Using the Alarm
A polled alarm function is available by reading the ALM
OUT bit. The ALM OUT bit is D7 of the Minutes timekeep-
ing register. A logic 1 in ALM OUT indicates the Alarm
function is triggered. There are eight registers associated
with the alarm function—seven programmable Alarm
Threshold registers and one programmable Alarm
Configuration register. The Alarm Configuration register
determines which Alarm Threshold registers are com-
pared to the timekeeping registers, and the ALM OUT bit
sets if the compared registers are equal. Figure 2 shows
the function of each bit of the Alarm Configuration regis-
ter. Placing a logic 1 in any given bit of the Alarm
Configuration register enables the respective alarm func-
tion. For example, if the Alarm Configuration register is set
to 0000 0011, ALM OUT is set when both the minutes and
seconds indicated in the Alarm Threshold registers match
the respective timekeeping registers. Once set, ALM OUT
stays high until it is cleared by reading or writing to the
Alarm Configuration register, or by reading or writing to
any of the Alarm Threshold registers. The Alarm
Configuration register is written with address 15h, and
read with address 95h.

Partno	Mfg	Dc	Qty	Available	Descript
MAX6902ETA	MAXIM	N/a	163	avai	SPI-Compatible RTC in a TDFN
MAX6902ETA+ \|MAX6902ETA	MAXIM	N/a	127	avai	SPI-Compatible RTC in a TDFN
MAX6902ETA+T \|MAX6902ETAT	MAXIM	N/a	17500	avai	SPI-Compatible RTC in a TDFN